IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO.
6, JUNE 2012
A 5-Gb/s Automatic Gain Control Amplifier
With Temperature Compensation
Chang Liu, Yue-Peng Yan, Wang-Ling Goh, Senior Member, IEEE, Yong-Zhong Xiong, Senior Member, IEEE,
Li-Jun Zhang, Member, IEEE, and Mohammad Madihian, Fellow, IEEE
Abstract—This paper presents an automatic gain control (AGC)
amplifier with temperature compensation for high-speed appli-
cations. The proposed AGC consists of a folded Gilbert variable
gain amplifier (VGA), a dc offset canceller, inductorless post
amplifiers, a linear open-loop peak detector (PD), an integrator,
a symmetrical exponential voltage generator, and a compensation
block for temperature stability. The novel temperature com-
pensation scheme ensures the AGC stability and accuracy over
20 C–200 C by predicting the integrator biasing voltage based
on the crucial blocks duplication technique. The proposed linear
open loop PD combined with the linear-in-dB VGA manages
the dB-linear error of less than 0.3 dB for the received signal
strength indication (RSSI). The AGC chip is fabricated using
a 0.13- m SiGe BiCMOS technology. Consuming a power of
72 mW from a 1.2-V supply voltage, the fabricated circuit exhibits
a voltage gain of 40 dB and a 3-dB bandwidth of 7.5 GHz. With
a 2 1 pseudo-random bit sequence at 5-Gb/s, the measured
peak-to-peak jitter is less than 40ps across the 20 C–200 C
temperature range. The low linear-in-dB error and the wide
operating temperature range achieving the high-speed data input
signal indicate the suitability of the proposed techniques for
high-speed AGC amplifiers.
Index Terms—Automatic gain control (AGC), linear-in-dB gain
characteristic, temperature compensation, linear open-loop peak
detector, symmetric exponential voltage generator, variable gain
control (VGA).
I. INTRODUCTION
W ITH the increasing demands for gigabit-class data
transmission in microwave and millimeter-wave
imaging systems [1], local-area-network (LAN) links [2],
Manuscript received November 21, 2011; revised March 10, 2012; accepted
March 15, 2012. Date of publication May 02, 2012; date of current version May
22, 2012. This paper was approved by Associate Editor Andreas Kaiser. This
work was supported by A*STAR (Agency for Science, Technology and Re-
search), Singapore, under Grant 102 129 0051.
C. Liu, is with the Institute of Microelectronics, Chinese Academy of
Sciences (IMECAS), Beijing 100029, China, the Institute of Microelectronics,
A*STAR (Agency for Science, Technology and Research), 117685 Singapore,
and also with Nanyang Technological University, 639798 Singapore (e-mail:
liuchang.mouse@gmail.com).
Y.-P. Yan and L.-J. Zhang are with the Institute of Microelectronics, Chinese
Academy of Sciences (IMECAS), Beijing 100029, China.
Y. -Z. Xiong was with the Institute of Microelectronics, A*STAR (Agency for
Science, Technology and Research), 117685, Singapore. He is currently with the
MicroArray Technologies, Chengdu 611731, China (e-mail: eyzxiong@ieee.
org).
W.-L. Goh is with Nanyang Technological University, 639798 Singapore
(e-mail: EWLGOH@ntu.edu.sg).
M. Madihian is with the Institute of Microelectronics, A*STAR (Agency
for Science, Technology and Research), 117685 Singapore (e-mail: madi-
hian@ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2012.2192660
0018-9200/$31.00 © 2012 IEEE
1323
and optical communication systems [3], the role of the auto-
matic gain control (AGC) amplifiers is fundamental in these
systems—to provide a constant envelope signal for low demod-
ulation error and to improve the linearity and dynamic range
capacity of the whole system.
For high-speed applications, an AGC with constant settling
time is preferred because it permits a maximum bandwidth
for fast signal acquisition while maintaining overall stability
[4]. A variable gain amplifier (VGA) with linear-in-dB control
is required to realize the constant settling time of the AGC.
In addition, an accurate linear-in-dB control signal facilitates
a precise received signal strength indication (RSSI) for the
system capacity optimization [5]. The prior state-of-the-art
high-speed AGC amplifiers with the dB-linear VGA had ig-
nored the nonlinear feature of the peak detector (PD) [2], [6]
which can damage the loop linearity and RSSI accuracy. A
linear high speed PD for lowering the overall linear-in-dB error
is therefore crucial.
Owing to the inherent temperature sensitivity of the
linear-in-dB feature, temperature compensation has become
indispensable for enhancing the environment tolerance of the
AGC. The compensation scheme involving bipolar transis-
tors [7] stacks multiple devices at the same current branch,
which saturates the transistors under low supply voltage.
Another compensation scheme using subthreshold regime
CMOS transistors [8] necessitates ac coupling capacitors for
temperature-insensitive control. Unfortunately, the ac coupling
topology corrupts the desired signal [9] and deteriorates the
output jitter due to the capacitor leakage current. Thus, a novel
temperature-compensation approach for high-speed AGC that
can operate at a low supply voltage is imperative.
In this paper, a 5-Gb/s AGC with temperature compensation
is presented. The dB-linear control feature is guaranteed by a
linear-in-dB VGA and a proposed linear open-loop PD. The pro-
posed temperature compensation approach significantly extends
the operating temperature range of the AGC at a low supply
voltage and under dc coupling condition to achieve minimum
jitter performance in case of random high-speed signals.
This paper is organized as follows. Section II describes the
architecture of the proposed AGC. The detailed circuit designs
are presented in Section III. Finally, the measurement results
and conclusions are given in Sections IV and V, respectively.
II. ARCHITECTURE
The architecture of the AGC amplifier is presented in Fig. 1.
The forward path includes: a VGA for gain adjustment, an ex-
ponential voltage generator to convert the control voltage to
1324
Fig. 1. Architecture of AGC amplifier.
differential exponential gain control voltages, a dc offset can-
celler with common-mode voltage adjustment scheme to cancel
the offset voltage and correct the common mode voltages to an
appropriate level, two post amplifiers to extend the bandwidth
and improve the sensitivity, and a test buffer for driving a 50-
off-chip load. The dc coupling topology adopted in the forward
path is to ensure an optimum jitter performance.
In the feedback path, the proposed PD extracts the ampli-
tude of the output signal linearly. Then, the output of PD is
compared with an internal reference voltage and the inte-
grator accumulates the difference between them to generate the
control voltage. Since is proportional to the output signal
amplitude, the corresponding is required to be gener-
ated by a reference level shifter (Ref. Level Shifter) for auto-
matically achieving the same proportional coefficient as .
The proposed temperature compensation block produces a bi-
asing voltage for the integrator in the main loop. This biasing
voltage varies with the ambient temperature and the input signal
strength to force the integrator to generate the required control
voltage for different temperatures.
III. CIRCUIT DESCRIPTION
Here, we present the circuit details of the various building
blocks and their design considerations.
A. VGA and Exponential Voltage Generator
Fig. 2 depicts the circuits of the VGA and the proposed ex-
ponential voltage generator. The combination of VGA and the
exponential voltage generator realizes a linear-in-dB character-
istic between the AGC’s gain and the control voltage.
For high-data-rate and low-power-supply applications, a
folded Gilbert structure [10] is used for the VGA. As shown in
Fig. 2, the relationship between the inputs and the outputs of
VGA can be expressed as follows:
(1)
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 6, JUNE 2012
where and are generated by the exponential voltage
generator and they manipulate the gain of the VGA.
A symmetrical exponential voltage generator (see Fig. 2) is
proposed to eliminate the need for large voltage headroom [10].
Unlike the traditional structure [10], no BJT is engaged at the
output branch and both BJTs are under the same operating con-
dition. This is to avoid BJTs from being saturated by the output
voltage when operating at a low supply voltage. Since and
operate in the active regions, the collector currents of and
are the same, i.e., . With
proper sizing of the transistors in the MOS current mirrors,
and would become equal to and , respectively. There-
fore, the difference between and can be calculated as
(2)
where is the saturation current and is the thermal voltage.
By substituting (2) into (1), we obtain
(3)
On a decibel scale, (3) can be altered to (4) as
dB (4)
where
Equation (4) expresses a linear relationship between the ampli-
fier gain and the control voltage in decibel scale.
The use of BJTs to generate the exponential current in our de-
sign determines an inherent temperature coefficient in (3) [11].
Fig. 3 shows the simulation results of the VGA gain versus the
control voltage. In order to maintain a constant gain range over
the temperature variation, the control voltage range must shift,
and this phenomenon will be discussed in Section F.
B. DC Offset Canceller (DOC)
In this design, a doubler scheme [12] is proposed for in-
clusion to the dc offset canceller, as shown in Fig. 4. This struc-
ture cancels the dc offset voltage and simultaneously corrects
the common mode voltages of the outputs of DOC to a desir-
able level . The value is chosen at the midpoint of the
calculated input common voltage range and its voltage is fixed
by the resistor ratio.
The common mode voltage correction scheme is necessary
for high speed applications. This is because the common mode
feedback (CMFB) scheme is usually absent in the gain cells of
the high-speed AGC owing to the large parasitic impedance that
shrinks the bandwidth. This leads to a shift in the common mode
voltage which deteriorates the dynamic range of the subsequent
stages. The low-pass filter (LPF) extracts the dc voltage at the
LIU et al.: A 5-GB/S AUTOMATIC GAIN CONTROL AMPLIFIER WITH TEMPERATURE COMPENSATION 1325

Fig. 2. Circuit schematics of linear-in-dB VGA and exponential voltage generator.

gain peaking and the group delay variation, each post amplifiers
has a peaking gain of 3.9 dB, with a simulated overall group
variation of 100 ps within the 3-dB bandwidth of AGC.

D. Peak Detector (PD) and Reference Level Shifter

Fig. 6 shows the proposed linear open-loop PD and reference
level shifter. A correction block is introduced after the conven-
tional open-loop PD, i.e., a source-coupled pair followed by
low-pass filtering. The correcting effect can be revealed through
comparison such that

(5)
(6)

where is the output of the conventional open-loop PD, is

Fig. 3. Simulation results: gain of VGA versus control voltage plots the output of the proposed PD, is the input ac signal of PD
for different temperatures. and is a constant.
The source-coupled and , and the RC low-pass filter
constitute the classical open-loop PD. can be expressed as
outputs of the AGC, feeding them back to and for dc
offset voltage cancellation. To minimize the chip area, nMOS
(7)
transistors with grounded drain and source are used as capaci-
tors. The LPF is designed for a low cutoff frequency of 200 kHz.
where is the common-mode voltage of the incoming signal,
C. Post Amplifiers is the threshold of the nMOS transistor, is the current
The stages following the dc offset cancelling block are two source, and is .
post amplifiers that provide a fixed gain for the AGC. Without To correct the nonlinear relationship between and
using on-chip bulky inductors for gain peaking [12], [13], a is introduced as a base voltage. is the equivalent output of the
third-order gain stage with active feedback scheme is adopted source-coupled amplifier in the absent of input ac signal when
to enlarge the bandwidth [14]. The circuit diagram for each post the two inputs are set to . Hence, can be expressed as
amplifier is given in Fig. 5(a). In this design, the gain peaking
of the post amplifiers compensate the inherent gain drop of the (8)
VGA and DOC in the high frequency, hence attaining excellent
gain flatness over the frequency range. Fig. 5(b) depicts the sim- The correction block (see Fig. 6) serves to convert and
ulated frequency response of the cascaded gain cells. into current and compare them. The output current , i.e.,
The AGC amplifier achieves an excellent gain–bandwidth re- , is proportional to while the is relatively
sponse through the gain peaking of the post amplifiers. How- smaller than . can be given by
ever, as per other broad bandwidth techniques, it is inevitable
to accumulate frequency-dependent network delay that causes
signal distortion [13]. Thus, the group delay variation is con-
sidered so as to avoid worsening of the jitter of the output high
speed signal. According to the tradeoff between the amount of (9)
1326 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 6, JUNE 2012

Fig. 4. Circuit of DOC.

Fig. 6. Circuits of the proposed linear open-loop PD and reference level shifter.

and are sensitive to temperature. When an identical input

signal is fed to the PD, the detected peak amplitude will drift
with temperature. If the internal reference voltage is a constant
over temperature, the comparison between and will
not be accurate, causing an error between the amplitude of the
output signal and the desired level. Hence, the internal reference
voltage is required to drift by the same amount that varies
with temperature.
Fig. 5. (a) Post amplifier circuit. (b) Simulated frequency response of the cas-
caded gain cells.
In Fig. 6, is the desired output ac signal amplitude of
AGC, and can be expressed as

where is a constant and is . Owing to (12)

the pMOS can be also expressed as
and are fed to another correction circuit. Thereafter, the
internal reference voltage can be expressed as
(10)
(13)
where is and is the threshold
voltage of the pMOS transistor. Substituting (9) into (10), we As can be seen, (11) and (13) have similar forms and the same
obtain temperature-sensitive coefficient. Fig. 7(a) shows the simulated
results of and on their amount of drift with tem-
(11) perature when the input signal amplitude of PD and are
both 100 mV. Although there is minute discrepancy between
is a constant and is equal to . and with temperature variation, this small amount
From (11), a linear relationship between and is real- of error is tolerable in the system. The linear response of the
ized by the proposed correction technique. The coefficients of proposed PD is presented in Fig. 7(b). Some distortion occurs
LIU et al.: A 5-GB/S AUTOMATIC GAIN CONTROL AMPLIFIER WITH TEMPERATURE COMPENSATION 1327

Fig. 7. (a) Drift feature of and with temperature. (b) Linear response of the proposed PD.

the steady state, i.e., over temperature, is de-

signed to vary with temperature for achieving desirable at
different temperatures. Thus, at the steady state, is propor-
tional to the biasing voltage such that

(15)

The temperature compensation block is therefore mandatory

to provide an optimum biasing voltage for the main loop,
to ensure a proper control voltage value while maintaining the
accuracy of the loop at different temperatures.
Fig. 8. Integrator circuit.
F. Temperature-Compensation Block
A biasing voltage predicting technique is proposed for the
when a small signal is incoming. Because the output current of temperature compensation. This technique takes advantage of
the correction circuit (see Fig. 6) is very tiny with the small input the replicated key blocks to generate a proper biasing voltage
signal according to (9). At the low current, the pMOS transistor for the integrator in the main loop (see Fig. 1) according to
operates in the weak-inversion region, which means it has the ambient temperature and the incoming signal. The replica
an exponential current–voltage relationship and cause the little of the temperature sensitive block, i.e., exponential voltage
distortion because of the derivation based on the square-law generator, guarantees an identical temperature coefficient
relationship. between the compensation block and the main loop for an
accurate compensation.
E. Integrator
Fig. 9 demonstrates the concept of temperature compensa-
In the AGC loop, the integrator circuit of Fig. 8 compares tion. Because of its linear-in-dB characteristics, the input power
the PD output with an internal reference voltage and has a linear relationship with the control voltage. Furthermore,
accumulates the difference between them. The output of the in- the proposed linear PD and the linear integrator are able to en-
tegrator is the control voltage that determines the gain of sure the linear relationship between the signal amplitude and
the VGA and has the following equation: the control voltage. Hence, the control voltage can be predicted
through the difference between the input signal amplitude
(14)
and the internal reference voltage . Amplifier A1 gener-
where is the dc voltage of and is the gain of the ates a predictive control voltage , which can be deter-
integrator. mined using the following equation:
As seen earlier in Fig. 3, is supposed to shift consider-
ably to maintain the identical gain range at different tempera- (16)
tures. According to (14), if is fixed at the same value as the
usual designs, the error between and needs to vary where is a constant and and are generated by the
radically to attain the different requirements. In view of temperature sensitive loop 1 and loop 2, respectively. Since
this and to derive an accurate output amplitude for the AGC at loops 1 and 2 each contain a replica of the exponential block,
1328 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 6, JUNE 2012

Fig. 9. Block diagram representation of the temperature-compensation concept.

Fig. 10. Amplifier A1.

and will have the same temperature coefficient as the

main loop. Hence, is sensitive to the temperature, just
like the control voltage in the main loop. is to
be fed into the positive input of the amplifier A2 that forces
the output of the replica integrator to through adjusting
the biasing voltage . The inputs of the replica integrator are
both , which imitates the ideal output amplitude
. Finally, an optimum biasing voltage is generated,
and the proportional relationships according to (14) and (15)
ensure that the control voltage in the main loop has an
identical temperature coefficient as (3). This implies that Fig. 11. Temperature sensitive loops: (a) loop 1 and (b) loop 2.
will shift with temperature to compensate the drifted BJT tech-
nical parameters thereby maintaining a constant gain range over
a wide temperature variation. forces the positive output of A3 to by adjusting automat-
The amplifier A1 is an instrument amplifier as shown in ically. can be given as
Fig. 10, and its transfer function is expressed by (16). The
amplifier generates the predicted control voltage ac-
cording to , and the amplitude of the incoming signal (17)
.
and are respectively generated by loops 1 and 2 in where is the reference common mode voltage of A3 and
Fig. 11. Both loops contain a replica of the exponential voltage is a dc differential input signal determined by the ratio
generator and a VGA with CMFB that has the same gain-control of the series resisters. After the adjustment, a desirable control
characteristics with the VGA in the main loop. Due to CMFB, voltage is produced by this loop. In loop 2, the desired gain
the two loops are able to achieve ultralow power consumptions of A6 is 0 dB. Base on the same theory of loop 1, the resistors
with the narrow bandwidth. Because of the temperature-sensi- connection produce the required output of A6 whereby the
tive exponential blocks, the control voltages, and , are loop forces the control voltage to a proper value to ensure
both required to shift to maintain respective gain values of A3 0-dB gain for A6 at different temperatures. is generated by
and A6 at different temperatures. In loop 1, to accomplish the the amplifier A7, which is a replica of A1. In both A1 and A7, the
same gain of A1 ( 15 dB) at different temperatures, the loop resistor is a MOS resistor whereby its value is controlled by
LIU et al.: A 5-GB/S AUTOMATIC GAIN CONTROL AMPLIFIER WITH TEMPERATURE COMPENSATION 1329

Fig. 13. Die microgragh.

Fig. 12. Simulated results of and at different temperatures:

(a) 20 C, (b) 27 C, and (c) 125 C. Note: the input signal amplitude of Fig. 14. Measured gain-bandwidth response over temperature.
AGC is 6 mV.

therefore verify the function as well as the merits of the pro-

the gate voltage. The transfer function of A7 can be expressed posed temperature compensation scheme. Fig. 12 also shows
as the increased ringing of the output amplitude before the loop at-
tains a steady state as temperature decreases.
(18) In summary, the temperature compensation block generates
an optimum biasing voltage for the integrator of the main loop
where is generated by loop 1, is a constant, is the value by accurately predicting the control voltage at different temper-
of the MOS resistor that is adjusted by loop 2, and is atures and incoming signals. The benefits of the proposed tem-
the amplitude of the incoming signal while the gain of VGA is perature compensation scheme are threefold. First, the compen-
equal to 15 dB. Hence, the control signal can be realized sated voltage is a biasing voltage out of the high speed signal
by loop 2. Upon the successful generation of and , the two path, which ensures less parasitic impedance to the gain cells for
signals are sent to A1 to predict the control voltage. achieving a broad bandwidth. Second, this proposed approach
According to (14), the two loops can guarantee accuracy in enhances the accuracy of the AGC over a wide temperature
the AGC, i.e., , when the temperature compensa- range while maintaining its stability. Third, the simple circuit
tion scheme yields an optimum with temperature variation. design allows it to be used at a low power supply. This approach
Hence, the temperature compensation scheme can be validated proofs that the duplication of temperature sensitive block for
through the accuracy between and . Fig. 12 provides generating the compensation signal for the main amplifiers, can
the simulation results of the entire loop at the output of the PD be widely used in other temperature sensitive applications.
and the internal reference voltage at different tem-
peratures, when the input ac signal amplitude of AGC is 6 mV. IV. MEASUREMENT RESULTS
It is can be seen that over a wide temperature range, the output The proposed AGC was fabricated in IHP’s 0.13- m SiGe
amplitude is equal to the desired level. The simulation results BiCMOS process. The chip occupies 1 mm silicon area
1330 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 6, JUNE 2012

Fig. 15. (a) Measured gain versus control voltage. (b) Gain versus input power over temperature.

Fig. 16. Linear-in-dB error versus input power.

(including bond pads) and is depicted in Fig. 13. It requires

no external components for testing and the performance is
measured by probing the die.
The AGC consumes 72 mW with a 1.2-V power supply. This
is excluding the output buffer that is used to drive the 50-
probe. The 3-dB bandwidth is from 200 kHz to 7.5 GHz. Fig. 14
shows the measured gain-bandwidth response over temperature.
The bandwidth decreases with temperature increasing.
Fig. 15(a) depicts the measured gain-control characteristics
at 20 C, 0 C, 27 C, 75 C, 125 C, and 200 C, with 5-Gb/s
PRBS signal input. The AGC exhibits a temperature-sensitive
control voltage for attainting a constant gain range and a Fig. 17. Measured 5-Gb/s 2 1 PRBS data single-ended output eye diagrams
linear relationship between the gain and control voltage. The at 20 C, 27 C, 125 C, and 200 C.
temperature stability of the dB-linear response is reflected
in Fig. 15(b), demonstrating gain versus input power over
different temperatures. The AGC provides more than 30-dB the range of input power from 40 to 15 dBm, the decibel
gain variation and shows good temperature insensitivity. In gain deviation from 20 C to 125 C is less than 2.5 dB. The
LIU et al.: A 5-GB/S AUTOMATIC GAIN CONTROL AMPLIFIER WITH TEMPERATURE COMPENSATION
TABLE I
MEASUREMENT RESULTS AND BENCHMARKING
gain at more than 125 C decreases due to the deteriorated
performance of the test buffer as temperature increases.
The AGC with a linear-in-dB control characteristic is
usually used to indicate the input signal power through the
control voltage. Fig. 16 presents the measured linear-in-dB
error, which reflects the linear-in-dB accuracy of the control
voltage. A 0.3 dB error is achieved through the use of our
proposed linear open-loop PD and linear-in-dB VGA. The
small linear-in-dB error has enhanced the accuracy of RSSI
dramatically.
Fig. 17 shows the measured eye diagrams of single-ended
output with 5-Gb/s 2 1 PRBS data input at different tempera-
tures ( 20 C, 27 C, 125 C, and 200 C). The output peak-to-
peak jitter is less than 40ps over the wide temperature range.
The amplitude of the output remains constant for different input
amplitudes at the same temperature except that there is a small
variation of 14% at 200 C. From the clear eye diagrams, it is no
doubt that the proposed AGC can work well over a wide tem-
perature range.
Other measurement results and a comparison with prior
works are summarized in Table I. A comparison with high
data rate AGC [2] revealed that the proposed AGC (with the
temperature compensation scheme) achieved an enhanced en-
vironment tolerance for the amplifier but at the expense of some
power consumptions. Then again, the 0.3 dB linear-in-dB
error is far lower than prior works. And compared to the prior
arts with temperature compensation scheme [7], [8], this work
realized the temperature compensation without requiring the
large voltage headroom and sacrificing the jitter performance
of high speed signal, attaining a widest operating temperature
range.
V. CONCLUSION
This paper has demonstrated a 5-Gb/s AGC with temperature
compensation. Compared with prior works, the proposed linear
open-loop peak detector is able to ensure a linear loop charac-
teristic, and the proposed temperature compensation scheme is
extremely suited for high speed signal temperature compensa-
tion applications. The validity of the approach had been verified
1331
through circuit measurement, where the chip operating temper-
ature range is from 20 C to 200 C. A 0.3 dB linear-in-dB
is achieved and this is a tremendous enhancement in accuracy
of the RSSI. The peak-to-peak jitter is lower than 40 ps over
the wide temperature range, and the 3-dB bandwidth is from
200 kHz to 7.5 GHz. The proposed AGC design is therefore
suitable for high-speed applications under varying temperature
operation.
ACKNOWLEDGMENT
The authors would like to thank the following staff and stu-
dents in the Institute of Microelectronics, A*STAR, Singapore:
Dr. J. He, Dr. S.-M. Hu, Dr. L. Wang, L. Liu, and D.-B. Hou,
for their kind assistance and the many helpful discussions.
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Chang Liu received the B.Sc. degree in electronics
science and technology from Beijing Institute of
Technology, Beijing, China, in 2007. She is currently
working toward the Ph.D. degree at the Institute
of Microelectronics, Chinese Academy of Sciences
(IMECAS), Beijing, China.
From 2007 to 2010, she worked on the design
and development of several key Analog/RF building
blocks including PLL, PGA, and AGC at IMECAS,
Beijing, China. Since 2010, she has been an ex-
change Ph.D. student at the Nanyang Technological
University, Singapore, and participating in the development of silicon-based
millimeter-wave identification systems for imaging, sensing, and wireless com-
munication applications at the Institute of Microelectronics, A*STAR (Agency
for Science, Technology and Research), Singapore. Her research interests in-
clude CMOS and SiGe BiCMOS Analog/RF and microwave/millimeter-wave
integrated transceiver circuits for high speed wireless communication applica-
tion.
Yue-Peng Yan received the M.S. degree in electrical
and electronic engineering and Ph.D. degree in in-
formation system sciences from Ibaraki University,
Ibaraki, Japan, in 1995 and 1998, respectively.
From 1999 to 2004, he was a Research Project
Leader with the Department of Semi-conductor,
NEC Corporation, Tokyo, Japan, where he was in-
volved in the development of monolithic microwave
integrated circuits (MMICs) and multichip modules
(MCMs) for third-generation (3G) W-CDMA cell
phones. Since 2005, he has been a Director Professor
and Dean with the Department of Electronics System Technology, Institute of
Microelectronics, Chinese Academy of Sciences (IMECAS), Beijing, China,
where he is involved in the “863” communication and navigation integrated
terminals project, “863” wireless sensor networks chip design project, and
circuits and systems (CAS) “hundred talents program” project. His research
interests include RF and microwave integrated circuit (IC) design and system
design.
Wang Ling Goh (SM’09) received the B.Eng. degree
in electrical and electronic engineering and Ph.D. de-
gree in microelectronics from Queen’s University of
Belfast, Belfast, U.K.
She is currently an Associate Dean for Out-
reach and External Relations at the College of
Engineering, Nanyang Technological University,
Singapore, where she was a Lecturer in 1996, and
became an Associate Professor in 2004 with the
School of Electrical and Electronic Engineering. She
was a Research Engineer at the Northern Ireland
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 6, JUNE 2012
Semiconductor Research Centre while working toward the Ph.D. degree. Her
research interests include digital/mixed-signal IC design, neural recording IC,
and 3-D IC.
Yong-Zhong Xiong (M’98–02’SM) received the
B.S. and M.Eng. degrees in communication and
electronic systems from the Nanjing university of
Science and Technology (NUST), Nanjing, China, in
1986 and 1990, respectively, and the Ph.D. degree in
electrical and electronic engineering at the Nanyang
Technological University (NTU), Singapore.
From 1986 to 1994, he was with NUST, where he
was involved with microwave systems and circuit
design in the Department of Electronic Engineering,
NUST. In 1994, He was with the Nanyang Techno-
logical University (NTU) as a research scholar. From 1995 to 1997, he was
with the RF and radios department, Singapore Technologies (ST, Singapore),
As a senior engineer, he was also affiliated with the Centre for Wireless Com-
munications, National University of Singapore, in 1996, where he was involved
with the RFID Project. Until the end of 1997, he was with the microelectronics
centre, Nanyang Technological University (NTU). Since September 2001, he
was with the institute of Microelectronics (IME) of Singapore as a Principal
Investigator (PI) to lead a group for the millimeter wave/Terahertz circuit
and system design. Now he is working with the MicorArray Technologies,
Chengdu, China, as a Chief Technical Officer (CTO). He has authored or coau-
thored over 140 technical papers. His major working areas include monolithic
RF, microwave and millimeter wave integrated circuit (RFIC/MMIC) design,
and device modeling and characterization. He holds several issued patents.
Dr. Xiong has served as a technical reviewer for the IEEE TRANSACTION ON
ELECTRON DEVICES, the IEEE TRANSACTION ON ELECTRON DEVICE LETTERS,
the IEEE TRANSACTION ON MICROWAVE AND THEORY TECHNIQUES, and the
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, and also served on
committees of Singapore IEEE MTT Chapter and IEEE International Workshop
on Radio-Frequency Integration Technology.
Li-Jun Zhang (M’02) received the B.Sc. degree
from Hefei University of Technology, Anhui, China,
in 1987.
He was a Research Project Leader of China
Academy of Electronics and Information Tech-
nology (CAEIT), China Electronics Technology
Group Corporation (CETC), China, from 1987 to
2008. Since 2008, he has been with Department of
Electronics System Technology of the Institute of
Microelectronics, Chinese Academy of Sciences
(IMECAS), as Professor and Deputy Director
and Doctoral Supervisor, where he is involved with the development of
ultrahigh-frequency and high-efficiency compounds for integrated circuit
components and integration technologies. He is now the National Science
and Technology Award evaluation expert. His research interests include
microwave high-power solid-state devices and solid-state transmitting system,
in third-generation semiconductor device GaN to develop GaN on Si model
and characterization methods, and based on its developed models to design
high-efficiency power amplifiers for millimeter-wave radar and communication
applications.
LIU et al.: A 5-GB/S AUTOMATIC GAIN CONTROL AMPLIFIER WITH TEMPERATURE COMPENSATION 1333

Mohammad Madihian (S’78–M’83–SM’88–F’98)

received the B.Sc. degree from Iran University of Sci-
ence and Technology, Tehran, Iran, in 1976, and the
M.Sc. and Ph.D. degrees from Shizuoka University,
Shizuoka, Japan, in 1980 and 1983, respectively, all
in electronic engineering.
He is currently Technical Director with the Insti-
tute of Microelectronics, Singapore. He previously
served as Managing Director at MEDIWAVE LLC,
Director at NEC Corporation of America, and Chief
Patent Officer and Department Head at NEC Labora-
tories America, leading RF chip development and PHY/MAC layer signal pro-
cessing research. He has a book on CMOS-RF. He has authored or coauthored
more than 210 journal and conference publications, including 28 invited talks,
and holds 80 registered or pending patents on device, circuit, and system for
wireless applications.
Dr. Madihian received the IEEE Microwave Theory and Techniques Society
(MTT-S) Best Paper Microwave Prize in 1988. He holds eight Distinguished
R&D Achievement Awards and 3 IEEE Certificates of Recognition. He served
as Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEICE Trans-
actions on Electronics, and the IEEE TRANSACTIONS ON MICROWAVE THEORY
AND TECHNIQUES. He is currently an Associate Editor of Japan IEICE Trans-
actions on Electronics, and also serving on the IEEE Speaker’s Bureau, IEEE
International Microwave Symposium Technical Program Committee, MTT-6
Subcommittee, and MTT-S Editorial Board. He was the 2010 Secretary for the
IEEE MTT-S and is currently an Administrative Committee member of the So-
ciety. He is the General Co-Chair of the 2012 IEEE Radio Frequency Integration
Technology Conference in Singapore, the Technical Program Chair of the 2013
IEEE International Wireless Symposium in Beijing, and the General Chair of
the 2018 IEEE International Microwave Symposium in Philadelphia. He was
the General Chair for both the IEEE Radio & Wireless Symposium and Com-
pound Semiconductor IC Symposium in 2007, and the Technical Program Chair
for these conferences in 2006. He served on the CSICS Executive Committee
from 2000 to 2010 and was the Executive Committee Chair Emeritus in 2008.
He also served as the RWS Executive Committee Chair from 2008 to 2010 and
is currently an Executive Committee member. He was the Editor-in-Chief of
International Journal of Microwave Science and Technology since its inception
in 2006 until 2009.