IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO.
5, MAY 2011
Active 220- and 325-GHz Frequency Multiplier
Chains in an SiGe HBT Technology
Erik Öjefors, Member, IEEE, Bernd Heinemann, and Ullrich R. Pfeiffer, Senior Member, IEEE
Abstract—A 325-GHz 18 frequency multiplier chain imple-
mented in a max = 250GHz 380
GHz evaluation SiGe het-
erojunction bipolar transistor technology is presented. The chain
achieves a peak output power of 3 dBm and consists of a balanced
doubler driven by two cascaded tripler stages. It operates from 317
to 328 GHz with a 0-dBm 18-GHz input signal and a 1.5-W power
consumption. Additionally, 220- and 325-GHz doubler breakout
circuits with integrated driver amplifiers are presented. The dou-
blers reach an output power of 1 dBm at 220 GHz and 3 dBm at
325 GHz with a power dissipation of 630 and 420 mW, respectively.
Index Terms—Frequency multipliers, heterojunction bipolar
transistor (HBT), millimeter-wave integrated circuits, silicon,
submillimeter waves.
I. INTRODUCTION
T HE RECENT advances in SiGe BiCMOS and CMOS
technologies have made it possible to build silicon-based
heterodyne receivers [1] and square-law detectors [2] operating
in the lower sub-millimeter-wave band. This band, spanning
from 300 GHz to 3 THz, offers a number of emerging appli-
cations in the safety, health-care, environmental, and industrial
inspection areas, as well as in the security screening field.
Unlike other terahertz technologies, silicon-based circuits can
be highly integrated and fabricated at low cost in high volumes.
Silicon device performance improvements have been accom-
plished through steady progress in vertical and lateral scaling
for parasitic resistance and capacitance reduction [3]. Various
technology nodes are typically compared at their peak cutoff
frequencies . Higher cutoff frequencies can be lever-
aged in two ways. On one hand, a faster technology node can
be used to bias devices at lower current densities to achieve a
given performance. This leads to a reduced power dissipa-
tion. On the other hand, a faster technology can support higher
operating (e.g., carrier) frequencies with typically about 1/3 of
the peak in practical applications. One of the drawbacks of
the vertical profile scaling, however, is the reduction in achiev-
able breakdown voltages (BVs) by pushing out the Kirk effect
Manuscript received October 07, 2010; revised January 20, 2011; accepted
January 25, 2011. Date of publication March 10, 2011; date of current version
May 11, 2011. This work was supported in part by the European Commission
under Project DOTFIVE 216110. This paper is an expanded paper from the
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Anaheim, CA,
May 23–28, 2010.
E. Öjefors and U. R. Pfeiffer are with the Institute for High-Frequency and
Communication Technology, University of Wuppertal, D-42119 Wuppertal,
Germany (e-mail: erik.ojefors@ieee.org; ullrich@ieee.org).
B. Heinemann is with Innovations for High Performance Microelectronics
(IHP) GmbH, D-15236 Frankfurt (Oder), Germany.
Digital Object Identifier 10.1109/TMTT.2011.2114364
0018-9480/$26.00 © 2011 IEEE
1311
to higher current densities. Power generation at, or above, the
cutoff frequency is therefore regarded as a difficult design
challenge in silicon.
At lower millimeter-wave frequencies, where amplifiers still
exhibit power gain, SiGe technologies have demonstrated sat-
urated output powers as high as 20 dBm at 60 GHz [4] and
recently up to 8 dBm at 160 GHz in [5]. The exploitation of
the sub-millimeter-wave band, however, requires the transis-
tors to be operated close to, or even above, their cutoff fre-
quencies. Power generation techniques beyond the cutoff fre-
quency are done in one of two ways, which are: 1) directly
extracted from oscillators or 2) up-converted from lower fre-
quencies by the help of frequency multiplier chains. An SiGe
278-GHz VCO, for instance, provided 38-dBm output power
in [6] and a 410-GHz 45-nm CMOS VCO provided 47 dBm
in [7], respectively. A linear superposition technique in CMOS
has demonstrated 46 dBm at 324 GHz [8]. Schottky-diode and
heterostructure-barrier-varactor (HBV) frequency multipliers in
waveguide technology are capable of generating more than 8
dBm of output power in the 260–400-GHz frequency range [9],
[10], but are costly to implement and difficult to integrate in mul-
tichannel or power-combining systems. However, III–V mono-
lithic microwave integrated circuit (MMIC) multipliers have re-
cently provided monolithically integrated alternatives capable
of 0-dBm output power at 195 GHz [11], as well as 6.4 dBm
at 300 GHz [12].
This paper presents two active frequency doublers oper-
ating at 220 and 325 GHz, respectively, as well as a 325-GHz
fully integrated 18 multiplier chain implemented in a
GHz GHz evaluation SiGe HBT tech-
nology. The 320-GHz multiplier chain has been previously
published in [13], and is presented here, with an improved bias
point and a more accurate output power calibration procedure.
This leads to a peak output power of 3 dBm, which is substan-
tially higher than previously reported silicon circuits operating
in this band. Section II describes the circuit architecture and the
design of the multipliers, while Section III outlines the process
technology and layout of the circuits. Sections IV, V presents
the characterization setup including the measured results.
II. INTEGRATED ACTIVE FREQUENCY MULTIPLIERS
The integrated active frequency multipliers designed in this
work consist of a differential driver amplifier or cascaded tripler
chain and a final 220- or 320-GHz balanced frequency doubler,
as shown in Fig. 1. On-chip driver amplifiers have been inte-
grated with the standalone doubler circuits in order to facilitate
1312
Fig. 1. Block diagrams of the 220- and 325-GHz active frequency doublers,
2
as well as the monolithically integrated 325-GHz 18 multiplier chain imple-
mented in this work.
characterization using low-power millimeter-wave test equip-
ment. The differential topology was chosen for the driver am-
plifiers and triplers since it offers higher output power, better
even-order harmonic rejection, and easier integration of odd-
harmonic multipliers than single-ended designs. A balanced fre-
quency doubler is used as the final multiplier stage in order to
provide a single-ended output and high suppression of the fun-
damental signal component.
The 18 multiplier chain is equipped with tuned driver am-
plifiers after the 54- and 162.5-GHz tripler stages to boost the
power entering the next multiplier stage and to suppress spu-
rious frequencies. Hence, the full 18 multiplier chain can be
monolithically integrated without any dedicated filters. A dif-
ferential amplifier is used at the input to convert the 18-GHz
single-ended signal from an external synthesizer to a balanced
drive for the 54-GHz tripler.
A. Balanced 220- and 325-GHz Frequency Doublers
The balanced 325-GHz frequency doubler consists of a differ-
ential pair Q1/Q2 with a shared collector connection, as shown
in the circuit schematic (Fig. 2). The design is similar to dou-
bler circuits implemented in the - and -bands using SiGe
HBTs [14].
In this balanced doubler design, the devices Q1 and Q2 are
differentially driven in class B by the 162.5-GHz signal, thus
yielding current pulses of 325 GHz at the shared collector
connection. Hence, the selection of input power and voltage
bias of the base–emitter junctions is critical in order
to optimize the conduction angle for maximum second-order
harmonic generation. Typically, the load impedance and device
size in a doubler design is chosen based on the maximum
allowable voltage swing at the collector node and the required
second-order signal current for a prescribed output power [15].
The starting point of this doubler design was, however, the
8 dBm of 160-GHz power demonstrated with an SiGe HBT
power amplifier by the authors in [5]. Based on the available
drive power and harmonic-balance simulations of the doubler
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 5, MAY 2011
Fig. 2. Schematic of the 325-GHz doubler, which is based on a differential
stage driven in class-B to generate combined I pulses of twice the frequency
at the common collector node.
circuit, a device size of m was
selected for maximum output power. The choice of four-finger
devices over a longer single-emitter HBT was based on the
availability of high-frequency optimized HBTs in the device
design library.
At the 325-GHz operating frequency, the low output
impedance of the HBTs Q1/Q2 limits the voltage swing.
Hence, the sensitivity of the doubler to the load impedance is
low and allows a small-signal conjugate impedance match to be
used for maximum power transfer to the output. The simulated
10-j26- impedance (5-j17 including interconnect parasitics)
at the collector node is matched to a 50- output impedance by
a shunt inductance, which is provided by shortening the TL1
quarter-wave 50- transmission-line stub to an electrical length
of 0.08 . With the selected output match, the amplitude of
the signal voltage at the shared Q1/Q2 collector load is limited
to 0.3 V at saturation. The output signal of the doubler stage is
fed through the TL2 50- transmission line to the output pad.
On-chip inductive shunt compensation of the pad capacitance,
similar to the method described in [16], is used to minimize the
insertion loss of the pad.
The 162-GHz quarter-wave short-circuit shunt stubs
TL3/TL4 provide voltage biasing of the base–emitter junctions
of Q1 and Q2 while simultaneously acting as short circuits at
the input for the frequency doubled 325-GHz output signal.
This 325-GHz ground-return path at the base nodes serve a
similar function as the harmonic reflector networks used in
[14] and [17]. The transmission lines TL5 and TL6 provide
impedance matching at the input together with the metal–in-
sulator–metal (MIM) capacitors C1/C2. With the selected
matching components, the simulated 3-dB bandwidth of the
standalone balanced doubler circuit is 220–336 GHz.
The 325-GHz output power, which has been obtained by har-
monic-balance simulations, is shown as power contours in Fig. 3
for different input power and biasing conditions. By applying a
voltage close to the turn-on point of the transistor, a sim-
ulated output power larger than 3 dBm can be obtained with
a 8-dBm drive signal. Under these drive conditions, the doubler
requires a 10-mA supply current from a V supply.
It should be noted that the presented simulation results in Fig. 3
are based on preliminary models of the optimized HBTs present
ÖJEFORS et al.: ACTIVE 220- AND 325-GHz FREQUENCY MULTIPLIER CHAINS IN SiGe HBT TECHNOLOGY
Fig. 3. Power-contour plot showing the simulated 325-GHz output power for
different input power levels and bias voltages.
in the engineering version of the SiGe technology used in this
work.
The 220-GHz balanced doubler is similar to the design of
the 325-GHz circuit and shares the same device sizes with
retuned matching elements for the lower operating frequency.
With a 8-dBm input-signal level, the simulated output power is
2.3 dBm.
B. Three-Stage 110/160-GHz Driver Amplifiers
The driver amplifiers designed with 110- and 160-GHz oper-
ating frequencies consist of three cascaded differential cascode
stages, as shown in Fig. 4. The HBT emitter area is scaled with
the factors 1:2:4 from m devices
in the first stage to the m in the
third stage, with corresponding changes of the dc-bias current
and impedance matching. The differential cascode is powered
from a 4-V VCC line with the transistors Q3/Q4 voltage biased
with V in order to minimize impact ionization and
delay the onset of breakdown.
A conventional L-type impedance-matching network based
on the transmission-line inductances TL3/TL4 and the MIM
capacitors C3/C4 is used at the output of the amplifier. The
matching network is tuned for a maximum output power. The
transmission lines TL1/TL2 and the capacitors C1/C2 provide
matching at the input of each stage.
In a 100- differential environment, the simulated
small-signal gain and 3-dB bandwidth of the three-stage
160-GHz amplifier is 27 dB and 20 GHz, respectively. The
simulated output 1-dB compression point is 9 dBm and the
saturated power 14 dBm. The quiescent current drawn by the
three-stage amplifier is 100 mA from a 4-V supply.
A 110-GHz version of the amplifier with similar specifica-
tions has been designed by retuning the impedance matching
elements. In simulations, this amplifier yields a 13-dBm 1-dB
compression point and a saturated output power of 18 dBm.
1313
Fig. 4. Simplified schematic shared by all stages of the 110/162.6-GHz three-
stage driver amplifier. The Q1–Q4 devices are scaled with factors 1:2:4 from
the first to the last stage with the corresponding changes of the tuning elements.
C. 162.5- and 54-GHz Frequency Triplers
The 162.5-GHz frequency tripler is based on the same dif-
ferential cascode amplifier as the input stage of the three-stage
driver. The amplifier is saturated by a strong input signal, which
generates square-wave-like collector currents in the
m large devices Q1/Q2 and Q3/Q4. The high-
pass characteristic of the output L-type LC impedance-matching
network is used to short circuit the fundamental 54-GHz compo-
nent. It also provides an impedance match for maximum power
delivery of the tripled signal into a 100- differential system
impedance. The input impedance matching network is tuned for
minimum return loss at the 54-GHz input frequency.
The 54-GHz tripler and the two-stage 54-GHz power ampli-
fier in the chain use differential cascode stages of similar ar-
chitecture as their 162-GHz counterparts, but with differently
selected device sizes and matching elements.
III. TECHNOLOGY AND MANUFACTURING
A HBT-only evaluation version of a BiCMOS technology has
been used for the circuit fabrication. It represents a combina-
tion of the IHP 0.25- m BiCMOS process SG25H1 [18] and an
HBT module similar to that of the recently presented 0.13- m
BiCMOS technology [19].
In contrast to the 0.13- m BiCMOS process, the following
steps, affecting the HBT performance, were altered. The pro-
file of the SiGe:C base layer was changed resulting in a lower
base-sheet resistance, while the collector current density was ap-
proximately maintained. The temperature of the final spike an-
neal was reduced. Furthermore, the wafers exhibit a 45 rotated
substrate orientation, an enhanced sub-collector, and a reduced
salicide sheet resistance.
1314 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 5, MAY 2011
Fig. 5. Micrographs showing the: (a) 220-GHz active doubler, (b) 320-GHz
2 2
version of the same circuit, and (c) 2.2 0.43 mm large full 18 multiplier
chip.
For circuit fabrication, the process offers polysilicon and
silicide resistors. The back-end manufacturing corresponds
to the process flow and design rules of the SG25H1 tech-
nology with five aluminum metal layers, including a 1-fF m
MIM capacitor. The transistors achieve at V a
current gain of about 500 and demonstrate an open-base col-
lector–emitter breakdown-voltage of 1.7 V. Open and
short de-embedded small-signal current-gain and unilateral
gain were used for the extrapolation of and from
40 GHz with 20 dB per frequency decade. Compared with a
0.13- m BiCMOS reference HBT, the peak values
could be increased from 240 GHz/330 GHz to approximately
250 GHz/380 GHz in this modified technology.
Fig. 5 shows chip micrographs of the two implemented ac-
tive doubler breakout circuits, as well as the full 18 multiplier
chain, which occupies a die area of 2.2 0.43 mm . Clearly vis-
ible are the 50- shielded microstrip transmission lines used as
tuning stubs and interconnects between the stages of the multi-
plier chain. The transmission-line signal conductors and the side
shields are implemented as strips in the top metal (M5) layer,
while the third metal layer (M3) is used as the microstrip ground
plane.
IV. CHARACTERIZATION SETUP
The frequency multipliers have been characterized on wafer
with the setup shown in Fig. 6. The 18-GHz input signal for
Fig. 6. Setup used for characterization of the integrated multiplier. The wafer
probe is connected to an Erickson calorimeter for total power measurements,
while single-tone verification of the output power is provided by a calibrated
subharmonic mixer.
the 18 multiplier chain is fed from a synthesizer to the chip
through a coaxial wafer probe. For the doublers, the 110- and
160-GHz drive signals generated by millimeter-wave source
modules were provided through 1-mm coaxial and WR-06
waveguide wafer probes, respectively.
A ground–signal–ground (GSG) WR-03-waveguide probe
was used to extract the output signal from the frequency mul-
tiplier. The insertion loss of the output probe and waveguide
system was extracted by one-port -parameter measurements
of short–open–load impedance standards on a calibration
substrate using a network analyzer calibrated to the input wave-
guide flange. Due to frequency-dependent ripple, the insertion
loss shows 7–8-dB variation in the 300–330-GHz range with a
mean value of 7.5 dB at 325 GHz. The measured insertion loss
is within 1 dB of the loss predicted by the sum of the 3.4-dB
measured insertion loss of the WR-03 waveguide and the
3.5-dB insertion loss of the wafer probe calculated from vendor
provided one-port measurements of reflective standards. At the
220-GHz frequency, the insertion loss increases to 8 dB due
to the higher losses of the waveguide section close to cutoff.
The output power has been measured using two alternative
methods. An Erickson calorimeter, equipped with an input
waveguide taper, was used for total output-power measure-
ments. The 173-GHz cutoff frequency of the WR-03 waveguide
system in front of the power meter prevents any fundamental
160-GHz signal leakage through the final doubler circuit from
affecting the total-power measurements. Compared to the
free-space power meter used for the characterization of the
18 multiplier in [13], the calorimeter offers better accuracy
since the unknown horn-antenna efficiency and pointing losses
due to misalignment are eliminated from the measurement. An
alternative power-measurement method is provided by a 20
harmonic mixer used instead of the power meter. The mixer
has been calibrated using the power meter and a 220–325-GHz
source module. Although less accurate, the harmonic mixer
measurements provide single-tone monitoring of the power in
the intended output harmonic by means of a spectrum analyzer.
Hence, these measurements can be used to verify sufficient sup-
pression of spurious signals in the total power measurements.
ÖJEFORS et al.: ACTIVE 220- AND 325-GHz FREQUENCY MULTIPLIER CHAINS IN SiGe HBT TECHNOLOGY
Fig. 7. Measured output power of the 320-GHz doubler output harmonic
(mixer measurement, solid line), as well as the total output power within
the waveguide band registered by the absolute power meter (dashed) for the
0
corresponding half-frequency 7-dBm input signal.
V. RESULTS
The output power characterization of the 220- and 325-GHz
doublers, as well as the 325-GHz 18 multiplier chain are pre-
sented below. In each measurement, the voltage to the final
doubler circuit was optimized for maximum output power.
A. Active 325-GHz Doubler
A frequency sweep of the output power of the 325-GHz active
doubler measured with the calorimeter and the harmonic mixer
method is presented in Fig. 7. The voltage was set to 0.7 V
and the input drive power from the characterization equipment
was maximized, which corresponds to 7 dBm at 162.5 GHz.
The good agreement between the harmonic-mixer and the total-
power meter reading indicate that the output power is dominated
by the frequency-doubled signal. A maximum output power of
3 dBm is obtained at 325 GHz and the 3-dB bandwidth is
308–328 GHz.
Fig. 8 shows the doubler output power at 325 GHz for a swept
162.5-GHz input signal from 11 to 7 dBm. Included in the
graph is also a measurement of a separate breakout of the inte-
grated driver amplifier. This measurement used the calorimeter
as the power detector; hence, this measurement may overstate
the 160-GHz output power of the driver amplifier since har-
monics and spurious tones generated by the multiplier-based
measurement equipment add to the total power measured. As
seen in the graph, the 7 dBm of input power available from
the measurement system is sufficient to almost fully compress
the 160-GHz amplifier. The 5-dB difference in input power be-
tween the 1-dB compression point (CP1 dB) and the saturated
output power (Psat) of the amplifier is typical for SiGe power
amplifiers that have not been optimized for high linearity [4].
Note, although the amplifier breakout is the same circuit as used
in the active doubler, it is terminated differently in both cases,
and hence, can only be an indication of the available drive power
in the active doubler.
1315
Fig. 8. Output power of the 320-GHz doubler for a swept 162.5-GHz input
signal (measured with the harmonic mixer). For reference, the graph also in-
cludes measured results of a separate breakout of the integrated 160-GHz driver
amplifier.
Fig. 9. Measured output power of the 220-GHz doubler output (mixer mea-
surement, solid line), as well as the total output power within the waveguide
band (calorimeter, crosses) at a 0-dBm input signal level.
The compression characteristic of the doubler indicates that
the power of the driver is sufficiently high to saturate the doubler
output. The measured power sweep shows reasonable agree-
ment with the simulations presented in Fig. 3, which predict ap-
proximately 3-dBm output power with a 0.7-V bias voltage
and an 8–11-dBm drive power.
B. Active 220-GHz Doubler
Like the 325-GHz doubler, the 220-GHz doubler was an-
alyzed with the power and frequency sweeps. For maximum
output power, the voltage was reduced to 0 V. The col-
lector current of the multiplier transistors increased to 15 mA
compared to 12 mA in the 325-GHz doubler case, which can be
explained by a higher drive power from the integrated amplifier
at the lower operating frequency. Fig. 9 presents a frequency
sweep of the multiplier output power measured with both the
calorimeter and harmonic mixer. For this continous frequency
sweep, the output power of the external millimeter-wave source
module used to drive the integrated doubler was set to 0 dBm
in order to ensure that the source remained in saturation over a
1316 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 59, NO. 5, MAY 2011
Fig. 10. Output power of the 220-GHz doubler (harmonic mixer measurement)
0
with the input power swept from 18 to 0 dBm.
2
Fig. 11. Measured output power of the 18 multiplier chain (mixer measure-
ment, dashed line), as well as the total output power within the waveguide band
registered by the calorimeter (solid line) for the corresponding 1/18-frequency
0-dBm input signal.
wide bandwidth. Due to a rapid roll-off of the waveguide-system
insertion loss close to its cutoff, a poor calibration of the mixer
measurements was obtained. However, both the calorimeter and
mixer measurements show close to 1-dBm output power at
225 GHz with a 215–240-GHz 3-dB bandwidth.
In Fig. 10, a power sweep of the 220-GHz doubler is shown at
225 GHz. For a 112.5-GHz input signal, the doubler reaches sat-
uration at 0.5 dBm for a 13-dBm input drive level. Above the
compression point, the output power remains close to 1 dBm.
C. Integrated 18 325-GHz Multiplier Chain
The measured output power of the 18 325-GHz multiplier
chain, swept over the 315–330-GHz range is shown in Fig. 11.
This figure includes the calorimeter and harmonic mixer results
as described above. Within the 317–328-GHz frequency range,
the mixer measurement of the 18th harmonic and the total power
in the waveguide band show good agreement. The minimum
power in this range is 6 dBm and the peak power of 3 dBm is
reached at 325 GHz. Note, that outside of this frequency range,
Fig. 12. Measured output power at the 325-GHz design frequency for an
0 0
18-GHz input power swept from 8 to 2.5 dBm. The two triplers in the
chain are not sufficiently saturated to provide a stable 162.5-GHz drive to the
0
final doubler below 5-dBm input power.
significantly larger spurious tones appear at the output because
the multiplier stages in the chain are not fully saturated. Hence,
the two measurement techniques deviate from each other.
The power of the 325-GHz 18th harmonic with a 18-GHz
input power level swept from 8 to 2.5 dBm is shown in Fig. 12.
An input power level of 3 dBm is enough to sufficiently com-
press the multiplier chain at the 325-GHz design frequency.
However, a larger input drive level compresses the stages fur-
ther so that the operating bandwidth is extended. The measured
saturated output power is 3 dBm, which shows good agree-
ment with the 325-GHz doubler results.
The higher output power compared to the results reported in
[13] was obtained by an increase of the external supply voltage
to 4.3 V for the full tripler chain (including the 53- and 160-GHz
driver amplifiers). This was necessary to overcome the resistive
losses in the probe contacts and supply leads to reach the desired
4-V supply voltage on-chip. Hence, previously reported results
were not taken at the optimal bias points. With the corrected
supply voltage, the total current consumption of the input dif-
ferential converter, the two triplers and the five amplifier stages,
increases from 300 to 370 mA. This higher bias current also in-
creases the delivered drive power to the doubler, and therefore,
also its current consumption from 8.9 to 13 mA from its sepa-
rate 2-V collector supply.
The residual phase-noise contribution of the multiplier chain
was monitored on a spectrum analyzer, using the harmonic
mixer for down-conversion of the 325-GHz output signal.
Phase-noise levels of 83.6 and 101.2 dBc/Hz at a 100-kHz
and 1-MHz frequency offset were obtained, respectively. These
levels approximately correspond to the multiplied phase noise
of the microwave synthesizers used to drive the multiplier
chain and harmonic mixer in the measurement setup. Hence,
the residual phase noise introduced due to up-conversion of
low-frequency noise by the 18 multiplier chain is close to
or below the noise floor of the measurement setup. These
phase-noise measurements verify that the multiplier chain, if
driven from a low-phase-noise microwave source, does not
ÖJEFORS et al.: ACTIVE 220- AND 325-GHz FREQUENCY MULTIPLIER CHAINS IN SiGe HBT TECHNOLOGY
TABLE I
COMPARISON OF SOLID-STATE SUBMILLIMETER SOURCES
3-dB output power bandwidth
Peak output power
Nonoptimized measurement conditions
suffer from the typical phase-noise degradation seen in sub-mil-
limeter-wave VCO designs. For instance, a linear-superposition
VCO in [8] exhibited 78 dBc/Hz at a 1-MHz offset frequency
and a 286-GHz VCO in [20] obtained 96.6 dBc/Hz at a
10-MHz offset.
VI. CONCLUSION
Frequency doublers capable of providing 1 and 3 dBm
at 225 and 325 GHz, respectively have been demonstrated in a
silicon process technology. The 20–25-GHz bandwidth of these
doublers is primarily limited by the integrated driver amplifiers
and could be increased at the cost of a lower gain per driver
stage. In addition, the 325-GHz doubler circuit has also been
fully integrated into an 18 multiplier chain, enabling it to run
from an external 18-GHz microwave source without a notice-
able peak output power degradation. The work demonstrates
further that single-chip sub-millimeter-wave synthesizers could
be realized with the help of a lower frequency VCO, e.g., oper-
ating it at 18 or 53 GHz together with an on-chip phase-locked
loop (PLL). Possible applications for such sources include
active illumination for sub-millimeter-wave imaging, as well
as local-oscillator signal generation for sub-millimeter-wave
receivers. As shown in Table I, the output powers presented in
this work are comparable to such types of III–V-based MMIC
frequency multipliers, and they are significantly higher than
the peak power demonstrated by voltage-controlled oscillator
(VCO)-based implementations in CMOS and SiGe-HBT tech-
nologies. Improved SiGe HBT technologies [21] optimized
for higher gain and power-handling capabilities would allow
further device and doubler/driver circuit optimization in the
future.
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Erik Öjefors (S’01–M’06) received the M.Sc. de-
gree in engineering physics and Ph.D. degree in mi-
crowave technology from Uppsala University, Upp-
sala, Sweden, in 2000 and 2006, respectively.
In 2007, he joined the Institute of High-Frequency
and Quantum Electronics, University of Siegen,
Siegen, Germany. Since 2008, he has been with the
Institute for High-frequency and Communication
Technology, University of Wuppertal, Wuppertal,
Germany.
Dr. Öjefors was the corecipient of the 2007 IEEE
Antennas and Propagation Society (AP-S) R. W. P. King Award, the 2008
EuMIC Best Paper Award, and the 2010 EuMC Microwave Prize.
Bernd Heinemann received the M.S. degree in
physics from the Humboldt Universität zu Berlin,
Berlin, Germany, in 1984, and the Dr.-Ing. degree in
electrical engineering from the Technische Univer-
sität Berlin, Berlin, Germany, in 1997.
In 1984, he joined the IHP GmbH (now Inno-
vations for High Performance Microelectronics),
Frankfurt (Oder), Germany. His research activities
include the development and characterization of
MOS and bipolar devices. From 1984 to 1992, he
contributed to the development of epi-free 0.8-m
BiCMOS technology. Since 1993, he has been a member of a team involved
with the exploration and technological implementation of SiGe HBTs.
Ullrich R. Pfeiffer (M’02–SM’06) received the
Diploma degree in physics and Ph.D. degree in
physics from the University of Heidelberg, Heidel-
berg, Germany, in 1996 and 1999, respectively.
In 1997, he was a Research Fellow with the
Rutherford Appleton Laboratory, Oxfordshire,
U.K. In 2000, his research was based on real-time
electronics for a particle physics experiment with
the European Organization for Nuclear Research
(CERN), Geneva, Switzerland. From 2001 to 2006,
he was with the IBM T. J. Watson Research Center,
where his research involved RF circuit design, power amplifier design at 60
and 77 GHz, and high-frequency modeling and packaging for millimeter-wave
communication systems. In 2007, he lead the Terahertz Electronics Group,
Institute of High-Frequency and Quantum Electronics, University of Siegen,
Siegen, Germany. Since 2008, he holds the High-Frequency and Communica-
tion Technology Chair with the University of Wuppertal, Wuppertal, Germany.
Dr. Pfeiffer is a member of the German Physical Society (DPG). He was the
recipient of the 2007 European Young Investigator Award. He was the core-
cipient of the 2004 and 2006 Lewis Winner Award for Outstanding Paper pre-
sented at the IEEE International Solid-State Circuit Conference, the 2006 IBM
Pat Goldberg Memorial Best Paper Award, the 2008 EuMIC Best Paper Award,
and the 2010 EuMC Microwave Prize.