A New Current Source Converter Using A Symmetric Gate Commutated Thyristor
(SGCT)
Navid Zargari, Steven Rizzo, Yuan Xiao
Hideo Iwamoto, Katsumi Sato
John Donlon
Abstract- In recent years extensive semiconductor development
has gone into both bipolar and MOS structures for Medium
Voltage (MV) applications. However the progression of MOS
structures in MV applications has been difficult and the issues of
module isolation, reliability, and dv/dt and motor/bearing life
continue to limit its acceptance in these applications. A more
suitable device structure and the natural choice for MV
applications is the bipolar thyristor structure. The device that
has been in use for many years, the GTO, is being replaced by
the Gate Commutated Thyristor (GCT). So far the GCT has
been only thought of as fulfilling the needs for the voltage source
topology. However, the Symmetric GCT (SGCT) is viable and
has significant advantages when implemented in a PWM
Current Source Inverter. This paper will describe the design
and characteristics of an 800A, 6.5kV SGCT and the effect of its
implementation in a PWM-CSI. These effects include: operation
at a higher switching frequency, elimination/reduction and
modification of the snubber circuitry, reduction in size of the
passive components, and a major impact on the cost of the
converter. The paper includes experimental results on a 4160V,
1250hp, PWM-CSI AC drive.
I. INTRODUCTION
The semiconductor switch that has been dominant for
Medium Voltage (MV) applications, the GTO, is being
replaced by other alternatives [1,2]. Extensive research has
resulted in a push for high voltage MOS structure devices,
mainly HV-IGBTs. However, the module isolation issue still
limits the voltage of these structures. Also, there are design
issues such as dv/dt (resulting in motor insulation and bearing
problems) and reliability concerns associated with the IGBT
that have raised concerns when used in low and medium
voltage applications [3,4,5]. Over the past few years, a new
device has emerged, the Gate Commutated Thyristor (GCT).
A GCT is a GTO integrated with its gate driver through a low
inductance path. This arrangement results in an improvement
of the dv/dt, di/dt, and turn-off capability over the
conventional GTO. The non-uniformity of the current
redistribution during turn-off that has been the major
disadvantage of the GTO has been resolved by ensuring a
uniform turn-off process and uniform storage time. The GCT
can also operate at a higher switching frequency with no or
minimum snubber capacitance. The GCT that has been in use
so far, however, is an asymmetric type GCT that fulfills the
Rockwell Automation, Cambridge, ON, Canada
Mitsubishi Electric Company, Fukuoka, Japan
Powerex Inc., Youngwood, PA, USA
requirements for a Voltage Source Converter, i.e. one that
does not block reverse voltage.
This paper presents a Symmetric Gate Commutated
Thyristor (SGCT) that can block the voltage both in forward
and reverse directions up to 6500V. This device is most
useful in Current Source Converters where the current is uni-
directional but the voltage can assume both polarities. The
proposed SGCT includes all the features of GCTs plus a new
ring gate arrangement that further enhances the uniformity of
the storage time and increases the current turn-off capability.
Implementing the proposed 6.5 kV SGCT in a MV CSI-based
AC drive results in significant advantages over conventional
PWM-CSI drives [6]. These advantages include:
A) Simplification of the snubber design and a reduction in
the size of the snubber capacitor by a factor of twenty,
B) operation at a higher switching frequency, hence
reducing the size of passive components (by 50%) and
improving performance of the drive, and
C) reduction of component count, hence improving
reliability, cost, and size of the drive.
The paper includes the design criteria and characteristics of
a 6.5kV, 800A SGCT and design principles and experimental
results on a 4160V, 1250hp PWM-CSI AC drive.
II. BRIEF REVIEW OF PWM-CSI AC DRIVE
A Current Source Inverter-based AC drive is shown in
Fig. 1. The inverter has current-source characteristics at the
dc terminal (dc side reactor) and voltage-source
characteristics at the ac terminal (ac side capacitor).
Operating the six switches interfaces the ac and dc sides.
These switches must be operated so as to avoid an open
circuit on the dc link or a short circuit on the ac side. This
means that at any given time there are only two switches
conducting, one in the top half of the bridge and one in the
bottom half. Fig. 2(a) depicts the current waveform for the
semiconductor switch for a typical seven pulse switching
pattern. The switch voltage waveform is shown in Fig. 2(b).
From these figures one can see that the switches must carry
uni-directional current while blocking bi-directional voltage.
The inverter output current and the line-to-line motor voltage/
current are also shown in Fig. 2(c) and Fig. 2(d) respectively.
 rectifier dc link inverter
M (unity turn-off gain), low inductance and low resistance are
Fig. 1. A PWM-CSI based AC drive.
Fig. 2. Typical waveforms for a CSI, from top to bottom: (a) device
current, (b)device voltage, (c) inverter output current, (d) motor current and
voltage.
Fig. 3. The 6.5kV/800A SGCT and its wafer.
III. SGCT DESIGN A ND CHARACTERISTICS
A. SGCT and Gate Drive Circuit
The new 6.5kV/800A SGCT and its silicon element is
shown in Fig. 3. Its package is 26mm in thickness with
47mm diameter pole electrodes. Fig. 4 shows the cross-
sectional structure of the SGCT. There is a ring gate terminal
on the inner side of the SGCT and the whole peripheral gate
electrode area on the chip is connected to this terminal inside
the package. Contact between the terminal and the electrode
via a gate ring is secured by pressure from a scroll spring
inside the package.
In order to establish the desired commutation operation
required for the SGCTs package and its gate drive circuit.
There are six gate terminals on the side of the SGCT that are
connected to the cathode cap through six terminals and to the
gate drive circuit by a multiple laminated substrate. The gate
drive circuit consists of the substrate, MOSFETs in parallel,
and capacitors in parallel. These parts are connected in series
to form the gate driver circuit. The arrangement, as shown in
Fig. 5, results in a total inductance [Lin] of the gate drive
circuit including the SGCT that is about 7nH (one hundredth
of that of a conventional GTO). The rate of rise of the gate
current is calculated as:
Vg 21V
di GQ / dt = = = 3000 A / s
Lin 7 nH
where Vg is the gate voltage. This high diGQ /dt gives
superior turn-off capability without requiring a snubber as
with a conventional GTO.
B. Wafer Design
The SGCT achieves voltage blocking capability in both
forward and reverse directions by NPT (Non-Punch-Through)
structure and nearly symmetrical pnp (p B-n B-p E ) transistor in
the wafer (no anode shorts). Fig. 6 shows a unit cell structure
in the SGCT wafer. The NPT structure provides high turn-off
and high di/dt capability but its thick n base layer (n B)
increases the on-state voltage (VTM ), the turn-off energy
(Eoff), and the recovery energy (Erec). Increasing these values
has a major influence on system losses. In order to improve
these parameters, MEPLT (Multi Energy Proton Lifetime
control Technology) is adopted and the lifetime controlling
condition is optimized. Using MEPLT, the chip is irradiated
several times by various accelerating energies. Proton
irradiation makes it possible to locally reduce the life time at
a fixed depth from the chip surface. The depth of the reduced
lifetime region is fixed by the accelerating energy value as
shown in Fig. 6(b). That depth influences both turn-off and
recovery characteristics. Fig. 7(a) shows the dependence of
turn-off characteristics such as turn-off dv/dt, turn-off tail
current (ITtail) and Eoff on that position. Fig. 7(b) shows the
dependence of recovery characteristics such as maximum
recovery current (IRM), maximum recovery voltage (VRM ),
recovery tail current (IRtail) and Erec on that position. When the
lifetime near J3 is reduced, Eoff becomes smaller. It is mainly
influenced by the turn-off dv/dt and is not much influenced
by Itail . When the lifetime near J1 is reduced, Erec becomes
smaller. It is mainly influenced by IRM and is not much
influenced by IRtail. It is seen by Fig. 7(b) that decreasing IRM
is effective for decreasing VRM.
Using these features as a basis, the MEPLT process is
optimized for the 6.5kV/800A SGCT chip and results in
dramatic improvement in VTM, Eoff, and Erec as compared with
the conventional symmetrical GTO. The MEPLT technique is Cathode
quite suitable to the production of SGCTs with high turn-off Gate
capability over a wider range of VTM than can be achieved by
conventional NPT structure and GCT technology. Cathode
nE J3
C. Edge Termination pB (nE p B junction)
J2
(pBn B junction)
The symmetrical device with high voltage blocking
nB
capabilities has a pnp transistor and double positive bevel Low lifetime
structure at the edge termination. The double positive bevel area

structure results in a higher local electric field at a given

blocking voltage than other edge termination structures such J1
(nB pE junction)
as positive bevel structure. The pnp transistor structure has an pE
amplification function that makes the symmetrical device
Anode Lifetime
sensitive to edge contamination. Therefore, it is important to Anode short long
reduce the electric field at the edge termination in order to get
(a) (b)
high blocking stability. The surface electric field of the new Fig. 6. (a) Unit cell structure. (b) Lifetime distribution by MEPLT.
double positive bevel structure is about 80% of that of the
conventional double positive bevel structure and is similar to
that of the single positive bevel structure adopted in high
voltage diodes. By this, the new bevel structure achieves high
voltage blocking stability. The surface electric fields at J1 J2 J3

Large
4800V for this SGCT with the new double positive bevel
structure, for this SGCT with the conventional double Eoff
positive bevel structure and for a conventional diode with
dv/dt/I Ttail/Eoff

single positive bevel structure are shown in Fig. 8.

Cathode electrode Gate terminal Scroll spring dv/dt

I Ttail
Small

Gate ring Anode Cathode

(electrode) Lifetime reduced position

(a)

GCT chip Mo disks J1 J2 J3

Large

Ceramic seal Anode electrode

E rec
IRM/VRM/IRtail/Ere

Fig. 4. Cross-sectional structure of SGCT.

VRM

IRM

IRtail
Small

Anode Lifetime reduced position Cathode

(b)
Fig.7. (a, top )The dependence of turn-off dv/dt, turn-off tail current(I Ttail)
and Eoff on lifetime reduced position (b, bottom)The dependence of
maximum recovery current(I RM), maximum recovery voltage(VRM), recovery
tail current(IRtail) and Erec on lifetime reduced position.

Fig. 5. The 800A, 6500V SGCT with the integrated gate drive.
 1.2E+05
D. Device Characteristics
Single positive bevel Conventional double
1.0E+05 positive bevel Fig. 9 shows the typical turn-off waveform at ITQRM=2kA
Electric field at beveled surface[V/cm]

on a 3000V bus at Tj =25C. Storage time (defined as from

8.0E+04 New double the input of the gate signal to the start of the fall of the anode
positive bevel current) is about 2s. It should be noted that the turn-off
6.0E+04 current is well above the rating of the device (800A). Fig. 10
shows the typical reverse recovery waveform at IT (on-state
4.0E+04 current)= 800A, diT/dt=1.2kA/s, VR =-3700V and Tj =115C.
By optimizing lifetime distribution using MEPLT, as Erec
2.0E+04
decreases with decreasing VRM and IRM, recovery capability is
enhanced. Therefore, the new SGCT achieves both high turn-
0.0E+00
off and high recovery capability while maintaining low
0 200 400 600 800 1000 1200
Distance from cathode surface[ m ] losses. Some of the more important characteristics of the
6.5kV/800A SGCT are given in Table I.
Fig. 8. The surface electric field simulation for various bevel structure. TABLE I
Major Characteristics of 6.5kV/800A SGCT
Item Symbol Conditions Limits
Controllable I TQRM VD=3000V 800A
on-state current Clamp snubber
Off-state VDRM VRG -2V 6500V
VG=0V voltage
VG VRG Reverse voltage VRRM 6500V
On-state VTM Tj= 115C, 4.8V
Storage time( ts) voltage I T=400A
<2 s Gate trigger I GT VD=24V 0.5 A
current
VDM Turn-on loss Eon I T=400A, VD=VR =3 0.4 J
VA Turn-off loss Eoff kV, Tj=115C 2.4 J
Recovery loss Erec Clamp snubber 3.0 J
IT=2kA di/dt=1kA/s
VD =3kV
I A:500A/div
Turn-off delay td I T=800A, 1 s
time VD=3kV, Tj=115C
VA:1kV/div
VG:20V/div Storage time ts Clamp snubber 3 s
IA di/dt=1kA/s
Time:2s/div
I=0A V=0V Thermal Rth(j-f) Junction to fin 0.025C/W
impedance

Fig. 9. The typical turn-off waveform.

IV. IMPLEMENTATION OF SGCT IN A PWM-CSI

Implementing a SGCT in a current source converter can

IA result in significant system improvements. These are
discussed below.
IT=800A
I=0A V=0V A. Snubber Circuitry

IRM The turn on and reverse recovery di/dt capability of

di/dt=1.2kA/s VR=3.7kV SGCT are increased to 1000A/s. This allows for a
significant reduction of the size of the di/dt limiting reactor.
VRM In Medium Voltage applications often a series connection of
two or more devices are used. The series connection requires
VA a resistor for static voltage sharing which is calculated from:
V1
R sh = (1)
IA:500A/div I rrm
VA:1kV/div
Time:2s/div where Rsh is the sharing resistor, V1 is the maximum voltage
Fig. 10. The typical reverse recovery waveform. unbalance desired and IRRM is the allowable tolerance for
the reverse leakage current. The value of Rsh is usually
 dc+
practical aspects of the snubber design that must be
didt reactor didt reactor considered are the power dissipation of the snubber resistors
RD RS and the rms current and voltage rating of the capacitor.
GTO SGCT
D RSH B. Loss Calculation

CD Due to the improvement of the switching speed of the

CS
SGCT and because of the small snubber used, the switching
RS frequency of the SGCT can be increased. This will result in
higher switching losses. However, reduction of the snubber
circuitry and the di/dt limiting reactor result in lower snubber
CS
losses and the total loss of the inverter can be significantly
Phase A Phase A lower. Losses for the GTO and SGCT inverters are compared
and results are shown in Table III. These results are for a
Fig. 11. (left) An inverter leg using GTO, (right) an inverter leg using
1250hp 4160V drive and are based on the design given in
SGCT. Table II. The losses are obtained by first measuring the
device voltage and current at the time of switching from
between 20k-100k. The dynamic voltage sharing of simulation (e.g. Fig. 2) and then calculating the switching
devices is achieved by implementing a small RC circuit. The losses based on the device data sheet (e.g. Table I).
values of R and C are chosen by limiting several transient
voltages to acceptable levels. First is the effect of the turn on
TABLE II
and turn off delay times which is given by the following: DESIGN T ABLE BASED o n P ER UNIT VALUES
t I
V2 = d (2) Item PWM CSI PWM CSI Comments
C with GTO with SGCT
Di/dt 1 pu 0.1 pu
where td is the tolerance in the overall turn off delay time, I reactor
is the commutatable current and C is the capacitor in the RC RD 1 pu 0 pu Diode eliminated
circuit. The recovery voltage unbalance has to be limited as CD 1 pu 0 pu Diode eliminated
well. This adds another criterion for choosing the capacitance Rs 1 pu 0.5 pu
Cs 1 pu 0.05 pu 1/20 size of GTO
value, given by: Rshare 1 pu 2.5 pu
Q rr
V3 = (3) Fsw 1 pu 3 pu Switching frequency
C trippled
where Qrr is the reverse recovery charge. Since the switching
times of the SGCT have been much improved, only a small TABLE III
capacitor is required to meet the criteria given by (1)-(3). The LOSS COMPARISON T ABLE
same capacitor can also act as the snubber for the SGCT if Item PWM CSI-SGCT PWM CSI-GTO
the following criteria are met: With 420Hz With 180Hz
Switching frequency Switching frequency
v The RC time constant must be small enough to allow fast Conduction loss 1.0 1.0
charge and discharge for the capacitor and allow for high Switching loss 0.42 0.27
switching frequency operation with short pulse widths. Switching freq. 420Hz 180Hz
v The voltage overshoot during turn off and reverse Device loss 1.42 1.27
recovery must be limited to acceptable values. Snubber loss 0.46 1.28
Total 1.88 2.55
v Proper damping in the snubber circuitry must be device+snubber
obtained.
v The resistor should be large enough to limit the
charge/discharge current. C. Passive Filter Components
The sharing resistor Rsh , and the RC snubber components are
designed based on the above criteria. Fig. 11 depicts the 1) Design of the output capacitor: As previously mentioned
typical inverter leg using a GTO and that of using a SGCT the switching frequency of the converter can be increased.
design. It can be seen that the conventional RCD snubber is Increasing the switching frequency inherently improves the
eliminated. The RC snubber that is used for the SGCT harmonic spectrum and requires a smaller filter to achieve the
inverter employs capacitors that are twenty times smaller than same quality (same THD) waveforms. This is because higher
the GTO snubber capacitor. The small snubber circuit switching frequency moves the harmonics to a higher order
arrangement has much lower loss and allows simpler which are easier to mitigate by small low pass filters. The
packaging and new assembly arrangements. Table II lists the harmonic spectra for the inverter output current with three
components in the inverter leg for both designs. Other
different switching frequencies are depicted in Fig. 12. It can
be noted that filtering the harmonics in the bottom figure
(Fsw=540Hz) is easier than the other two cases (lower Fsw).
The output filter capacitor is designed considering the
following issues:
v By properly positioning the filter break point, the
harmonic resonances between the capacitor and the
motor reactances are moved to a safe region where no
residual harmonics exist.
v The capacitor is sized in such a way to meet specific
THD requirements for both motor voltage and current
waveforms.
Design of the capacitor itself require special attention to the
current and voltage rating of the capacitor. These are
calculated allowing for the maximum harmonic currents
injected from the inverter side and the fact that the motor is
allowed to operate continuously at speeds above 60Hz.
Fig. 12. Harmonic spectra of inverter output current for three different
switching frequencies: top to bottom, 300Hz, 420Hz and 540Hz.
2) Design of the dc link reactor: The main criterion for the
design of the dc link reactor is to keep the current ripple
within an acceptable level (e.g. 20%). The size of the dc link
will depend on the front-end topology used as different
topologies result in different harmonic spectra and require
different size of inductors to satisfy the design criterion.
There are three different possibilities for the front-end
rectifier: a 6pulse thyristor rectifier, an 18 pulse thyristor
rectifier or a PWM rectifier. The 18 pulse SCR rectifier meets
IEEE-519 by employing a multi-winding isolation
transformer. The PWM rectifier which is a replica of the
inverter also meets IEEE-519 and uses the same SGCT
devices. The PWM rectifier offers a better Power Factor [6],
an overall size reduction and improved efficiency since it
does not require an isolation transformer for harmonic
cancellation. The harmonic mitigation is achieved by
switching at only 420Hz (Fig. 12).
V. EXPERIMENTAL RESULTS ON A 4160V PWM-CSI AC DRIVE
A 6.5kV 800A SGCT is tested in a 4160V PWM-CSI
AC drive. This configuration uses two devices in series with
the design being similar to that given in Table II. The turn on
waveforms are shown in Fig. 13. The turn on time is reduced
to 2-3s and the tail time is significantly reduced. The turn-
off and recovery waveforms are already discussed in Figs. 9
and 10 and therefore are not shown anymore. The device
current and voltage waveforms are depicted in Fig. 14. A
Selective Harmonic Elimination pattern with seven switching
per half-cycle is used to operate the inverter. The angles are
calculated to eliminate the 5th , 7th and 11th harmonics. The
switching waveforms confirm proper operation of the SGCT
with high di/dt, high dv/dt and a small RC snubber. The
motor voltage and current waveforms are shown in Fig. 15.
The THD of the current waveform is less than 2.5%. The
motor line-to-line voltage is sinusoidal without he presence of
any voltage steps or high dv/dt waveform. This is one of the
main advantages of CSI drive where the motor insulation is
not subjected to high dv/dt and chopped voltage waveforms
as is the case for any type of Voltage Source Inverter (VSI)
based ac drives.
VI. CONCLUSION
A Symmetric Gate Commutated Thyristor with full
reverse voltage blocking capability is proposed in this paper.
A ring gate arrangement ensures uniformity of the storage
time and improves the current commutation capability as
compared to conventional GTOs. The developed SGCT is a
6500V 800A device and is most suitable for CSI-based MV
AC drives. The implementation of the SGCT in PWM-CSI ac
drives is discussed and design issues are investigated. The
results show that the PWM-CSI with SGCT can operate at a
higher switching frequency and requires smaller passive filter
components, improving the performance of the drive.
Moreover, the conventional RCD snubber can be replaced
with a small RC snubber resulting in a reduction of size and
component count and enhancing the reliability of the system
REFERENCES
[1] K. Satoh, M. Yamamoto, T. Nakagawa and K. Kawakami, A new high
power device GCT (Gate Commutated Turn-Off) Thyristors, In Conf.
Rec. EPE97, pp. 70-75, 1997
[2] H. Gruening, B. Odegard, A. Weber, E. Carroll and S. Elcher, High
Power Hard-Driven GTO Module for 4.5 kV/3kA Snubberless
Operation, in Conf. Rec, PCIM96, pp.-, 1996
[3] S. Bernet, R. Teichmann, A. Zuckerburger and P. Steimer,
Comparison of high power IGBTs and hard-driven GTOs for high
power inverters, in IEEE Trans. on Ind. Appl.., vol. 35, no. 2, pp.
487-493, March/April 1999.
[4] D. Rendusora and P. Enjeti, An improved inverter output filter
configuration reduces common mode and differential modes dv/dt at
motor terminals in PWM drive systems, in IEEE Trans. on Pow. Elec.,
vol. 13, no. 6, pp. 487-493, November 1998.
[5] S. Bhattacharya, L. Resta, D. Divan and D. Novotny, Experimental
comparison of motoring currents with PWM hard and soft swicthed
 voltage source inverters, in IEEE Trans. on Pow. Elec., vol. 14, no. 3,
pp. 552-562, May 1999.
[6] N. Zargari, Y. Xiao and B. Wu, A PWM CSI-based vector controlled
medium voltage AC drive with sinusoidal input and output
waveforms, in Conf. Rec. IEEE-IAS97, pp. 768-774, 1997.
[7] S. Rizzo, B. Wu and R. Sotudeh, Symmetric GTO and snubber
component characterization in PWM current source inverters, in IEEE
Trans. on Ind. Appl., vol. 13, no. 13, pp. 617-625, July 1998.

0 Fig. 15. Motor current and voltage waveforms., 4000V, 1250hp induction
motor (200A/div, 4200V/div, 5ms/div).

Fig. 13. Turn on waveform (200A/div, 1000V/div, 2s/div).

Fig. 14. The voltage and current waveform of SGCT with 420Hz switching
frequency, full load, full speed, 1250hp, 4160V AC drive. (200A/div,
1000V/div, 2ms/div).