Isolated gate driver for SiC MOSFETs with constant

negative off voltage

QinsongQian a, Juzheng Yu a, Junjie Zhu a, Weifeng Sun a and Yangbo Yi b

a
National ASIC System Engineering Research Center, Southeast University, Nanjing, Jiangsu, P.R.China 210096,
b
Wuxi Chipown Micro-electronics limited, Wuxi, Jiangsu, P.R.China 214028
swffrog@seu.edu.cn

Abstract—In recent years, more and more SiC power
semiconductor switches have become available, showing their
superior behavior for power electronics. To fully exploit the
potential of the SiC MOSFET, conventional gate drivers for
silicon devices must be adapted to this device due to its special
requirements. An isolated gate driver for SiC MOSFETs with
constant negative off voltage is presented in this paper. Firstly,
the isolation and the floating ground driving are provided by a
coupled transformer. Then a negative turn-off voltage is realized
by a voltage clamp circuit made up of resistors, capacitors and
diode. Moreover, a controllable voltage is introduced to
compensate the variable duty ratio and constant off voltage is
achieved. As a result, the spurious turn-on phenomena of SiC
MOSFETs can be avoided. As isolation, floating ground and
constant negative voltage with variable duty ratio are obtained,
the proposed gate driver can be widespread utilized in lots of
topologies.
due to the smaller gate capacitance and the higher switching
speed. Also, for SiC MOSFET, the threshold gate voltage is
usually lower, about 2.5V [2].
Therefore, in a phase-leg configuration, to fully utilize the
potential advantages of fast SiC devices and guarantee the
reliability of the power converter, crosstalk should be
suppressed.
A typical method in the engineering field is designing a
level shift circuit, as shown in Fig. 1(a). An isolated gate-drive
chip is employed to drive the 2 power MOSFETs, and the Cb1,
Dn1, Rgd1 are the components of the level shift circuit.

Keywords—Isolated gate driver; silicon carbide; bridge-leg

configuration; negative gate voltage; spurious turn-on.

I. INTRODUCTION
Recently, switching device performance has been enhanced
with the development of wide band-gap materials, which allow
higher temperature operation, reduced switching times, and
low conduction losses [1]. Compared to the silicon power
MOSFETs, the SiC power MOSFETs have the advantage such
as low gate-drive loss, low switching loss and low RDS(on). Also,
the SiC power MOSFET can still be operating under 600ºC,
which is significantly high compared with conventional Si
power MOSFETs. However, compared to Si power MOSFETs,
disadvantages such as lower threshold voltage and negative
gate-source breakdown voltage limit the applications of SiC
power MOSFETs in bridge circuits.
Usually, the gate drive circuit of the SiC power MOSFETs
in single switch topologies such as flyback converter, Boost
converter and CCFL converter do not require a negative
shutdown voltage. However, due to the higher switching speed
and smaller gate capacitance, during a fast switching event, the
miller capacitor current of the complementary device in the
bridge-leg configuration can significantly alter the gate voltage
of the switch and thus creates undesirable conditions, which is Fig. 1. A typical gate drive circuit in phase leg configuration (a) the scheme
called “crosstalk” between the switches in the same phase leg of the circuit (b) test results under 1MHz
[2]. This phenomenon is much more severe for SiC devices

978-1-5090-5366-7/17/$31.00 ©2017 IEEE 1990

 This popular scheme is tested, as shown in Fig. 1(b). The
negative shutdown voltage ensures the reliability of the SiC
power MOSFETs. However, the scheme shown in Fig. 1(a) is
too expensive because of the isolated gate-drive chip. Although
the chip can be replaced by the non-isolated gate-drive chip,
the cost is still higher than the transformer based method, and
the isolation would fail, which is unaccepted for the industrial
and vehicular applications.
On the other hand, prior reported works have proposed
several methods for crosstalk mitigation [3-6]. However,
isolation between the driver signals and the power circuits,
which is popular in off-line converters with bridge legs, is hard
to be realized in the gate driver proposed in [3] as several
active switches are needed. The negative voltage of the gate
driver in [4] would vary with the duty ratio, and there is a very
limited amount of negative voltage one can apply on the gate,
which is about -5V [2]. Meanwhile, the gate drivers in [5] [6]
need additional voltage source which shares ground with the
source node of the MOSFETs, thus they cannot be applied in
the bridge topologies with floating ground.
In this paper, we propose an isolated gate driver for SiC
MOSFETs with negative off voltage. The negative voltage is
constant with variable duty ratio and the auxiliary voltage
source can be directly obtained from the gate driver voltage
source, therefore the proposed gate driver can be applied in lots
of topologies, especially for bridge-leg configurations.
II. THE PROPOSED GATE DRIVER
The proposed gate driver is shown in Fig. 2. The
transformer T and the blocking capacitor Cb are used to realize
the isolation between the drive signal and the power MOSFET.
Thus the gate driver can be used in the bridge legs with
floating ground.
Fig. 2. Proposed gate driver with constant negative voltage.
Meanwhile, there are some important differences to
improve the gate driver performance. First, the negative
voltage clamp circuit consists of two capacitors, C1 and C2,
two resistors, R1 and R2 and one clamp diode D. It is shown in
Fig. 2. With the negative voltage clamp circuit, the SiC MOS
can be turned off with negative voltage. As C2 is paralleled
1991
with the parasitic gate-to-source capacitor Cgs and the value of
C2 is much larger than Cgs, the negative voltage can be nearly
constant during the transition interval. The negative voltage
can be expressed as [4]
R2
Vgs   dVd (1)
R1  R2
where d is the duty ratio of the drive signals. Thus the SiC
MOSFET can be turned off with negative voltage.
III. DUTY RATIO COMPENSATION CIRCUIT
However, it can be seen from (1), the negative voltage
changes with the duty ratio d. And the change of the duty ratio
is very common in modern digital-control systems. Meanwhile,
as mentioned before, there is a very limited amount of
negative voltage one can apply on the gate. Therefore, it is
necessary to keep the negative voltage constant with variable
duty ratio. The duty ratio compensation circuit is introduced in
the proposed gate driver to keep the negative voltage constant
even with variable duty ratio. This circuit is composed of an
auxiliary voltage source dVc and two series-connected
transformers, TM and TA. The auxiliary voltage source dVc is
directly derived from the gate driver energy source and
applied to the series connected transformers. The energy
carried by the two series-connected transformers is very small.
Specifically, the energy carried by TM is less than 20% of that
of the main transformer T, while the energy carried by TA is
less than 10% of that of the TM [7]. Thus, the two series-
connected transformers are easy to implement in practice and
additional cost are low. From Fig. 2, the series connection of
TM and TA gives
V A  VM  dVd (2)
n1VA  n2VM  dVc (3)
where n1 and n2 is the turns ratios of the two series connected
transformers.
Meanwhile, combined with the effect of the series
connected winding of TM, the gate-to-source voltage during
the turn-off interval can be expressed as
R2 R1
Vgs   dVd  kVM (4)
R1  R2 R1  R2
VM can be deduced from (2) and (3). As a result, (4) can be
rewritten as
1  n1 dVc 
Vgs   ( R2  kR1 )dVd  kR1  (5)
R1  R2  n2  n1 n2  n1 
In (5), there are two items which would vary with the duty
ratio d. Among them, the second item contains the controllable
AC generator Vc. In contrary, the first item would
monotonously increase with larger duty ratio as the driver
signal Vd is constant. Therefore, it is necessary to eliminate the
first item of (5) by selecting proper values of R1, R2, k, n1 and
n2. From (5), the first item can be eliminated with following Vgs1
equation. 5V/div
-2V
R2 kn1
 (6)
R1 n2  n1 d=0.7 d=0.7

Thus, with (5) and (6), the negative voltage across the gate- d=0.3
to-source terminals during the turn off interval in the proposed
gate driver can be deduced as -2V Vgs2
5V/div
kR1
Vgs   dVc   dVc (7)
( R1  R2 )(n2  n1 )
Time(2µs/div)
In (7), ε is a constant decided by R1, R2, k, n1 and n2. By
considering the transient response of the circuit and (6), the Fig. 4. Gate-source voltage waveforms with proposed gate driver.
value of these parameters can be selected [4]. Therefore, the
variable negative voltage can be compensated by the AC Meanwhile, the switching performance of the gate driver
generator Vc. The value of Vc changes with the variable duty would not be influenced by the auxiliary circuits including the
ratio d and keeps the negative voltage constant. Besides, in negative voltage clamp circuit and the duty ratio compensation
order to avoid large extent of the change scope of the AC circuit. The experimental waveforms in Fig.5 show the
generator Vc, the constant ε should be selected properly. switching performance of the SiC MOSFET of the tested
converter. The turn-on and turn-off speed of proposed gate
driver would not be limited. The turn on and turn off time of
IV. VERIFICATION AND DISCUSSION
the gate voltage are 207ns and 193ns, respectively. What’s
The proposed gate driver is built and tested in an more, zero voltage switching can be realized.
asymmetric phase-shifted full-bridge converter [8] with SiC
MOSFETs. The topology of the test converter is shown in Fig. TABLE 1. Key parameters of the proposed gate driver.
3, which is used as a battery charger. The input voltage is
R1 R2 C1 C2 k n1 n2 Vc
fixed at 310Vdc, and the load varies from 5A to 15A.
15k 50 0.47μ 0.22μ 1~10
2 3/4 1
Ω kΩ F F V
DR1 Lf
Q1 Q3
LR Tr Cf VO
..
Vin
.
Vpri Lm . Battery
Vgs1 Vds1
Load
5V/div 100V/div
Q2 Q4

DR2

Fig. 3. The asymmetric phase-shifted full-bridge topology of the test ZVS is achieved
converter.

The key parameters of the built gate driver are shown in Toff=193ns Ton=207ns
Table 1. Fig.4 shows the gate-source voltage waveforms of the
MOSFETs in the same leg. The switching frequency is about Time(500ns/div)
80 kHz and the duty ratios of the MOSFETS are both not
equal to 0.5. Specifically, they are 0.3 and 0.7 separately. It Fig. 5. Switching performance of the SiC MOSFET of the tested converter.
can be seen that the negative turn-off voltage is almost
constant at -2V with different duty ratios. Additionally,
voltage spike and ringing are hardly observed. V. CONCLUSION
An isolated gate driver for the safe operation of the SiC
MOSFETs is presented. By introducing a duty ratio

1992
compensation circuit, the negative turn-off voltage can be
constant even with variable duty ratio. To be specific, the
negative off voltage keeps at -2V when the duty ratio varies
from 0.1 to 0.9. As the threshold gate voltage is usually lower
and there is a limited amount of negative voltage one can
apply on the gate, the constant negative voltage applied on the
SiC MOSFETs provided by the proposed gate driver could
avoid the spurious turn-on phenomena. Moreover, the negative
voltage is constant with variable duty ratio. Experimental
results confirm the switching speed, the constant negative off
voltage and the good waveform shape of the proposed gate
driver. Thus the proposed gate driver can be widespread
utilized in lots of topologies, especially for bridge-leg
configurations.
ACKNOWLEDGMENTS
This work was supported by the Qing Lan Project and
Suzhou Application Basic Research Project (SYG201450).
REFERENCES
[1] Biela, J., Schweizer, M., Waffler, S., and Kolar, J.W.: ‘SiC versus
Si-evaluation of potentials for performance improvement of
inverter and DC-DC converter systems by SiC power
semiconductors’, IEEE Tran. Ind. Electron. , 2011, 58, (7), pp.
2872 – 2882
1993
[2] Zheyue Zhang, Fred Wang, Leon Tolbert, B. J. Blalock, ‘A gate
assist circuit for cross talk suppression of SiC devices in a phase-
leg configuration’, IEEE Energy Conversion Congress and
Exposition 2013, pp.2536-2543.
[3] Hwu K I, Yau Y T, ‘A gate driver with negative and double
positive output voltages under positive-voltage source’, Applied
Power Electronics Conference and Exposition, 2008. APEC 2008.
Twenty-Third Annual IEEE. IEEE, 2008:627-629.
[4] Wang J, Chung S H, ‘A novel Rcd level shifter for elimination of
spurious turn-on in the bridge-Leg configuration,’ IEEE
Transactions on Power Electronics, 2015, 30, (2), pp: 976 - 984.
[5] Z. Zhang, F. Wang, L. M. Tolbert, and B. J. Blalock, ‘Active gate
driver for cross talk suppression of SiC power devices in a phase-
leg configuration,’ IEEE Trans. Power Electron., vol. 29, no. 4, Apr.
2014, pp. 1986–1997.
[6] Q. Zhao and G. Stojcic, “Characterization of Cdv/dt induced power
loss in synchronous buck DC-DC converters,” IEEE Trans. Power
Electron., vol. 22, no. 4, Jul. 2007, pp. 1505–1513.
[7] Jose A. Carrasco, Alan H. Weinberg, Esteban Sanchis and Enrique
J. Dede, “A Conductance-Controlled Variable Transformer Turns
Ratio Regulator for a Zero-Voltage–Zero-Current Power Switching
Converter,” IEEE Trans. Power Electron., vol. 14, no. 6, Nov. 1999,
pp. 1070–1077.
[8] P. Das, M. Pahlevaninezhad and G. Moschopoulos, “Analysis and
Design of a New AC–DC Single-Stage Full-Bridge PWM
Converter With Two Controllers,” IEEE Trans. Power Electron.,
vol. 60, no. 11, Nov. 2013, pp. 4930–4946.