5306
12, DECEMBER 2019
Fast SiC Switching Limits for Pulsed
Power Applications
Landon Collier , Member, IEEE, Taiga Kajiwara, Student Member, IEEE, James Dickens, Senior Member, IEEE,
John Mankowski, Senior Member, IEEE, and Andreas Neuber , Fellow, IEEE
Abstract— Solid-state semiconductor switches are emerging as
an attractive choice for the fast switching of compact, repetitive,
and pulsed power systems. In particular, the high voltage and
fast switching capabilities of SiC MOSFETs are well suited
for many applications when appropriately gated. For instance,
the turn-on and turn-off characteristics of such devices are
strongly dependent on the gate driving circuitry. Traditional
commercial gate drivers, typically utilizing push–pull or totem-
pole driving topologies, are often not well suited for fast, high
current switching with rise times on the order of 10–20 ns, as the
driving performance is highly dependent on the combined RLC
characteristics of the driving circuitry and the switching device.
The proposed gate drive topology utilizes a current-carrying
inductor to rapidly charge the MOSFET gate–source capacitance.
A high-voltage inductive kick generates the necessary potential
to drive the inductor current into the gate through the parasitic
gate impedance. As the energy stored in the drive inductor is
continuously variable, it can be adjusted such that the gate
voltage settles to a lower value, typically 20 V, after the initial kick
to prevent excessive gate–source overvoltage. With an inductive
drive current of ∼23 A, a peak dI/dt of 25 kA µs−1 was achieved
for the tested bare SiC MOSFET die. Additionally, a peak dI/dt
of 13 kA µs−1 was achieved with the TO-247 packaged device.
Index Terms— MOSFETs, pulse circuits, pulse generation,
pulsed power switching, pulsed power systems, semiconductor
devices, silicon carbide (SiC).
I. I NTRODUCTION
M ODERN developments in compact pulsed power gener-
ation utilize fast semiconductor switches to switch high
voltages and currents [1]–[3]. In many of these applications,
specifically those which require flat-top pulses, fast rise and
fall times are often desirable. Although the inductance of
the primary discharge is a factor, the ultimate limitation on
achievable rise time is governed by the turn-on and turn-
off capabilities of the switching element. While commercially
available gate drivers utilize the standard totem pole topology
with 20/−5 V rails, a more aggressive approach to driving the
gate with a higher voltage has been shown to significantly
Manuscript received January 8, 2019; revised May 10, 2019; accepted
June 21, 2019. Date of publication July 23, 2019; date of current version
December 11, 2019. The review of this article was arranged by Senior Editor
S. Gitomer. (Corresponding author: Landon Collier.)
L. Collier, J. Dickens, J. Mankowski, and A. Neuber are with the Center for
Pulsed Power and Power Electronics (CP3 E), Texas Tech University, Lubbock,
TX 79409 USA (e-mail: landon.collier@ttu.edu).
T. Kajiwara is with the Department of Computer Science and Electrical
Engineering, Kumamoto University, Kumamoto 860-8555, Japan.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPS.2019.2928535
0093-3813 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 47, NO.
improve the switching speed [4]–[6] in pulsed scenarios.
For example, high dI /dt of up to 2.6 kA/µs−1 was achieved
in [5] using a SiC MOSFET with a gate drive voltage of 80 V.
For high-voltage pulsed applications, wide bandgap semi-
conductors, such as SiC MOSFETs, have a number of distinct
advantages over traditional Si switches including low on-state
resistance and high hold-off voltage capability [7], [8]. The
switching characteristics of power MOSFETs are determined
by a variety of factors including the gate drive current, gate–
source capacitance, and parasitic elements [9], [10]. In addi-
tion, it is often necessary to employ an external gate resistance
to dampen any oscillations caused by the external and internal
parasitic inductances. This further limits the current that can
be delivered to the device by traditional totem pole drivers,
as the combined RLC time constant slows the gate capacitance
charging time [11].
The proposed gate drive approach utilizes magnetic energy
storage in the form of a current-carrying inductor to drive
current into the MOSFET gate. The topology in Fig. 3,
although similar to previously developed resonant gate drivers
such as those presented in [12]–[14], operates in a much
more aggressive regime. While these resonant drivers can
achieve high gate drive efficiency through energy recovery,
they are also limited in rise time capability due to the
use of clamping diodes or other methods that prevent gate
drive voltages from exceeding 20 V. The proposed approach
removes the limitation on the excessive gate drive voltage for
short transients, and instead utilizes a continuously variable
inductor current to rapidly charge the MOSFET gate capac-
itance. The high-voltage (>120 V) inductive kick, generated
by interruption of this inductor current, helps to overcome the
large gate impedance presented by the parasitic inductance,
and is capable of driving high current (>20 A) into the gate to
achieve very fast turn-on time (<20 ns) and high dI /dt (up to
25 kA/µs−1 ) in the main pulse discharge circuit. The effect of
additional parasitic inductance introduced into the gate-driving
circuit due to device packaging is also considered.
II. 1.7- K V S I C MOSFET DUT
The Cree CPM2-1700-0045B is a silicon carbide (SiC)
power MOSFET designed for a maximum drain to source
voltage, VDS , of 1700 V, a maximum continuous drain current,
I D , of 72 A, and a typical gate threshold voltage, Vgs(th) ,
of 2.4 V. The pulsed rating of the device extends this maxi-
mum drain current up to 160 A, with the pulsewidth limited
COLLIER et al.: FAST SiC SWITCHING LIMITS FOR PULSED POWER APPLICATIONS
Fig. 1. Cree CPM2-1700-0045B SiC MOSFET bare die pictured with a
TO-247 packaged version. The underside of the SiC die is metallized and
serves as the drain connection.
by the maximum junction temperature. The typical ON-state
drain–source resistance, RDS(on) , is given as 45 m with a
gate–source voltage, Vgs , of 20 V [15]. With a rated rise
time of ∼20 ns, this commercially available device is an
attractive option for use in modern solid-state pulsed power
generators. The TO-247 packaged version is pictured in Fig. 1
alongside the bare SiC die. The results from both variations
are presented in a later section to investigate the impact of
parasitic components introduced by external packaging.
III. H IGH -S PEED G ATE D RIVING
In pulsed applications, the transient switching behavior of a
MOSFET is primarily determined by the gate driving circuitry.
Although a continuous driving current is not necessary, a high
current pulse into the gate of the MOSFET is required for
fast switching. Often, an external gate resistor is added to
reduce ringing between the gate capacitance and the parasitic
inductance within the driving circuit. For a typical −5/20 V
driver, this results in a gate voltage charge/discharge waveform
that is dependent upon an RC time constant for turn-on/turn-
off that is less than ideal for high-speed switching.
A. Traditional Gate Driving Approach
The CRD-001 Isolated Gate Driver, from Cree, is a commer-
cially available gate driving test platform designed specifically
for high-voltage SiC MOSFETs. With an isolation voltage
rating of 5.2 kV, this driver is well suited for use with the
device under test (DUT). The CRD-001 is equipped with
an IXYS IXD609 ultrafast MOSFET driver IC capable of
sourcing/sinking a peak current of 9 A.
This IC utilizes a totem-pole driver to charge/discharge the
MOSFET gate capacitance to 20/−5 V. In order to maintain
the operation below the 9 A peak current rating, a minimum
external resistance of ∼2.2  is necessary. Neglecting the
effects of parasitic inductance within the gate–source charging
5307
Fig. 2. Equivalent circuit of a packaged MOSFET with parasitic elements
shown.
loop, this RC (Q q ≈ 188 nC at 20 V, C g ≈ 9.4 nF) time
constant corresponds to a 0–15 V rise time of ∼29 ns and
a fall time to below the gate threshold voltage of ∼42 ns.
The inclusion of additional parasitic elements, primarily the
gate–source inductance, as well as nonideal rise time of the
totem pole itself will result in further degradation of the driver
performance. For pulsed applications where a rise time less
than 20 ns is desired, an alternative approach with increased
gate drive current is necessary.
B. MOSFET Switching Parasitics
Fig. 2 depicts the equivalent circuit for a packaged
MOSFET including the parasitic elements. In low-frequency
or slow-rise time applications, the parasitic gate, source, and
drain inductances (L g , L s , L d ) can be neglected, as these
values are typically very small (less than 10 nH for the DUT).
However, for high-current, fast-rise time pulses (i.e., high
dI /dt), these parasitic elements can have detrimental effects on
the transient switching characteristics. In addition, the Miller
capacitance, Cgd , can negatively affect the MOSFET switching
performance, as charge is pulled out of the gate during turn-on
and injected into the gate during turn-off from high dV /dt.
IV. I NDUCTIVE G ATE D RIVER
In order to counteract the negative effects on the switching
performance introduced by the parasitic elements in Fig. 2,
the proposed gate driving scheme utilizes a current-carrying
inductor to deliver a high-current pulse into the gate of the SiC
MOSFET. This method has a number of advantages over the
traditional gate drive approaches including the high-current
amplitude (>20 A), as determined by the inductor charging
time. In addition, the generation of a high-voltage inductive
kickback, a consequence of Faraday’s Law of Induction, helps
to overcome the gate charging impedance presented by the
parasitic gate and source inductances.
Fig. 3 shows a simplified circuit schematic of the induc-
tive gate driver. This circuit operates in the three modes as
5308
Fig. 3. Simplified inductive gate driver circuit schematic with the drive
current Idr indicated. (a) Inductor charge. (b) Inductor discharge (turn on).
(c) Gate discharge (turn off).
depicted: (a) inductor charge, (b) inductor discharge (turn
on), and (c) gate discharge (turn off). During (a), Q1 and
Q2 are switched on. This allows the current through inductance
L dr to ramp-up at a rate approximately equal to V0 /L dr .
In order to trigger the SiC MOSFET (Q3), Q2 is switched
off. As the current through L dr is interrupted, the inductive
kickback produces a high-voltage pulse that drives current
into the gate of the MOSFET, rapidly charging the gate–
source capacitance, Cgs . After the specified pulselength has
been reached, Q2 is again switched on to discharge the gate
capacitance and turn-off the SiC MOSFET.
Although the peak voltage generated by this kickback can
greatly exceed the rated Vgs of the SiC MOSFET, a majority
of this voltage is dropped across the gate resistance and
inductance [5]. However, care must be taken to ensure that the
total charge delivered to the MOSFET gate does not result in a
gate voltage exceeding the rated Vgs(max) after the initial pulse.
As a first-order approximation, the energy relation specified
in (1) can be used to approximate the necessary inductor
current, I L dr , for a given drive inductance, L dr
1 1
L dr I L2dr = C g Vgs(max)
2
. (1)
2 2
For Vgs(max) = 20 V, C g = 9.4 nF, and L dr = 22 nH,
the required inductor current is approximately 14 A. In reality,
IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 47, NO. 12, DECEMBER 2019
Fig. 4. Inductive gate driver PCB with primary components indicated
including a 22-nH, air-core drive inductor and a 120-nF capacitor bank.
a higher current than estimated by this equation is required
due to resistive losses in external gate and internal bond
resistances. In addition, the total gate capacitance, C g , is a
function of the drain–source voltage, Vds . During testing, this
inductor current was adjusted empirically to ensure that the
gate voltage did not exceed the rated Vgs(max) after the initial
inductive kick.
A. Inductive Gate Driver Printed Circuit Board (PCB)
The inductive gate driver test PCB, pictured in Fig. 4,
includes two TI UCC5320 3-kV isolated gate drivers. These
drivers, which correspond to GD1 and GD2 in Fig. 3, are
controlled via two outputs of a BNC Model 525 Pulse Delay
Generator. These control signals determine the inductor charg-
ing time as well as the output pulsewidth.
The HV discharge circuit consists of 12 × 10 nF, 2-kV
rated ceramic capacitors, 3 × 10  HVR carbon composite
resistors in parallel, and the SiC MOSFET. The discharge loop
was designed with low inductance in order to minimize its
effect on the current rise time. Neglecting the stray inductance
introduced by the MOSFET packaging, the loop inductance is
estimated to be less than 20 nH. Further reduction of the load
inductance could be achieved through the use of multiple SiC
MOSFETs switched in parallel.
B. Diagnostics
In order to facilitate current measurements without intro-
ducing additional parasitic inductance into the discharge cir-
cuit, a variety of low-profile, differential Rogowski coils
were developed [16]. The probes were calibrated alongside
a Pearson current monitor with 0.01 V/A−1 sensitivity, with
a typical calibration curve shown in Fig. 5. As the probes
are not self-integrating, the measured signal is numerically
integrated to obtain the desired current waveform. These
Rogowski probes are used to measure both the load current and
the inductor current during testing and exhibit slightly faster
COLLIER et al.: FAST SiC SWITCHING LIMITS FOR PULSED POWER APPLICATIONS 5309

Fig. 5. Calibration of a custom, low-profile Rogowski coil with 0.01 VA−1

Pearson current monitor.

rise time characteristics when compared with the commercial

Pearson monitor (τ < 5 ns).
Due to the low-profile design of the Rogowski coil, the addi-
tion of external shielding to minimize interference is imprac-
tical, and the calibrated gauge factor can become inaccurate
depending upon the orientation of the coil within the pulse
discharge circuit. In order to ensure signal integrity and accu-
racy, on-board adjustment to the initial calibration is performed
through measurement of the load voltage. This measurement
is converted to a current using the known load resistance, and
the Rogowski measurement is scaled to minimize the RMSE
between the two waveforms.
V. R ESULTS
In order to evaluate the inductive gate drive circuit for
viability in fast rise time (<20 ns), high-current applications,
the driver circuit in Fig. 4 was tested over a range of charging
voltages with the bare SiC die bonded to the board as well as
with the TO-247-packaged MOSFET. The typical measured
charge/discharge waveforms are shown in Fig. 6 for a charge
voltage of 400 V for the bare SiC die. Note that the difference
between the drain–source voltage before and after the pulse is
a direct consequence of the discharge of the capacitor bank
during the pulse. Additional characterization of the mount
multilayer ceramic capacitor (MLCC) bank related to short
pulse applications is detailed in Appendix A.
With a peak inductor current (I L dr ) of ∼13.5 A, a load
current rise time of 15 ns is achieved for a peak current of
∼110 A. While the measured gate voltage exceeds 60 V during
the driving pulse, it settles to ∼20 V after the initial ringing.
As the peak inductor current is continuously variable by
adjusting the charging time, it can be chosen to ensure that the
gate is driven appropriately across a range of operating condi-
tions. For example, the falling dV /dt at the drain during turn-
on pulls charge out of the gate through the Miller capacitance,
Cgd . Thus, for higher charging voltages, the inductor current
must be increased to account for the current lost through
this parasitic capacitance in order to achieve the best possible
rise time. The optimized rise time achieved for both the die
and packaged MOSFETs are shown in Fig. 8 for a range of
capacitor bank charging voltages discharged into a 3.3  load.
Fig. 6. Measured inductive gate drive waveforms using the SiC MOSFET
die with Vds = 400 V and R L = 3.3 . Note the internal gate–source voltage
(black trace) is corrected for parasitic inductances in the MOSFET leads. The
fast inductive spike in the externally measured gate voltage (light gray trace)
is a consequence of the high dI /dt during fast gate charging.
A. Gate Voltage
While traditional gate driving techniques make an effort
to limit the externally applied gate voltage to 20 V or less,
the inductive technique used here generates much higher
voltages, often in excess of 140 V during the initial device
turn-on. Due to the use of higher than normal gate voltage,
one may expect degradation of the gate oxide layer and device
failure after a small number of pulses. A previous work [4]–[6]
using a high gate voltage to improve the MOSFET switching
time has presented the argument that a fast-transient high
voltage on the gate is mostly dropped across the external
gate–source resistance and inductance, with only a small por-
tion of this voltage appearing across the internal gate–source
capacitance.
Due to the high dI /dt experienced during fast switching of
the SiC device, significant voltage appears across the gate–
source parasitic elements. Thus, the measured gate voltage
does not correspond to only the MOSFET gate–source voltage,
Vgs , but instead represents the series combination of voltage
5310 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 47, NO. 12, DECEMBER 2019

drops in the following equation:

d Ig d Is
Vmeas = Ig Rg + L g + Vgs + L s (2)
dt dt
where Ig is the gate current, Rg the internal gate resistance,
L g the gate lead inductance, L s the source lead inductance,
and Is the source current. Although the internal gate–source
voltage cannot be directly measured, an approximation of this
voltage can be obtained by rearranging (2) to obtain Vgs .
Using estimates from the SPICE simulation (see Appendix B)
for the SiC die parasitic elements, with L g = 4 nH and
L s = 3 nH, and the manufacturer-specified internal resistance,
Rg = 1.3 , the corrected gate voltage is calculated and
plotted (black trace) alongside the measured voltage (gray
trace) in Fig. 6.

B. Die MOSFET
In an effort to reduce the effect of parasitic elements on
the switching characteristics of the MOSFET, the bare SiC
die pictured in Fig. 1 was bonded directly to the test board
in Fig. 4. The circuit was tested at varying charging voltages,
with output waveforms shown in Fig. 7. In addition, the peak
inductor current was adjusted empirically during each test
to ensure a complete turn-on. While a charge voltage of
400 V required ∼13 A of the drive inductor current, this value
increased to ∼23 A for a charge voltage of 1.6 kV.

C. Packaged MOSFET
Significant degradation of pulse characteristics was
observed using the packaged version of the MOSFET, primar-
ily in the rise and fall times of the output pulse, see Fig. 7.
In addition, significantly higher inductor current was necessary
to ensure fast turn-on with the packaged version over the
bare die primarily due to the additional inductance within the
bonded package connections. At the lower end, a peak drive
inductor current of ∼26 A was required to fully turn-on the
MOSFET at a charge voltage of 400 V. At 1.6 kV, this peak
inductor current was increased to ∼67 A.
D. Rise time
The rise time of the SiC MOSFET is highly dependent upon
the magnitude of the gate drive current. For the inductive gate
drive topology presented in this article, the gate drive current
depends on a number of factors including the inductor charge
current, parasitic resistance, and inductance in the gate, and
the voltage generated by the inductive kick during turn-off of
Q2 in Fig. 3(b). During the initial turn-on of Q3, this inductive
kickback voltage, which is seen entirely by Q2, can easily peak
over 100 V, exceeding the rated breakdown voltage of Q2.
Although this overvoltage is only present for tens of
nanoseconds, some drive current can be lost through the switch
Q2 as it begins to break down. This current loss has a negative
effect on the rise time of Q3, as less current is available to
charge the gate capacitance. Due to the large parasitic gate
inductance present in the TO-247 package, a significantly
larger drive current, and thus a significantly larger inductive
kickback voltage, was required to fully turn-on the MOSFET;
Fig. 7. Measured load current (R L = 3.3 ) at varying charging voltages.
The additional source inductance introduced by the TO-247 packaging results
in significantly extended turn-off times.
however, due to the loss of drive current through Q2, the rise
time of the packaged variant was limited.
E. Turn-Off Characteristics
The use of an inductive gate driver to rapidly charge the gate
capacitance results in very fast rise time for pulsed currents
greatly exceeding the rated current of the device. However,
as per Fig. 7, the fall time degraded as on-state current
through the device is increased, most notably for the packaged
MOSFET. The turn-off circuit, depicted in Fig. 3, is a simple
RC discharge with R = Rg = 2  and C = C g ≈ 9.4 nF, and
a resulting time constant of ∼18 ns. Additional charge injected
into the gate through the Miller capacitance (Cgd ) due to the
rapidly rising drain voltage further degrades the turn-off time.
The extended fall time seen from the TO-247 packaged
MOSFET is primarily attributed to the parasitic source induc-
tance (L s in Fig. 2). Due to the high dI /dt experienced during
turn-off, this inductance produces a negative voltage spike at
the internal source connection, effectively biasing the gate at
a lower voltage with respect to the ground. This change in
potential difference slows down the effective discharge time of
the MOSFET gate capacitance, resulting in significant exten-
sion of the turn-off time. The reduction in source inductance
COLLIER et al.: FAST SiC SWITCHING LIMITS FOR PULSED POWER APPLICATIONS
Fig. 8. Optimized load current rise time for the SiC die and packaged
MOSFET with R L = 3.3  and Vds = 0.4 − 1.6 kV.
achieved through the use of the bare SiC die minimizes this
effect.
Further improvement to the fall-time could be achieved
through simple negative biasing for the turn-off portion of the
circuit. Additionally, it should be possible to utilize a similar
inductive drive circuit with current flowing in the opposite
direction to rapidly pull charge from the gate. Such a bipolar
inductive gate drive approach may be sufficient to overcome
the obstacles to fast pulsed switching of traditionally packaged
SiC MOSFETs at high current levels.
F. Reliability Testing
In order to further alleviate concerns on reliability, repetitive
testing of the inductive drive circuit was performed. To elim-
inate any thermal effects, the pulse discharge circuit was
operated at a frequency of 2 Hz, with 10 000 shots conducted
at each tested charge voltage (400, 800, 1200, and 1600 V).
In summary, a total of 40 000 shots was conducted on the
device without failure and with no noticeable degradation in
the output pulse characteristics. Furthermore, simulation of the
inductive drive circuit using the manufacturer-provided SiC
MOSFET model (see Appendix B) reveals that although the
external gate voltage can reach as high as 140 V, the internal
gate–source voltage never exceeds 20 V due to the voltage
drop across the gate parasitics, see Fig. 12. Thus, assuming
the inductive drive current has been tuned appropriately,
the high-voltage kick on the MOSFET gate should not result
in premature oxide degradation or device failure. In fact,
the only-device failure that has occurred with the proposed
gate driving scheme was the result of an improperly tuned
inductive drive current that caused a high-settling voltage on
the gate, in excess of ∼30 V, after the initial inductive kick.
VI. C ONCLUSION
The proposed gate driving scheme utilizes the tendency of a
current-carrying inductor to produce a high-voltage kick upon
5311
current interruption in order to rapidly charge the MOSFET
gate–source capacitance, even in the presence of large parasitic
elements. A high turn-on dI /dt, up to 25 kA/µs−1 , was
achieved with an inductor current of 23 A and a peak inductive
kickback voltage of 140 V without noticeable damage to
the SiC device. The peak inductor current, and thus the
peak kickback voltage, is continuously variable by adjusting
the length of time the inductor is allowed to charge before
triggering. This level of modularity allows for use with a
variety of solid-state switches with a wide array of parasitic
inductances and gate capacitances.
Additionally, the effect of parasitic elements, primarily the
gate and source inductances, introduced to the MOSFET
through traditional packaging (TO-247) was investigated.
Although high turn-on dI /dt, up to 13 kA/µs−1 , was achieved,
it required significantly higher inductor current (∼60 A)
to overcome the additional impedance presented by the
gate–source parasitics. The parasitic source inductance also
had a significant lengthening effect on the turn-off time of
the packaged switch. This limitation could likely be overcome
by using a similar reverse inductive drive circuit to rapidly
discharge the gate capacitance.
A PPENDIX A
C APACITANCE D ERATING
In order to minimize the effects of parasitic elements in the
pulse discharge circuit, a parallel combination of 12, 10 nF
surface MLCCs were used for the capacitor bank. These
capacitors tend to have much lower inductance when compared
with leaded capacitors due to the absence of leads and low-
profile mounting capability; however, due to the ferroelectric
X7R dielectric, these capacitors demonstrate a significant loss
in total capacitance with an increase in the applied voltage.
Thus, while the capacitor bank is nominally 120 nF when
charged to 100 V, the actual capacitance at a charge voltage
of 1.6 kV is reduced to only ∼80 nF, see Fig. 9.
In addition to the capacitance derating with voltage, the out-
put energy efficiency of MLCCs, along with many other types
of capacitors, is strongly dependent upon pulsewidth. For very
short pulses (sub μs), a significant portion of the stored energy
in the capacitor is lost electrically, with the energy being
dissipated elsewhere such as in the production of heat and
shock waves in the material. [17] This energy loss results in
further derating of the effective capacitance with decreasing
pulsewidth.
Measurement of the capacitor current and voltage during a
fast discharge pulse allows for determination of this effective
capacitance using (4) and (5)
Vc = Vc (t0 ) − Vc (t1 ) (3)
 t1
Q c = Ic dt (4)
t0
Q c
Ceff = (5)
Vc
where Vc is the capacitor voltage, Ic is the capacitor current,
and t0 and t1 are the start and end times chosen to encapsulate
the entire pulse. Q c then represents the total electrical charge
drained from the capacitor during the pulse and Vc represents
5312 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 47, NO. 12, DECEMBER 2019

Fig. 9. Effective capacitance of nominal 120-nF capacitor bank using X7R

dielectric MLCCs for slow (10 μs) and fast (100 nS) discharge.

Fig. 11. Simulated and experimentally measured load current waveforms at

a specified charging voltage.

Fig. 10. LTSPICE schematic of the inductive gate driver circuit with a SiC
MOSFET model and parasitic elements.

the change in the capacitor voltage over this same interval. The
measured effective capacitance, Ceff , for a 100 ns pulse (red
triangles) is shown alongside the “slow” discharge curve (blue
triangles) in Fig. 9 for the nominally 120-nF capacitor bank
used in this article. The significant reduction in the effective
bank capacitance with increasing charge voltage is responsible
for the increasingly negative current slope during discharge
seen in Fig. 7.
A PPENDIX B
SPICE S IMULATION
In order to evaluate the proposed gate driving scheme
Fig. 12. Simulated gate voltage for the SiC die with Vds = 400 V, see
for use in large-scale, solid-state, pulsed power genera- Fig. 6. External gate voltage includes the voltage drop across the parasitic
tors, it is desirable to obtain a circuit model that can gate–source elements. Internal gate voltage corresponds to the voltage across
accurately describe the system behavior. The circuit shown the internal gate–source capacitance.
in Fig. 10 is used to simulate the experimental tests using
a SPICE MOSFET model provided by the manufacturer, to 3.3  to model the experimental load. Finally, the parasitic
Cree. Parasitic elements introduced by the circuit layout and inductance of the discharge loop, L par , was adjusted to 15 nH
MOSFET packaging are accounted for using lumped elements to obtain the best match between simulated and experimental
(Rd, Ld, Rs, Ls, Rg, Lg). The capacitor bank capacitance, data.
Cbank , is adjusted depending upon the charge voltage per For the bare SiC die model, the MOSFET parasitics, L g ,
derating curve in Fig. 9 for a 100 ns pulse. L d , and L s , are determined through iterative adjustment and
The manufacturer-provided model includes values for the comparison between the simulated and measured waveforms.
parasitic elements introduced by the TO-247 packaging, with The values used in the bare die simulation, with output current
Rg = 1.3 , L g = 15 nH, L d = 6 nH, and L s = 9 nH. shown in Fig. 11, are L g = 5 nH, L d = 7 nH, and L s = 3 nH.
The drain and source resistances, Rd and Rs , are assumed to The significant reduction in gate inductance with the bare
be very small (<10 m), as these values are entirely omitted SiC die resulted in much lower peak voltage on the gate
from the manufacturer model. The load resistance, R L , is set and improved the turn-on time. In addition, the reduced
COLLIER et al.: FAST SiC SWITCHING LIMITS FOR PULSED POWER APPLICATIONS
source inductance allows for much faster fall time when
compared with the packaged switch. These effects can be
seen clearly in both the measured and simulated waveforms
in Fig. 11.
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5313
Landon Collier (M’15) received the B.S. degree
in computer engineering and the M.S. and Ph.D.
degrees in electrical engineering from Texas Tech
University, Lubbock, TX, USA, in 2015, 2016, and
2019, respectively.
He is currently a Senior Research Associate with
the Center for Pulsed Power and Power Electronics,
Texas Tech University. His current research inter-
ests include high-power solid-state switching, mag-
netic field diffusion phenomena, and pulsed power
systems.
Taiga Kajiwara (S’14) received the M.S. and Ph.D.
degrees in electrical engineering from Kumamoto
University, Kumamoto, Japan, in 2015 and 2018,
respectively.
He is currently a Pulsed Power Engineer with
the Kewpie Corporation, Tokyo, Japan. His current
research interest includes pulsed power technology
and its applications in microbial inactivation.
James Dickens (S’89–M’96–SM’04) received the
Ph.D. degree in electrical engineering from Texas
Tech University, Lubbock, TX, USA, in 1995.
He is currently the Co-Director of the Center
for Pulsed Power and Power Electronics, Texas
Tech University. His current research interests
include compact pulsed power, nonlinear transmis-
sion line (NLTL) oscillator arrays, SiC and GaN
photoconductive switching, and explosively driven
pulsed power generation.
John Mankowski (SM’14) is currently a Professor
of electrical and computer engineering with Texas
Tech University, Lubbock, TX, USA, where he is
also a member of the Center for Pulsed Power
and Power Electronics (P3E). He has authored or
coauthored more than 200 journal and conference
proceedings articles. His current research interests
include high power microwave generation [including
Vircators, nonlinear transmission lines (NLTLs), and
impulse radiating antennas (IRAs)], compact pulsed
power, and high-power switching.
Mr. Mankowski was a Co-Guest Editor of the IEEE T RANSACTIONS ON
P LASMA S CIENCE for the 2004 and 2008 Special Issues on Pulsed Power
and Science Technology.
Andreas Neuber (M’97–SM’03–F’12) received the
Diploma degree in physics and the Ph.D. degree in
mechanical engineering from Technische Universität
Darmstadt, Darmstadt, Germany, in 1990 and 1996,
respectively.
He is currently a Distinguished Professor of
electrical and computer engineering with Texas
Tech University, Lubbock, TX, USA. He has
authored more than 150 refereed journal articles.
His current research interests include high power
RF, ionospheric heating, surface flashover physics,
photoconductive switching, and diverse aspects of pulsed power.