Abstract— Crosstalk in a phase-leg configuration significantly limits the high

switching speed performance of silicon carbide (SiC) MOSFET due to their lower
threshold voltage and higher allowable negative gate voltage as compared with the
traditional silicon (Si). To fulfill the potential fast switching speed quality of SiC
MOSFET, an assist gate driver (AGD) circuit for crosstalk suppression based on the
negative-biased turn-off voltage was proposed, which contains an auxiliary capacitor
and two passive transistors without additional control signals. First, a recommended
gate driver by several SiC device manufacturers was introduced to analyze the
mechanism of crosstalk. Then, the operating principle of the proposed AGD circuit
was elaborated, and the parameter design criteria of the main elements were given.
Finally, a simulation using LTspice and an experiment based on Wolfspeed 1200-V SiC
MOSFET tests were used to verify the effectiveness of the proposed gate driver.
Simulation and experimental results show that the AGD circuit has a superior
characteristic of crosstalk suppression under varying operating conditions. Thus, the
proposed circuit could meet the fastidious requirement of fast-speed SiC MOSFET
under high dc voltage condition with less complexity.
摘要:与传统硅(Si)相比，碳化硅(SiC) MOSFET 具有较低的阈值电压和较高的允许
负栅电压，相腿结构中的串扰严重限制了其高开关速度性能。为了实现 SiC
MOSFET 潜在的快速开关速度特性，提出了一种基于负偏关断电压的辅助栅极
驱动(AGD)电路，该电路包含一个辅助电容和两个无源晶体管，不需要额外的控
制信号。首先，介绍了几种碳化硅器件制造商推荐的栅极驱动器，分析了串扰
产生的机理。阐述了该 AGD 电路的工作原理，给出了主要元件的参数设计准则。
最后，利用 LTspice 进行了仿真，并在 Wolfspeed 1200 v SiC MOSFET 上进行了实
验，验证了所提栅极驱动器的有效性。仿真和实验结果表明，该 AGD 电路在不
同工况下具有较好的串扰抑制特性。因此，该电路能够以较低的复杂度满足高
直流电压条件下高速 SiC MOSFET 的苛刻要求。
SILICON carbide (SiC) material is widely used in the new-generation power electronic
devices due to its wider bandgap, higher electron mobility, and better thermal
conductivity when compared to the traditional silicon (Si) [1]–[3]. All of these
superior characteristics are beneficial to high switching speed, high voltage, and high
operational temperature, which make SiC MOSFET as a promising device and
excellent alternative of Si IGBT for high-power converters [4]. In particular, in high-
power density applications (e.g., aerospace, electric vehicle, and rail transit), SiC
MOSFET is an ideal choice due to its fast speed characteristic [5], [6].
与传统的硅(Si)[1] -[3]相比，碳化硅(SiC)材料具有更宽的禁带宽度、更高的电子
迁移率和更好的导热性能，在新一代电力电子器件中得到了广泛的应用。所有
这些优越的特性有利于高开关速度、高电压和高工作温度，这使 SiC MOSFET 成
为一个有前途的器件和 Si IGBT 的高功率转换器[4]的优秀替代品。特别是，在高
功率密度应用(例如，航空航天，电动汽车和轨道交通)，SiC MOSFET 是一个理
想的选择，因为它的快速特性[5]，[6]。
However, in a power converter using the phase-leg configuration, high switching
speed corresponding to high dv/dt amplifies the negative impact of parasitic
components, which may interfere the operating behavior of its complementary
devices [7]–[9]. The positive gate voltage spikes are induced during a complementary
switch turn-on transient, resulting in extra switching losses and even shoot-through
failure. The process of the turn-off period evokes negative voltage spikes, which
could overstress power devices. Furthermore, the SiC MOSFET owns a low threshold
voltage and merely tolerates a high negative gate–source voltage. For example, the
commercial product Wolfspeed’s C2M0080120D has a typical threshold voltage of
only +2.2 V and its negative gate– source voltage cannot exceed −10 V in room
temperature. These tolerable voltages might be cut down as the temperature
increases [10]. Consequently, the crosstalk between two switches in a SiC MOSFET
phase-leg configuration could be serious on account of the small negative gate–
source voltage and low threshold voltage, resulting in a fastidious gate driver design
requirement.
然而，在采用相位腿结构的功率变换器中，高 dv/dt 对应的高开关速度放大了
寄生元件的负面影响，可能会干扰其互补器件[7]-[9]的工作行为。在互补开关接
通瞬态过程中，正栅电压尖峰会引起额外的开关损耗，甚至击穿故障。在关断
过程中会产生负电压峰值，这可能会对功率器件造成过度的压力。此外，SiC
MOSFET 具有较低的阈值电压，仅能耐受较高的负栅源电压。例如，商业产品
Wolfspeed 的 C2M0080120D 的典型阈值电压仅为+2.2 V，其负栅源电压在室温下
不能超过−10 V。这些耐受电压可随着温度的升高而降低。因此，在 SiC
MOSFET 相腿结构中，由于负门源电压小、阈值电压低，两个开关之间的串扰
可能会很严重，导致栅极驱动器设计要求苛刻。
Previously reported works have proposed several gate assist circuits to mitigate the
crosstalk of SiC MOSFET [11]–[24]. These methods can be divided into two
categories. The first method is the gate impendence regulation (GIR). The concept of
GIR is to provide a small gate impendence during the switching transient of its
complementary devices. The simplest realization method is to add a large capacitor
between the gate and source terminals of SiC MOSFET [13], which is effective to
suppress the spurious gate voltage pulse and mitigate crosstalk. However, switching
speed will be decreased because of the additional capacitor, resulting in an increase
of switching losses. Yin et al. [14] provided a method to accelerate the turn-off
transient by means of adding a small resistor connected in series with a diode and
then in parallel with an external gate resistor. Such method merely focuses on turn-
off transient, and the turn-off ringing could increasingly become severe as the gate
resistor decreases [25], [26]. A gate assist circuit was revealed in [18], which could
switch SiC quickly, but switching speed was likely to decrease due to a capacitor
connected to gate–source directly. Furthermore, this circuit only focuses on the
positive spikes suppression, and the auxiliary capacitor without discharge path was
inapplicable to longtime operation. In [19] and [21], additional controllable switches
connected in series with the capacitor were applied between the gate–source
terminals and control gate impendence by activating the auxiliary controllable
switches. However, the auxiliary actively controlled transistors and the
implementation of relatively complicated logic signal synthesis unavoidably increase
the circuit complexity.
先前报道的工作提出了几种栅辅助电路来减轻 SiC MOSFET[11] -[24]的串扰。这
些方法可以分为两类。第一种方法是门限调节(GIR)。GIR 的概念是在互补器件
的开关瞬态过程中提供一个小的门阻抗。最简单的实现方法是在 SiC
MOSFET[13]的栅极和源极之间增加一个大电容，可以有效地抑制栅极电压杂散
脉冲和抑制串扰。但是，由于增加了电容，会降低开关速度，导致开关损耗增
大。Yin 等人的[14]提供了一种方法，通过增加一个小电阻与二极管串联，然后
与一个外部栅电阻并联，加速关断瞬态。这种方法只关注于关断瞬态，随着门
电阻[25]，[26]的降低，关断振铃现象会越来越严重。在[18]中发现了一种栅极
辅助电路，该电路可以快速切换 SiC，但由于直接连接到栅极源的电容可能会降
低切换速度。此外，该电路只针对正尖峰抑制，没有放电路径的辅助电容不适
合长时间工作。在[19]和[21]中，通过激活辅助可控开关，在门源端和控制门阻
抗之间附加与电容串联的可控开关。然而，辅助有源控制晶体管和实现相对复
杂的逻辑信号合成不可避免地增加了电路的复杂性。
High dv/dt, which may induce spurious gate voltage, was determined by the Miller
plateau stage during the switching transient. Hence, a crosstalk mitigation strategy
[16], [17] was proposed to increase the Miller plateau duration by deactivating the
additional transistors to enlarge gate resistance. As a result, dv/dt was decreased and
crosstalk was mitigated. However, due to the relatively large internal gate resistance
of SiC MOSFET, the measured gate voltage was less than that across the internal
gate–source terminals.
高 dv/dt 会引起杂散栅电压，这是由开关瞬态过程中的米勒平台阶段决定的。
因此，提出了一种抑制串扰的策略[16]，[17]，通过激活额外的晶体管来增大栅
电阻来增加 Miller 平台持续时间。结果，dv/dt 降低，串扰减轻。然而，由于
SiC MOSFET 相对较大的内部栅电阻，测量的栅电压小于内部栅源端
Moreover, gate voltage control (GVC) is another strategy in the suppression of the
crosstalk. The means of GVC is to provide a negative turn-off gate voltage to suppress
the positive gate voltage spikes of the switch when its complementary switch is
deactivated [23], [24]. This method can suppress the impact of crosstalk during the
turn-off transient. However, the high negative gate voltage spikes induced during the
turn-off transient, resulting in the overstress of power switches, should be taken into
consideration. In [22], a resistor capacitor diode (RCD) level shifter circuit without
using any extra voltage source was provided, which could generate a negative gate
voltage to lower down the positive gate voltage spikes and ensure the negative gate
voltage spikes within the limits of the maximum allowable negative gate voltage.
However, the higher allowable negative voltage of SiC MOSFET brings the difficulty
for determining the negative gate voltage which was generated by RCD level shifter.
According to the aforementioned literature, Table I concludes the prior works with
their performance, as well as the performance of the proposed circuit. It can be
found that prior works only focused on a portion of switching speed, voltage spikes
suppression, or complexity.
此外，栅电压控制(GVC)是另一种抑制串扰的策略。GVC 的方法是当互补开关
[23]，[24]失能时，提供一个负的关断栅电压来抑制开关的正栅电压尖峰。该方
法可以有效地抑制关断过程中串扰的影响。但是，在关断过程中产生的高负栅
电压尖峰会导致电源开关的过应力，这是需要考虑的问题。在[22]中，提供了
一种不使用任何额外电压源的电阻电容二极管(RCD)移电平电路，该电路可以产
生一个负栅电压来降低正栅电压尖峰，并保证负栅电压尖峰在最大允许的负栅
电压范围内。然而，由于 SiC MOSFET 的允许负电压较高，使得 RCD 电平移频器
产生的负栅电压难以确定。根据上述文献，表一总结了之前的工作和它们的性
能，以及所提出的电路的性能。可以发现，以往的研究只关注开关速度、电压
峰值抑制或复杂性的一部分。
This study proposes an assist gate driver (AGD) circuit for positive and negative
spurious gate voltage mitigations, which adopt a capacitor and two transistors in
series without additional trigger signals, providing a simple, less switching time delay
solution to fully utilize the high-speed switching performance of SiC devices. Section
II analyzes the mechanism of crosstalk, reviews two conventional drive circuits, and
introduces the operating principle of the proposed AGD. Section III analyzes the
transient process of the proposed AGD and accordingly gives the primary parameter
design criteria. Section IV focuses on validation through LTspice simulations and
experimental demonstrations. Finally, Section V gives the conclusion.
本研究提出了一种辅助栅极驱动(AGD)电路，该电路采用一个电容和两个晶体管
串联，没有额外的触发信号，提供了一个简单、更少的开关时延解决方案，以
充分利用 SiC 器件的高速开关性能。第二部分分析了串扰的机理，回顾了两种
传统的驱动电路，并介绍了所提出的 AGD 的工作原理。第三节分析了所提 AGD
的暂态过程，并给出了主要的参数设计准则。第四节着重于通过 LTspice 模拟和
实验演示进行验证。最后，第五部分给出结论。
II. MECHANISM OF CROSSTALK AND THE PROPOSED AGD CIRCUIT
Fig. 1 depicts a double-pulse test (DPT) schematic for evaluating the crosstalk
suppression capability of the gate driver, in which a recommended gate driver (RGD)
by several SiC device manufacturers [23], [24] was used for analyzing the mechanism
of the crosstalk. As shown in Fig. 1(a), when the upper switch was turned on, the
drain–source voltage of QL suddenly rose, resulting in a current flowing through the
Miller capacitor CgdL and charging up the parasitic capacitor CgsL between gate–
source nodes. Thus, a positive spurious gate voltage of QL was generated and
induced to a fault activation. Similarly, when QH was turned off, CgsL generated a
negative spurious voltage, which could overstress the SiC MOSFET, as shown in Fig.
1(b).

A conventional gate driver (CGD) was proposed in [14] to suppress crosstalk, as

shown in Fig. 2. The charging current of the Miller capacitor was shunted by C during
the turn-on transient, and then, the positive voltage spike was attenuated. Moreover,
the negative voltage spike was suppressed by C during the turn-off transient due to
the decrease of the gate loop impendence. However, this method increases the
equivalent capacitance of gate–source terminals and prolongs the charging and
discharging time of the capacitor, which extends the switching time and increases
switching losses. 在[14]中提出了一种传统的门驱动(CGD)来抑制串扰，如图 2 所
示。在开启瞬态过程中，通过 C 分流米勒电容的充电电流，使正电压尖峰得到
衰减。此外，在关断过程中，由于门环阻抗的降低，C 抑制了负电压峰值。但
该方法增加了栅源端等效电容，延长了电容器的充放电时间，延长了开关时间，
增加了开关损耗。
To suppress the crosstalk in a phase-leg configuration without sacrificing the fast
switching speed of SiC MOSFET, the proposed AGD, as shown in Fig. 3, employed a
transistor connected in series with capacitors to bypass the Miller current during the
switching period. Consequently, the gate drive loop impedance was reduced, and the
high-speed performance of SiC MOSFET was preserved. Moreover, no extra control
signals were required for the additional transistors as a result of their low threshold
voltage (approximately 0.7 V), which was generated by the circuit itself when the
voltage spikes occurred.

为了在不牺牲 SiC MOSFET 快速开关速度的情况下抑制相位腿结构中的串扰，如

图 3 所示，所提出的 AGD 采用了一个串联的晶体管和电容，在开关期间绕过米
勒电流。因此，栅驱动环路阻抗降低，保持了 SiC MOSFET 的高速性能。此外，
额外的晶体管不需要额外的控制信号，因为它们的低阈值电压(约 0.7 V)，这是
由电路本身产生的电压尖峰。
In detail, capacitor Ca eliminated the effect of commonsource stray inductor Ls and
clamped the voltage of Ca to keep almost constant, which is equal to V2. Thus, the
capacitance of Ca should be relatively large enough. Capacitor C connected in series
with an n-p-n transistor VT 2 and a p-n-p transistor VT , offering another small
impedance loop for suppressing crosstalk during the switching transient. Transistors
VT 2 and VT 1 were turned on automatically when the Miller current flows through
Rg, where Rg is an external gate drive resistor used for suppressing the parasitic
ringing caused by stray inductor Lg. Diode D is used to prevent emitter–base of the
transistor from breakdown. The transient analysis of this proposed circuit will be
discussed at length below. 电容器 Ca 消除了共源杂散电感 Ls 的影响，箝位 Ca 的
电压几乎保持恒定，等于 V2。因此，Ca 的电容应该足够大。电容器 C 与一个 n-
p-n 晶体管 VT 2 和一个 p-n-p 晶体管 VT 串联，提供了另一个小阻抗回路，用于
在开关瞬态过程中抑制串扰。当米勒电流流过 Rg 时，晶体管 VT 2 和 VT 1 自动
接通，Rg 是一个外部栅驱动电阻，用于抑制杂散电感 Lg 引起的寄生响铃。二极
管 D 用于防止晶体管的发射极基板击穿。下面将详细讨论这个电路的暂态分析。
III. TRANSIENT ANALYSIS OF THE PROPOSED AGD
The switching sequence of a bridge-leg configuration is drawn in Fig. 4, where control
signals SH and SL are the gate drive signals of QH and QL, respectively, and the
synchronous voltages vdsL and vgsL of lower switch QL are also displayed (assuming
lower switch as the interfered device).

图 4 绘制了桥腿结构的开关顺序，其中控制信号 SH 和 SL 分别为 QH 和 QL 的门
驱动信号，并显示了下开关 QL 的同步电压 vdsL 和 vgsL(假设下开关为受干扰设
备)。

A. Operating Principle of AGD Circuit

The operation transient of a bridge circuit during one control period can be divided
into eight phases. The operating principle of the proposed AGD circuit is depicted in
Figs. 5 and 6. The mechanism of the crosstalk suppression is described as follows. It is
noted that the capacitor Ca and common-source stray inductor Ls are omitted in the
following analysis for simplification since the effect of common-source stray inductor
Ls is eliminated by capacitor Ca.
桥式电路在一个控制周期内的运行暂态可分为八相。所提议的 AGD 电路的工作
原理如图 5 和图 6 所示。串扰抑制的机理描述如下。值得注意的是，由于电容
Ca 消除了共源杂散电感 Ls 的影响，为了简化，在下面的分析中省略了电容 Ca
和共源杂散电感 Ls。

Phase 1 [t0–t1] (On the State of QH ): In this duration, the auxiliary circuit branch was
out of work. Upper switch QH was fully activated, whereas the lower switch QL was
fully deactivated. The current IL of the load inductor L flowed through the upper SiC
MOSFET channel, and the crosstalk did not occur.
Phase 1 [t0-t1] (On the State of QH):在此时间内，辅助电路支路处于无工作状态。
上层交换机 QH 完全激活，而下层交换机 QL 完全去激活。负载电感 L 的电流 IL
流过上 SiC MOSFET 通道，没有发生串扰。

Phase 2 [t1–t2] (Turn-Off Transient of QH ): V2H reversely charged CgsH when QH

was turned off, and the effect of auxiliary circuit on the turn-off performance of QH
can be neglected due to the unidirectional conduction of diode D1H , and the output
parasitic capacitance of VT _2H is usually an order of magnitude smaller than the
input capacitance of the main power devices. Meanwhile, the current flows through
the QH channel were converted to the body diode Dbody_L of the lower switch and
the drain–source voltagevdsH of QH suddenly rose. Furthermore, the drain–source
voltage vdsL of QL fell down rapidly. As a result, the Miller capacitor CgdL began to
discharge, and the discharged current induced a positive voltage on the external gate
resistor RgL, which turned on VT _2L. Consequently, CL was connected to the gate–
source terminal of QL, and the impedance of the gate drive loop was significantly
reduced as the capacitance of CL was relatively large. Thus, the spurious negative
spikes of vgsL can be eliminated. At the end of t2, the turn-off transient of the upper
switch was completed.
第二阶段[t1-t2] (QH 的关闭瞬态):V2H 相对地指控 CgsH QH 关闭时,和这么多的岔
路上的辅助电路性能的影响可以忽略由于二极管的单向导电 D1H,和输出寄生电
容的 VT _2H 通常是一个数量级小于输入电容的主要电力设备。同时，流过 QH
通道的电流被转换为下开关的体二极管 Dbody_L, QH 的漏源极电压 evdsh 突然升
高。此外，QL 漏源极电压 vdsL 迅速下降。因此，米勒电容 CgdL 开始放电，放
电电流在外接栅电阻 RgL 上感应一个正电压，使 VT _2L 接通。因此，CL 被连接
到 QL 的栅源端，由于 CL 的电容较大，栅驱动回路的阻抗显著降低。因此，可
以消除 vgsL 的伪负尖峰。t2 结束时，完成上开关的关断瞬态。

Phase 3 [t2–t3] (End of Commutation): QH and QL were in fully OFF-state, and

current IL flows through body diode Dbody_L. Circuit stayed on the dead state in this
period. At the end of t3, QL was turned on.
Phase 3 [t2-t3] (End of Commutation): QH 和 QL 处于完全 off 状态，电流 IL 流过体
二极管 Dbody_L。这段时间电路处于死状态。在 t3 结束时，QL 被打开。

Phase 4 [t3–t4] (Turn-On Transient of QL): Similarly, the diode D2L is a unidirectional
device, and the output capacitance of transistor VT _1L is an order of magnitude
smaller than the input capacitance of the main power device. Thus, the influence of
the auxiliary circuit on the turn-on performance can be neglected. Load current IL
partly flowed through the channel of QL as it began to be activated. At the end of t4,
QL was fully activated.
Phase 4 [t3-t4] (on - on Transient of QL):同样，二极管 D2L 是一个单向器件，晶体
管 VT _1L 的输出电容比主功率器件的输入电容小一个数量级。因此，辅助电路
对通断性能的影响可以忽略。当 QL 开始被激活时，负载电流 IL 部分流过 QL 通
道。在 t4 结束时，QL 完全激活。

Phase 5 [t4–t5] (Fully Turn-On Transient of QL): No current was generated in the gate
drive loop as QL was fully activated, and the path of IL consisted of the channel and
body diode Dbody_L. At the end of t5, QL began to turn off.
Phase 5 [t4-t5] (full Turn-On Transient of QL):当 QL 完全激活时，门驱动环路中没
有电流产生，IL 的路径由通道和体二极管 Dbody_L 组成。在 t5 结束时，QL 开始
关闭。

Phase 6 [t5–t6] (Turn-Off Transient of QL): V2L charged CgsL reversely, QL was turned
off, and the load current was converted form channel to body diode Dbody_L.
Similarly, as analyzed in phase 2, the influence of the auxiliary circuit on the turn-off
performance of QL can be neglected.
Phase 6 [t5-t6] (Turn-Off Transient of QL):反向 V2L 充电的 CgsL, QL 被关闭，负载电
流从通道转换到体二极管 Dbody_L。同样，如第二阶段所分析的，辅助电路对
QL 关断性能的影响可以忽略。

Phase 7 [t6–t7] (Fully Turn-Off Transient of QL): Similar to phase 3, the body diode of
QL is the only path for the load current. At the end of t7, QH began to turn on.
Phase 7 [t6-t7] (full Turn-Off Transient of QL):与 Phase 3 类似，QL 的体二极管是负
载电流的唯一路径。在 t7 结束时，QH 开始启动。

Phase 8 [t7–t8] (Turn-On Transient of QH ): V1H charged up CgsH to turn on QH .

Likewise, the effect of the auxiliary circuit on the turn-on performance of QH can be
neglected as analyzed in phase 4. The current path was converted from Dbody_L to
the channel of QH as QH was turned on. As a result, vdsH suddenly fell down and
vdsL rose rapidly. Miller capacitor CgdL was charged up, and the charging current
induced a positive voltage to turn on VT _1L. CL directly connected with the gate–
source terminals of the lower switch, and the gate loop impedance of QL was largely
decreased. Therefore, the positive voltage spikes of QL can be minimized, and the
crosstalk during the turn-on transient of QH was suppressed. At the end of t8, the
operation model returned to phase 1.
V1H 给 CgsH 充电，启动 QH。同样，辅助电路对 QH 的接通性能的影响可以忽略，
在第四阶段进行了分析。当 QH 被打开时，当前路径从 Dbody_L 转换到 QH 的通
道。结果 vdsH 突然下降，vdsL 迅速上升。对米勒电容 CgdL 充上电，充电电流
感应正电压，使 VT _1L 接通。CL 直接与下开关的门源端相连，QL 的门环阻抗大
大降低。因此，可以使 QL 的正电压尖峰最小，并抑制 QH 的接通瞬态过程中的
串扰。在 t8 结束时，操作模型返回到阶段 1。
According to the operating principle of the proposed AGD, the positive and negative
spurious voltages can be minimized without slowing down the switching speed. The
proposed AGD circuit is suitable for SiC MOSFET with fast switching capability.
根据所提出的 AGD 的工作原理，可以在不减慢开关速度的情况下最小化正、负
杂散电压。该 AGD 电路适用于具有快速开关能力的 SiC MOSFET 器件。

B. Primary Parameter Design of AGD Circuit

According to the aforementioned operating principle of the proposed AGD circuit,
the critical passive components of the proposed circuit are external gate resistor Rg
and auxiliary capacitor C, as shown in Fig. 3. These components significantly affect
switching performance. In this section, the design criteria of Rg and C are analyzed
based on Wolfspeed’s C2M0080120D SiC MOSFET, and the basic parameters of this
devices can be obtained from [10], as shown in Table II. The lower switch is the
device under interference, and the effect of stray inductor Lg can be omitted. Fig. 7
shows the simplified equivalent circuit without the auxiliary circuit in the gate loop
during QH switching transient. The voltage source vin = at can be seen as the
influence of QH on QL when QH is switching, where a(a_ON or a_OFF) is a constant
slew rate of the drain–source of QL during the switching transient. Thus, the voltage
drop on external gate resistor RgL should be large enough to turn on auxiliary
transistors VT _1L or VT _2L during the switching transient of QH . Consequently, the
auxiliary circuit can be connected into the gate loop to suppress crosstalk.
By applying Kirchhoff’s current law (KCL) at node G, the current equation can be
obtained as follows: 根据上述所述的 AGD 电路工作原理，所述电路的关键无源元
件为外部栅电阻 Rg 和辅助电容 C，如图 3 所示。这些元件对开关性能有很大的
影响。本节基于 Wolfspeed 公司的 C2M0080120D SiC MOSFET 对 Rg 和 C 的设计
准则进行分析，从[10]得到该器件的基本参数，如表 II 所示。较低的开关是受干
扰的器件，可以忽略杂散电感 Lg 的影响。图 7 为 QH 开关瞬态过程中门环中没
有辅助电路的简化等效电路。电压源 vin = at 可以看作是 QH 在切换时对 QL 的影
响，其中 a(a_ON 或 a_OFF)是在切换瞬态过程中 QL 漏源的恒定变换速率。因此，
在 QH 的开关瞬态过程中，外部栅极电阻 RgL 上的压降应该足够大，使辅助晶体
管 VT _1L 或 VT _2L 接通。因此，辅助电路可以连接到门环以抑制串扰。
应用结点 G 处的基尔霍夫电流定律(KCL)，可得电流方程为:

The gate–source capacitor voltage of QL can be expressed as follows by solving the

differential equation (1):

The voltage (delta)V1 of RgL induced by the Miller current during switching transient
should provide the turn-on voltage of the transistor (0.7 V) and the series-connected
Schottky diode (0.4 V), which can be expressed as
在开关瞬态过程中，Miller 电流所感应的 RgL 电压(delta)V1 应该提供晶体管(0.7
V)和串联肖特基二极管(0.4 V)的接通电压，可以表示为

where V2L = −5 V and the selection range of RgL is shown in Fig. 8, where different
slew rates of the drain–source voltage during turn-on and turn-off transients are
considered; it can be seen that these two curves are very similar to each other.
Therefore, the slew rate a has little influence on (delta)V1.
其中，V2L =−5 V, RgL 的选择范围如图 8 所示，其中考虑了在通断过程中漏源极
电压的不同转换率;可以看出，这两条曲线非常相似。因此，回转速率 a 对(δ)V1
的影响很小。

Since the determination of RgL is related to Cgd, and the value of Cgd has voltage
dependence according to the datasheet [10], the effect of voltage dependence of
Cgd is discussed as follows. Cgd varies little with voltage after a rapid decrease of Cgd
as VDS increasing from 0 to 20 V, and Cgd remains almost constant (∼6.5 pF) when
VDS is larger than 400 V. Considering practical application, the 1200-V SiC MOSFET is
usually used in high voltage system (several hundred volts). Thus, the situation of
VDS bigger than 100 V is discussed, e.g., Cgd = 15 pF (VDS = 100 V), Cgd = 9.5 pF (VDS
= 300 V), and Cgd = 6.5 pF (VDS > 400 V). As shown in Fig. 9, the minimum value of
RgL decreases as Cgd increasing, so the determination of RgL by fixing Cgd = 6.5 pF
could meet the demand of (delta)V1.

由于 RgL 的确定与 Cgd 有关，而根据数据表[10]，Cgd 的值与电压有关，因此讨

论 Cgd 对电压的影响。当 VDS 从 0 增加到 20 V 时，gcd 迅速下降，但随着电压
的变化，gcd 变化不大，当 VDS 大于 400 V 时，gcd 几乎保持不变(~ 6.5 pF)。考
虑到实际应用，1200 v SiC MOSFET 通常用于高压系统(几百伏特)。因此,VDS 公
司的情况比 100 V 是讨论,例如,Cgd = 15 pF (VDS = 100 V),这份报告= 9.5 pF (VDS =
300 V)和 Cgd = 6.5 pF (VDS > 400 V)。如图 9 所示,RgL 减少的最小值作为全球发展
中心增加,所以决心的 RgL 修复 Cgd = 6.5 pF 可以满足需求(δ)V1。
As shown in Fig. 8, the external gate resistance of RgL should be greater than 3.1
ohm. By considering the switching speed and gate ringing, a compromising value of
larger than 5 ohm was selected in this study. Once an appropriate RgL was
determined, the proposed AGD circuit was put into work. The ON-state resistance of
transistor and diode was only dozens of milliohms; hence, the effects of the
transistor and diode can be neglected, and the simplified equivalent circuit of gate
loop with auxiliary circuit during the switching transient is depicted in Fig. 10. The
application of KCL at node G and KVL into the gate loop yields the following equation:
如图 8 所示，RgL 的外栅电阻应大于 3.1 欧姆。考虑到开关速度和门环的影响，
本研究选取了大于 5 欧姆的折衷值。一旦确定了合适的 RgL，提出的 AGD 电路
就投入工作。晶体管和二极管的通态电阻只有几十毫欧姆;因此，可以忽略晶体
管和二极管的影响，在开关瞬态过程中，带有辅助电路的简化门环等效电路如
图 10 所示。将节点 G 处的 KCL 和节点 KVL 处的 KCL 应用到门环中，得到如下方
程:

A second-order differential equation can be obtained by simplifying (5) and (6)

The voltage changing value (delta)V2 on auxiliary capacitor CL caused by the high
switching speed of QH can be expressed as

Apparently, the positive spurious gate voltage spike of QL cannot exceed the
threshold voltage Vth, and the negative spurious gate voltage should be larger than
the minimum allowed gate voltage VMIN(neg) to suppress the crosstalk

Solving inequality group (9) yields (delta)V2 < 3.9 V, and Fig. 11 shows the selection
range of CL. Similarly, the slew rate a has little influence on (delta)V2.
Similarly, the determination of CL is related to Cgd, and Fig. 12 shows the effect of
voltage dependence of Cgd on the CL design; the minimum value of CL increases with
Cgd, but (delta)V2 almost remains unchanged when CL > 10 nF, especially when CL is
bigger than 100 nF, (delta)V2 varies gradually and owns a wide margin. Thus, a 100-
nF capacitor was selected to mitigate the crosstalk. In addition, a 0-ohm resistor was
applied to restrain the high-frequency interference on the base of the transistor.
同样，CL 的确定也与 Cgd 有关，图 12 显示了 Cgd 的电压依赖性对 CL 设计的影
响;CL 的最小值随 cvd 的增大而增大，但当 CL > 10 nF 时(delta)V2 基本不变，特
别是当 CL > 100 nF 时，(delta)V2 变化平缓，有较大的余量。因此，一个 100 nf
的电容器被选择来减轻串扰。此外，在晶体管的基础上，采用零欧姆电阻抑制
高频干扰。

IV. SIMULATION AND EXPERIMENTAL VERIFICATIONS

A DPT using the C2M0080120D SiC MOSFET was used for the simulation and
experimental verification of the proposed AGD. The selected auxiliary n-p-n and p-n-
p transistors are ZXTN25100BFHTA and ZXTP25100BFHTA, respectively, which
possess low saturation voltage and high breakdown voltage. The Schottky diode
applies DIODES 1N5819HW-7-F with low conduction voltage and fast recovery
performance. Table III lists the main passive element parameters of different gate
drivers. Table IV lists the characteristics of auxiliary transistor and diode.
采用 C2M0080120D SiC MOSFET 的 DPT 器件对所提出的 AGD 进行了仿真和实验
验证。所选的辅助 n-p-n 和 p-n-p 晶体管分别为 ZXTN25100BFHTA 和
ZXTP25100BFHTA，饱和电压低，击穿电压高。肖特基二极管采用二极管
1N5819HW-7-F 具有低导通电压和快速恢复性能。表三列出了不同栅极驱动器的
主要无源元件参数。表四列出了辅助晶体管和二极管的特性。

A. Simulation Verification
Almost all manufacturers of the main semiconductor devices offer LTSpice models of
products. Thus, the LTspice is beneficial for simulation analysis. Therefore, LTspice
was assumed to simulate different gate drivers and the proposed one in this paper.
To be consistent with the experimental conditions, the positive and negative gate
voltages were set to +18 and −5 V, respectively. The dc-link voltage of the main circuit
was set to 400 V with an inductor load of 400 μH. A parasitic inductance of 5 nH and
external gate resistance of 10 ohm were included in all gate drivers in the
simulations. Fig. 13 shows the comparison simulation waveforms of the turn-on and
turn-off transients of upper switch QH using different gate drivers. The dc-link voltage
was set to 400 V, and the testing method was DPT. Table V lists the switching
performance parameters of different gate drivers. In a word, the positive spike gate
voltage of the RGD gate driver presented in Fig. 1 reached 2.3 V, which risks
increasing switching losses, and the negative spike gate voltage has exceeded the
minimum allowable value. Although the CGD gate driver presented in Fig. 2 can
significantly suppress the crosstalk, the switching delay time increases as the
capacitor is connected into the gate loop, resulting in the increase of switching
losses. Compared with CGD, the proposed AGD can suppress crosstalk by reducing
the turn-on delay time by 77.6%, and the turn-off delay time can be reduced by
65.2%, resulting in the reduction of the total switching losses by 32.2%. The
simulation results briefly reveal that the proposed AGD has superior performance on
crosstalk suppression. To give an insight into the characteristic of the proposed AGD,
a DPT platform based on C2M0080120D SiC MOSFET was constructed for the
experimental verification.
几乎所有的主要半导体器件制造商都提供 LTSpice 型号的产品。因此，LTspice 有
利于仿真分析。因此，假设 LTspice 模拟了不同的栅极驱动器和本文提出的栅极
驱动器。为了与实验条件一致，将正、负栅极电压分别设置为+18 和−5 V。在
电感负载为 400 μH 的情况下，设置主电路的直流电压为 400 V。所有栅极驱动
器的寄生电感均为 5 nH，外部栅极电阻均为 10。图 13 为不同栅极驱动下上层
开关 QH 的通断瞬态比较仿真波形。直流链路电压设置为 400v，测试方法为
DPT。表 V 列出了不同栅极驱动器的开关性能参数。综上所述，图 1 中 RGD 栅
极驱动器的正尖峰栅电压达到 2.3 V，有增加开关损耗的风险，而负尖峰栅电压
已超过最小允许值。虽然图 2 所示的 CGD 门电路驱动器可以明显抑制串扰，但
由于电容接入门电路，导致开关延时时间增加，导致开关损耗增大。与 CGD 相
比，所提出的 AGD 能够抑制串扰，其导通延迟时间降低了 77.6%，关断延迟时
间降低了 65.2%，总开关损耗降低了 32.2%。仿真结果表明，所提出的 AGD 具有
较好的串扰抑制性能。为了深入了解所提出的 AGD 的特点，构建了基于
C2M0080120D SiC MOSFET 的 DPT 平台进行实验验证。

B. Experimental Verification
The prototype circuit board of the proposed AGD is shown in Fig. 14, and the passive
elements parameters are listed in Table III. The schematic of the DPT is shown in Fig.
1, where Vdc refers to dc-link voltage and load is an air core inductor L that is used
for keeping a constant current during the communication duration. The
measurement system is specified in Table VI.
所提出的 AGD 原型电路板如图 14 所示，无源元件参数列于表三。DPT 的原理图
如图 1 所示，其中 Vdc 指的是直流链路的电压，负载是一个空芯电感 L，用于在
通信期间保持恒定的电流。测量系统见表六。

Fig. 15 displays the captured waveforms under different gate drivers with the
operating condition of 400 V/5 A with 10- gate resistance, and the switching
characteristic parameters of experimental results are shown in Table VII. When the
recommended driver was used, the crosstalk was very obvious. The positive voltage
spike was 3.8 V during the turn-on transient, which exceeded the threshold voltage.
The minimum negative spike reached up to −12.4 V, easily leading to a degradation of
the gate oxide and decreasing the reliability of SiC MOSFET. As shown in Fig. 15(c)
and (d), the CGD can limit the positive and negative spikes to an allowable range.
However, the switching speed was sacrificed due to the additional capacitor between
gate-to-source nodes, resulting in large increases in switching losses. While applying
the proposed AGD, the experimental waveforms are shown in Fig. 15(e) and (f).
Moreover, the maximum voltage spike was −1.6 V during the turn-on transient of
QH , and the negative spike was only −7.9 V. Compared with the CGD, the spurious
voltage spikes of the proposed one are slightly smaller because the auxiliary
capacitance was big. Furthermore, when making a deep comparative analysis of the
captured waveforms in Fig. 15(a), (c), and (e) and Fig. 15(b), (d), and (f), the switching
performance of the proposed AGD was very similar to the RGD gate driver, and the
crosstalk suppression performance inherits the features of the CGD gate driver, which
indicates that the proposed AGD possesses the merits of RGD and CGD gate drivers.
图 15 显示了在 400v / 5a、10 门电阻工况下，不同门驱动下捕获的波形，实验
结果的开关特性参数如表 7 所示。当使用推荐的驱动程序时，串扰非常明显。
在开启瞬态过程中，正电压峰值为 3.8 V，超过了阈值电压。最小负尖峰达到
−12.4 V，很容易导致栅极氧化物的退化，降低了 SiC MOSFET 的可靠性。如图
15(c)和(d)所示，CGD 可以将正、负尖峰限制在允许的范围内。然而，由于门源
节点之间的附加电容，导致开关速度的牺牲，导致开关损耗的大幅增加。在应
用所提出的 AGD 时，实验波形如图 15(e)和(f)所示。QH 在接通过程中，最大电
压峰值为−1.6 V，而负峰值仅为−7.9 V。与 CGD 相比，由于辅助电容较大，其
杂散电压峰值略小。此外,当进行深入比较分析捕获的波形图 15 (a), (c), (e)和图
15 (b), (d)和(f),开关的性能提出的 AGD 非常类似于 RGD 门驱动器,和串扰抑制性
能继承 CGD 门驱动器的特点,这表明所提出的 AGD 具有 RGD 和 CGD 门驱动的优
点。
To fully evaluate the effectiveness of the AGD for crosstalk suppression, an
experimental comparison under different gate driver circuits was conducted
according to different gate resistances, dc-link voltages, and load currents.
为了充分评价 AGD 抑制串扰的有效性，根据不同的栅极电阻、直流链路电压和
负载电流，在不同的栅极驱动电路下进行了实验比较。
Fig. 16 presents the comparison test results dependent on the gate resistance
between the conventional and proposed gate drivers under 400-V dc-link voltage
with 5-A load current. The external gate resistance varied from 5 to 20 ohm. The
switching delay time increased with the increase of external gate resistance, leading
to an increase in power losses. However, the crosstalk phenomenon was suppressed
due to a low dv/dt. 图 16 给出了在 400 v 直流链路电压和 5 a 负载电流下，传统栅
极驱动器和提议栅极驱动器之间依赖于栅极电阻的对比测试结果。外部栅极电
阻从 5 欧姆到 20 欧姆不等。随着外栅电阻的增大，开关延时时间增大，导致功
率损耗增大。但由于 dv/dt 较低，串扰现象被抑制(上開關 vgs 電壓 正峰值由-1
便到-2 代表正串擾變小，-8.3 到-7.3 代表負串擾變小)。

Fig. 17 illustrates the comparison test results dependent on the dc-link voltage under
a load current of 5 A with 10-ohm gate resistance, where Vdc varied from 300 to 600
V. The crosstalk phenomenon was more significant when Vdc rose. The value of Vdc
had a slight influence on the switching delay time. Thus, the switching power losses
increase as dc-link voltage rises up. Fig. 18 shows the comparison test results
dependent on the load current, where Vdc is 400 V and external gate resistance is 10
ohm. When the load current varied from 3 to 10 A, switching losses increased and
the spurious spikes rose. Similarly, the switching delay time was slightly affected by
the value of the load current. In summary, the switching behavior is affected by the
operating condition for both gate drivers. The spurious voltage spikes decrease as
gate resistance increases and increase with system voltage and load current,
respectively. By contrast, the proposed AGD has a better capability for crosstalk
suppression under varying operating conditions. Moreover, the proposed circuit
combines the merits of the recommended and CGD circuits, and the simulation and
experimental results have approved this. 图 17 显示了负载电流为 5 a，栅电阻为
10 欧姆时，直流电压从 300 V 到 600 V 的对比测试结果。当 Vdc 上升时，串扰现
象更为明显。Vdc 值对开关延时时间影响较小。因此，开关功率损耗随着直流
电压的升高而增大。图 18 为负载电流的对比测试结果，其中 Vdc 为 400 V，外
栅电阻为 10 欧姆。当负载电流从 3 A 变化到 10 A 时，开关损耗增大，杂散尖峰
增大。同样，开关延时时间受负载电流大小的影响较小。综上所述，两种栅极
驱动器的开关行为都受操作条件的影响。杂散电压峰值分别随栅极电阻的增大
而减小，随系统电压和负载电流的增大而增大。相比之下，所提出的 AGD 在不
同的工作条件下具有更好的串扰抑制能力。此外，该电路结合了推荐电路和
CGD 电路的优点，仿真和实验结果验证了这一点。

V. CONCLUSION
A gate driver circuit using two auxiliary transistors, diodes, and a capacitor was
proposed in this study to suppress the positive and negative spikes of SiC MOSFET in
a bridgeleg configuration. The simulation and experimental results verify that the
proposed driver circuit can attenuate the positive gate voltage spikes and clamp the
negative spikes to a safety voltage range without slowing down the switching speed
or increasing switching losses. Moreover, this circuit possesses a simple control
strategy that does not include any additional control signals. Compared with the
CGD, the overall switching performance has been improved by means of the
proposed AGD: turn-on delay time decreased by up to 75% and 65% during the turn-
off transient at the tested operating condition and the switching energy losses
reduced by 35% under the experimental tested operating condition. Furthermore,
drain current has little influence on switching delay time in the proposed assist
circuit, and the reason for this phenomenon will be studied in the future work.
本研究提出了一种使用两个辅助晶体管、二极管和电容的栅极驱动电路，以抑
制桥腿结构 SiC MOSFET 的正、负尖峰。仿真和实验结果表明，该驱动电路在不
降低开关速度或增加开关损耗的情况下，可以将正栅电压峰值衰减，将负栅电
压峰值箝位到安全电压范围内。此外，该电路具有不包含任何额外控制信号的
简单控制策略。与 CGD 相比，AGD 的整体开关性能得到了改善:在测试工况下，
在关断瞬态过程中，AGD 的开关延迟时间分别降低了 75%和 65%，在测试工况
下，AGD 的开关能量损失降低了 35%。此外，漏极电流对所提出辅助电路中的
开关延时时间影响不大，产生这种现象的原因将在今后的工作中进行研究。