SiC MOSFET Gate Drive Design Considerations

Julius Rice, John Mookken

Cree Inc.
Durham, NC United States
Julius_Rice@Cree.com

Abstract - The purpose of this paper is to provide guidance means that SiC MOSFET drivers have less time to detect
on how to design gate driver circuits for Silicon Carbide (SiC) and interrupt a short circuit condition safely. This is an
MOSFETs. There are new commercially available SiC important factor when designing over current protection
MOSFETs available in discrete and module packages which schemes.
are much faster and more efficient than their traditional IGBT
counterparts. To take full advantage of these benefits we need Table 1. Comparison of critical parameters between similar rated SiC
to understand the requirements for a new breed of gate drivers MOSFET and Si IGBT.
that are tailored to meet the unique drive and protection
characteristics of SiC MOSFETs. Traditional IGBT based P/N IGW25N120H3 [1] C2M0080120D [2]
fault protection schemes such as desaturation (desat) detection Si IGBT SiC MOSFET
can be implemented with some modifications to protect SiC IC 100 (A) 25 24
MOSFETs. However, due to the higher switching speed of the VCE or VDS (VDC) 1200 1200
new SiC devices, it is worth another look at all the design and QG (nC) 115 62
implementation aspects of a good SiC MOSFET gate driver. EON @TJ max (uJ) 2600 230
25A/600V
EOFF @TJ max (uJ) 1700 175
I. Introduction 25A/600V
TR @ TJ max (nS) 35 20
Many designers in the power electronics industry are TF @ TJ max (nS) 50 23
already expert users of IGBTs in power converter designs. Ipulse, TP limited by 100 80
However, 1200V and 1700V SiC MOSFETs have become a TJ max. (A)
Tsc, short circuit 10 5
real alternative to using IGBTs in power applications. Due withstand time (uS)
to the availability of many new, faster switching and more @ typical VGE/VGS
efficient SiC MOSFETs, there exists a need to better
understand the differences between driving and protecting III. Design considerations
Si-IGBTs and SiC MOSFETs so that it is possible to
develop low cost and effective gate drivers with all the A. Gate voltage and current
features that are common in IGBT drivers. Si-IGBTs gates are typically driven from -8V in the
OFF state to +15V in the ON state. For SiC MOSFETs, the
II. Differences between the devices voltage varies slightly to +18 or +20V in the ON state and
-5V in the OFF state. Driving the SiC MOSFET more
Before we begin considering the SiC MOSFET gate aggressively at +20V minimizes switching losses and
drive, let’s consider the main differences between a similar improves the surge current rating for the SiC device, but it
rated SiC MOSFET and Si IGBT that are relevant. The puts a greater voltage stress on the gate which can affect the
parameters that are significant for a gate drive design have long term reliability of the device. Typically for SiC
been summarized in Table 1. MOSFETs, gate voltage upper limit varies from +22V to
SiC MOSFETs typically have significantly lower switching +25V and the lower limit from -5V to -10V. Some isolated
times and therefore lower switching losses, but they also power supply manufactures (Murata, Mornsun and Recom)
have lower total gate charge Qg. Furthermore, the total are manufacturing power supplies specifically tailored to
switching losses in Si-IGBTs tend to increase with junction SiC MOSFET requirements.
temperature while the opposite is true for SiC MOSFETs. The calculations for gate power and current
These characteristics mean that the SiC devices are well requirements are identical to the way it is determined for Si
suited for high switching frequency applications. IGBTs and power MOSFETs. The only difference to note is
Another critical parameter to consider is the short the smaller Qg and gate voltage transition times.
circuit withstand time and turn-off SOA for the two devices.
Both these values are lower for SiC MOSFETs. Examining B. Parasitics in the gate loop
the V-I curves partly explains (see section III) why the two
Parasitics in the gate driver circuit, especially
devices have different current surge capability. Another
inductance have a greater impact on the effectiveness of SiC
reason for the difference in surge current capability is the
gate drives due to the faster switching speeds. Ideally, the
fact that Si-IGBT devices are significantly physically larger
driver would be located very close to the MOSFET.
than SiC devices with similar ratings. This effectively

978-1-4799-9883-8/15/$31.00 ©2015 IEEE 24

Module users can no longer afford to place the gate driver
several inches away from the module and use a pair of
twisted cables to connect the output to the module.
A Kelvin source connection is recommended whenever
possible. The high level of drain current di/dt can couple
back into the gate drive through any common gate/source
inductance which can cause significant ringing in the gate
loop.
The MOSFET, like any majority carrier device, does
not exhibit a tail current when turning off. This is one of the
reasons MOSFETs can be turned off faster than IGBTs.
However, the tail current in an IGBT provides natural
snubbing during the switch transitions which works to
reduce ringing. The lack of this tail in the MOSFET causes
them to ring much more than a comparable IGBT. Pictured
below (see Fig. 1) is scope capture of a SiC MOSFET
device ringing during turn-off. The higher ringing
combined with the lower threshold voltage of a MOSFET is
cause for concern.
If multiple MOSFETs are to be paralleled, then the
value of RG selected will impact how well the devices share.
In general, decreasing RG improves dynamic sharing and
reduces differences in switching losses; however, this
tradeoff would need to be examined closely [4].
D. Short Circuit Protection (desat)
In IGBT based topologies such as motor drives, the
switch could be turned on during an abnormal event such as
shorted motor windings. When this happens, the gate drive
circuit should be able to detect the fault condition and safely
shut the device off before a failure occurs. Traditionally,
IGBTs have used a desaturation (desat) circuit to monitor
VCE and detect when the device transitions from the
saturation region to the active region. This threshold occurs
typically around 7V in Si IGBTs.
A MOSFET is different from an IGBT in the fact that
there is no clearly defined transition between the linear and
saturation region. However, with careful design, an
overcurrent (desat) circuit can still be implemented with the
SiC MOSFET gate driver. Fig. 3 and 4 show VI curves for
an IGBT and SiC MOSFET.

Fig. 1 Turn off waveform [3]

Reducing the stray inductance with proper layout is the

best means to minimize the ringing. With the gate driver,
the gate and source paths should ideally both be copper
planes on opposing layers to minimize the stray inductance.
Fig. 3 VI characteristic for IGBT [5]
C. Effects of RG
One of most critical design choices that the gate drive
designer has to make is what value of RG to select. Going
with the minimum value for RG will minimize the switching
losses; however, dv/dt will increase and EMI as well. The
designer will have to study the tradeoffs between switching
losses and EMI to optimize the design. One example of this
type of tradeoff can be seen in a motor drive study which
was done to compare the maximum dv/dt on the drive’s
output terminals versus RG for comparable Si IGBTs and
SiC MOSFET modules. Fig. 2 shows the tradeoff. The Fig. 4 VI characteristic for SiC MOSFET [2]
designer would have to weigh the benefits of smaller RG and
fewer losses against the risk of potentially more EMI
challenges and possibly the cost of a filter on the motor One method to implement the over current protection
drive’s output. circuit in SiC MOSFETs would be to follow the same
method i.e. VDS monitoring. However, since the forward
RG versus dv/dt
20,000
pulse current rating and short circuit withstand times are
15,000
lower when compared to Si-IGBTs, it is necessary to reduce
SiC MOSFET
Max dv/dt

the blanking times and reference threshold voltage. The

10,000
monitored VDS voltage would be compared to a reference
Si IGBT
5,000 voltage so that under normal circuit operation, the reference
0
voltage would not be exceeded. In the event of a fault or
15 20 25 30 35
Gate Resistance Ω
40 45 short circuit, the increased drain current would cause VDS to
increase until it exceeded the value of the reference voltage.
Fig. 2 dv/dt versus RG

25
 Fig. 5 shows a SiC MOSFET gate driver designed to 940A. The current is interrupted roughly 550ns after this.
drive Cree’s 300A all SiC MOSFET half bridge module, This is primarily due to circuit and propagation delays.
CAS300M12BM2 (Fig. 6).
VCC_REG_LOWER
+5V

-VEE_LOWER
U11
RST_B 4.3V
16 1 R54 D10
GND1 VEE2 1k HV D11
TP18 R52 R53 15 2 C35
10K 10K VCC1 DESAT 100n
0805 0805 0805
C36 14 3 D12
/RST GND2 DRN/COLECTR_LOWER
FLT_B 100n C38
13 4 C37 10V DNP
FLT_B /FLT NC 100n 0805
12 5
RDY _B RDY VCC2 SOURCE_LOW ER
11 6
IN- OUT
PWM_B
10 7
TP20 IN+ CLAMP
R59 9 8
10k GND_1 VEE_2

PWM_B 0603 1ED020I12-F2

-VEE_LOWER
TP23

GND

Fig. 5 SiC MOSFET Overcurrent Protection Circuit

Fig. 8 Short Circuit

E. Two-level gate drive

Anytime a short circuit or fault is interrupted, there is
going to be a voltage overshoot due to the high amount of
di/dt combined with the parasitic inductances that are in the
power circuit path. This problem is exacerbated by SiC
MOSFETs due to their extreme switching speeds. One
Fig. 6 Cree CAS300M12BM2 means of mitigating this is by going to a two level gate
driver during turn-off or soft turn-off, commonly used in
This circuit topology allows the user to select what IGBT drivers.
value of VDS the circuit will trip at. The example gate driver The circuit would be designed to operate similar to an
chip (1ED020I12-F2), has an internal comparator that turns over current protection (or desat) circuit and monitor VDS.
the gate off when the voltage exceeds 9V. A 4.3V zener Once VDS exceeds the level it normally runs at during
diode has been added in series between the MOSFET’s normal operation, the gate would be lowered to some
drain and the gate driver’s comparator input. This will intermediate voltage. This intermediate voltage would
cause the gate driver chip to interrupt the current with 4.7V lower the current flowing through the device due to its
(9V–4.3V) across the MOSFET. transconductance. After remaining at this intermediate
voltage for some period of time, the gate would then lower
To test the circuit, the gate driver circuit was connected to its turn-off voltage to completely turn the MOSFET off.
to a CAS300M12BM2 half bridge module as shown in Fig. Lowering VGS to the intermediate voltage and then to the off
7. A short circuit was placed across the top switch voltage reduces the current at a slower rate than normal
simulating a shoot-through condition. turn-off. This reduces the di/dt and potential voltage
overshoot. Reducing the gate voltage also lengthens the
3 period of time a MOSFET can endure a short circuit before
Cree half bridge gate
failure due to the lower current and hence lower total
G
Driver energy.
S
1
VDC
1K Vz In some applications the po ower devices used may be
required to survive a period of time under short circuit
Pulsing
Circuit
Cree half bridge gate
Driver
G conditions before turning off or be able to ‘ride through’ the
S
2 event. One means to handle these types of applications
CT would be to utilize a two-level gate turn-off.
Fig. 7 Half Bridge Short Circuit Test
Lowering the gate drive voltage when an overcurrent is
detected will reduce the current through the MOSFET via its
The waveform capture shown in Fig. 8 shows the transconductance (Fig. 9) and increase the short circuit
current building ramping up to a peak of 1800A before the withstand time.
gate driver shuts the MOSFET off. Due to the 4.3V zener in
the circuit, the voltage comparator on the gate driver chip
only requires 4.7V across the MOSFET (VDS) to trip. The
module here was tested at 25C (RDSON = 5mΩ @25C) so the
drain current at 25C resulting in a VDS of 4.7V would be

26

Fig. 9 MOSFET Transconductance [2]
To illustrate how lowering VGS will increase a SiC
MOSFET’s short circuit duration, a tester was setup (Fig.
10). Cree’s CMF10120D, 160mΩ 1200V MOSFET was
connected to a capacitor bank. The MOSFET was turned on
and the current was measured through the device. To
confirm that the circuit and instrumentation were setup
correctly, the MOSFET was pulsed for 5us (within part’s
SOA) and the waveforms recorded (Fig. 11). The current
peaked at 130A and the duration was 5us as expected.
Fig. 10 MOSFET Short Circuit Test
Fig. 11 CMF10120D VGS=20V Short Circuit (5us)
Next, the MOSFET was pulsed for 40us with VGS =
20V (Fig. 12). This is beyond the part’s capability and the
purpose of this measurement is to see how long the part
survives the short circuit before failure. Once again the
current peaked at 130A. The part failed 7us into the event.
Fig. 12 CMF10120D VGS=20V Short Circuit (7us)
27
To show how lowering the gate voltage would increase
the MOSFET’s short circuit survival time, the gate voltage
was set to 15V (Fig. 13). Once again, the MOSFET was
pulsed for 40us which is long enough to ensure the part’s
failure.
Fig. 13 CMF10120D VGS=15V Short Circuit (13us)
This time, the MOSFET survived for 13us before
failing. Lowering the gate voltage from +20V to +15V
nearly doubled (86%) the short circuit withstand time of the
device. For ride through capability it may be possible to
design a gate driver that can transition to an intermediate
voltage switching and return to full or normal level of
switching after a high current event passes.
IV. Conclusion
MOSFETs being majority carrier devices inherently
ring more due to the fact that there is no tail current which
provides a significant amount of damping in IGBT circuits
and gate drives. However, if good layout practice is
utilized, and parasitics especially inductances are carefully
minimized, the ringing can be minimized and kept to an
acceptable level. Fault protections such as desaturation
(desat) detection circuits can be implemented with SiC
MOSFET gate drivers. For specialized applications where
detecting a fault and immediately shutting down the gates is
not an acceptable response, a two-level turn-off can be
utilized to reduce the current through the MOSFET which
allows it to withstand the fault for a longer period of time.
Through these practices, a SiC MOSFET along with a
properly designed gate driver can replace IGBTs in many
applications that have typically been exclusively served by
Si IGBTs in the past.
REFERENCES
[1] Infineon, IGW25N120H3 datasheet, Rev 2.1, Feb. 2014
[2] Cree Inc., C2M0080120D datasheet, Rev. B
[3] R. J. Callanan, “Application Considerations for Silicon
Carbide MOSFETs”, Cree Application Note CPWR-AN08
Rev-
[4] G. Wang, J. Mookken, M. Schupbach, “Dynamic and static
behavior of packaged silicon carbide MOSFETs in
paralleled applications”, Applied Power Electronics
Conference and Exposition (APEC), 2014 Twenty-Ninth
Annual IEEE , vol. 1478 – 1483, March 2014.
[5] ST Microelectronics, STGW15M120DF3
STGWA15M120DF3 datasheet, Oct. 2014