High PSRR Voltage Reference circuit with Dual-Output for low power

applications
Md Istiyak , Vinay B K , Pushpa mala S

Dept. of Electronics and Communication Engineering , CMR Institute of Technology , Bangalore, India
Phone:+919164255723 e-mail: mdistiyak1397@gmail.com.
Dept. of Electronics and Communication Engineering , CMR Institute of Technology , Bangalore, India
Phone: +918951544436, e-mail- vinay.bk@cmrit.ac.in.
Dept. of Electronics and Communication Engineering , Dayananda Sagar University, Bangalore, India
Phone: e-mail: pushpasiddaraju@gmail.com.

ABSTRACT
The Paper proposes a novel a dual – output voltage reference circuits with multiple (Two) output reference voltage of 281 mV (Vref1)
and 320.5 mV (V ref2) is implemented. A crucial part of the proposed module is design of front-end analog integrated circuits to
provide stable reference voltages and currents with accurate values. In order to incorporate these circuits on the chip Bandgap
reference circuits are most widely used. This design finds its vast application in analog to-digital conversion in which the reference
input voltage is compared several reference voltages levels in order to find out corresponding digital value. The importance of the
proposed work lies on theoretical understanding of the circuit operation and its performance limitations along with designing of a
bandgap reference (BGR) circuit.

Keywords - low-Temperature coefficient; low-line sensitivity; high-power supply rejection ratio; dual-output voltage reference;

1. INTRODUCTION
Bandgap reference circuit produces stable a voltage that is Some of the circuits were able to provide two reference output
constant resilient to PVT variations, input DC power supply voltages, with the requirement of more than one startup-up
variations and rejects power supply noise with a better noise circuit and a current reference circuits. But this complicated the
margin. Bandgap circuit has a nominally zero temperature structure leading to area utilization and high power consumption
coefficient (Zero TC) since has constant voltage across and hence it also doesn’t satisfy the criteria for low power
temperature variation. The voltage and bias current from the application
Bandgap reference circuit is fed to another circuit block such
as, current mirror or differential pair, as a reference orIn some circuits, MOSFET was used in sub-threshold conduction
biasing voltage to power up it. mode. This region is useful for system operating at low
Maintaining the Integrity of the Specifications, the challenge voltages of around 1V. This increases the transconductance
with miniature medical wearable devices is low power, high of MOSFET and provides for high gain. Although it satisfies
the criteria for low power, these limit the PSRR which is not
performance, noise immunity i.e ability to reject noise so
good. Finally, it is observed that, we need circuits with
that an high PSRR can be achieved. When MOSFETs were qualities of low power consumption, small size, low
introduced, PMOS and NMOS were the technology building temperature coefficient and high PSRR.
blocks for devices. The question later arose to in which
mode these IC’s should be used for better efficiency, which 2. EXISTING TECHNIQUES
one to choose, PMOS or NMOS. Since PMOS consumes
and dissipates more power compared to NMOS, it was
obivious that NMOS was chosen. If we talk about the modeThe proposed works of [1] , [2] and [5] have used concept of
of operation than we know that in cutoff region MOSFET temperature compensation technique for low TC’s . Most of
consumes zero power with the transistir in off mode. Now, Them follow first order or 2nd order and also High order
in triode mode, the transistor acts as resistor whose Temperature compensation technique. Some of them also
resistance is a function of the voltage to the gate terminal. use ATC(adjusted temperature curvature) which also helps to
reduce temperature drift and to enhance the voltage of band
Due to the change in power consumption, most applications gap reference circuit . But ATC makes circuit complex which
choose the transistor to work in saturation mode. In this increases area. Using 2nd order technique helps to stabilize
mode, the transistor needs a fixed amount of power to work. the temperature.
Later, as technology advanced, CMOS was introduced and
replaced NMOS only technology with CMOS, whichMOSFET should work in sub-threshold [7] region . It helps to
ecapasulated features like very low power consumption, reduce in supply voltage as well as power dissipation
high performance and also provided for high noise .But along with the pros it also has some cons which applies only
immunity. Hence, apllications tried to pursue CMOS high precision circuits only. As discussed in [1], [7] sub-
threshold region problem is the variation of threshold
technology which was more efficient compared to MOSFET
voltage, this result in variation of +-15% in reference voltage
and BJT. Traditional Bandgap Reference circuits were used
. To solve this problem, a new sub-threshold band gap
BJT because gm/Ic of BJT was larger than gm/Id of voltage reference circuit is proposed, In which they do not
MOSFET. But the problem with BJT was that they act like use same body bias voltage and apply current trimming
parasites that mess up with switching circuits by latching up. technique for the purpose to dynamically control the
CMOS circuits dissipate less power compared to BJT, with threshold voltage of MOS. This compensation technique, has
cascade current mirror circuits made from MOSFET far reduced the deviation of the reference voltage by 0.6%, and
better than with BJT and hence BJT doesn’t validate the 3.8% without trimming. since I am not going for implantable
construction of ultra-low power and high throughput medical application hence sub-threshold region is good for
application circuits. this kind of application. For any band gap reference circuit
PSRR value
should be high for this purpose [2],[6] have used current Vgs is the gate-source voltage,
mirror circuits. The purpose of resistance of high value is Vds is the drain-source voltage,
to achieve low current in sub-threshold region but the Vth is the threshold voltage,
problem with the high value resistance is that it increases h is the sub-threshold slope factor.
the area of the circuit and make unsuitable for ultra –low
power large scale integrated circuits [4]. Researchers have
solved this problem by the development of a band gap The characteristic current
reference circuits without the use of resistor as well as BJT Io = µCOX(η-1)VT2 (2)
[6],[3].
Where,
3. PROPOSED METHODOLOGY Thermal voltage Vt = kBT/q,
The proposed circuit consist of a start-up circuit, cascade kB is the Boltzmann constant,
current mirror circuit acting as a current reference circuit and q is the elementary charge,
voltage reference circuit. The start-up circuit in the Bandgap µ= µo(TO /T)m is the carrier mobility, in which µO is the
reference circuit is used to push the circuit from the electron migration rate of MOSFETs at room temperature,
undesired operating point to desired operating point. Once TO is reference temperature,
the circuit reaches the desired operating point, the start-up T is the absolute temperature, and
circuit automatically turns off, and doesn’t interfere with the m is the mobility temperature exponent .
working of other parts of circuit. In the proposed
circuit(Fig.1.) M1,M2,M3 and M4 act as start-up circuits. The generated current is dependent on temperature
The other part of CMOS BGR consist of current reference controlled by R1. In weak inversion forward saturation region
circuit and voltage reference circuit. There are two cascode VDS>4VT. The differential current ∂ID can be expressed as
current mirror circuit ,M5-M8, acting as PMOS cascode
current mirror circuit and M9-M12, acting as NMOS cascode
current mirror. Together with R1 and the cascode current
circuits, a
bias current dependent on temperature is generated.
𝜕𝐼D K12
ηKb 𝑙 (3)
𝜕𝑇 = 𝑅1𝑞 𝐾11
𝑛

Current generated from M5 to M12 is copied to voltage

reference circuit which is controlled by R1, which finally
produces two output voltages from the respective reference
circuit. To filter this reference, an external capacitor C1 and
C2 is used.
I. RESULTS AND DISCUSSIONS

The reference voltage obtained is around

Vref1=281.28mv and Vref2=320.52mv (Fig.2.) with
variation coefficient is around 1.4%-1.8%.This is achieved
by Monte Carlo simulation for 2000 samples at room
temperature. Finally, Mean value is calculated for both Vref1
and Vref2 which gives us the average value of Vref1 and
Vref2 and also Variation coefficient is measured .

Fig.1. Proposed BGR circuit

It is necessary for a current mirror to be dependent of
temperature, supply voltage and process variation and the
current can be express as
𝑉𝑔𝑠−𝑉𝑡ℎ Vds
ID=KIoexp( )[1 − exp (− )] (1)
𝜂𝑉𝑡 Vt

Where,
ID is the drain-current,
K is the aspect ratio of the MOSFETs,

Fig 2. Monte Carlo simulation of output voltages for
2000 samples. Simulation of Vref1 and Vref2.
In Sub-threshold mode, CMOS voltage reference by
using the MOSFET at high threshold voltage (HVT), an
ultra- low supply voltage (0.45V or at less)is achieved, but a
trade off in larger temperature coefficient (TC) limits its
application.
Fig. 4. Simulation for LS vs Vref1
The graph of PSRR vs. Frequency( Fig.5. and Fig.6)
should show high values in the range of -50dB to-100dB. To
enhance the PSRR value double cascode current circuit is
used which significantly increase the PSRR value compared
to currently available band gap reference circuit .

Fig 5. Simulation of PSRR of Vref1.

It is observed that the measured PSRR of proposed
design is higher than -50dB@100 Hz. This decreases with
increase in frequency from 100Hz to 10 KHz. However, it
increases when the frequency is higher than 10 KHz .

Fig 3. Simulation TC of Vref1 and Vref2;

The graph of temperature coefficient(TC) vs Vref should
be linear i.e constant w.r.t Temperature. It is seen(Fig.3.) that
the power dissipation drops down significantly by 27% at
temperature ranging from 0-100 ℃ . In the temp range 0-
1000C, analysis is done and the TC values obtained using
the formula
𝑉𝑚𝑎𝑥−𝑉𝑚𝑖𝑛
Temp. Coeff =
𝑉𝑛𝑜𝑚𝑖𝑛𝑎𝑙(𝑇𝑚𝑎𝑥−𝑇𝑚𝑖𝑛) 𝑥 (4)

We get TCs of output voltages as 12.53ppm/ ℃ and

14.28ppm/ ℃ respectively. This result is a significant
improvement on currently available low-voltage bandgap
references. Temperature dependent analysis is done to
achieve better performance by reducing the temperature
using compensation techniques. The mean LS(Fig.4.) s
0.11% under a supply voltage ranging from 0.9v to 3.1v at
room temperature.
4. CONCLUSION
The reference voltage Vref1 and Vref2 is obtained through
Monte Carlo Simulation graph by taking samples of around
100-200. For each graph, the values of Vref1 and Vref2 is
observed and the average of Vref1 and Vref2 is calculated to
Fig 6. Simulation of PSRR of Vref2.
Compared with circuits without cascode current mirrors
and capacitor C , we observe that PSRR in our proposed
work is improved by more than 5dB at low frequency
and15dB at high frequency, respectively.
obtain the expected output reference voltage with their
variation coefficient. For Temperature Coefficient
determination, the value of TC in PPM/℃ (parts per million
degree Celsius) is calculated. This value should is nearly
constant for every temperature from min to max. Hence, we
propose that the output voltage provided by reference circuit is
independent of temperature , supply voltage and other
external factors with a Temperature coefficient of around
12- 14PPM/. Hence, the proposed circuit provides better
temperature coefficient and line regulation.

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