A Low-Power Decibel-Linear CMOS Automatiac Gain Control

Xin Lv, Junyu Shi, Jingjing Zou, Si-Heng Zhu, Ya-Fen Ge, Yong Liu, and Li-Ming Si
Department of Electronic Engineering, School of Information and Electronics, Beijing Institute of Technology, Beijing, China

This paper presents an all CMOS decibel-linear Automatic Gain Control (AGC). This AGC achieves large dynamic range with low
power consumption. By applying digital switches to change exponential approximation function, four dynamic ranges (62, 50, 33, 26 dB)
are realized. This AGC is implemented in TSMC 0.18-μm CMOS RF process. Measurement results show that this AGC achieves 60 dB
linear range with linearity error less than 1 dB. The whole circuit consumes 3.6 mA from 2-V supply.

Index Terms—Automatic gain control (AGC), variable gain control (VGA), decibel linear, low-power.

I. INTRODUCTION

A UTOMATIC gain control (AGC) plays an important role in

many applications which require large dynamic range,
like hearing aids, wireless communication systems, and optical
communication systems [1]-[4]. In wireless communication
systems where the amplitudes of input signals vary a lot, AGC
is an essential part for its ability to stabilize the amplitude of
output signals [5]. By automatically controlling the gain of
amplifier in response to changing input, AGC can maintain a
constant amplitude output. The variable gain amplifier (VGA)
should have exponential constraint on the gain characteristics
to obtain constant and signal independent settling time [6].
Thus, with an exponential control voltage, the proposed AGC
can have a decibel-linear characteristic. The exponential
function is realized by an approximation function. In addition,
power consumption has been a hot topic in analog CMOS
systems for decades due to market demands [7]. A cross
coupled pair technology is used to acquire good linearity and
low power consumption in this design.
This paper details a low power and decibel linear AGC
which can offer four dynamic ranges (62, 50, 33, 26 dB). This
is achieved by changing the approximation function without
changing the circuit topology. With a 2-V supply, the
measured gain matches the ideal linearity curve.
The paper is organized as follows. Section Ċ describes
principles and circuits implementation of the proposed AGC.
Section ċdescribes verification of simulations and
measurements. And a discussion of measured bandwidth
compared to simulation results is described in Section Č. The
conclusion is drawn in Section č
II. PRINCIPLE AND CIRCUIT IMPLEMENTATION
A. Principle of Proposed AGC
The proposed AGC scheme is described in Fig. 1. It consists
of exponential generator whose output I C 2 / IC1 can be
controlled by a bias voltage. Subsequently, this signal will be
used in Variable Gain Amplifier (VGA) to adjust the output
____________________________________
978-1-4673-6329-7/13/$31.00 ©2013 IEEE
Fig. 1. Block diagram of the proposed AGC
gain. After that, the output voltage of VGA is detected by peak
detector and changed into a DC voltage. Then, the DC voltage
is compared to a reference voltage Vref in error amplifier. And
the difference of them is amplified at the same time. After that,
the output of error amplifier will be applied to a low pass filter
to suppress the noise and undesired signal, and the output is
used as control voltage for exponential generator. This feed-
back system is able to adjust gain according to input voltage,
and finally stabilize the amplitude of output signal.
B. Exponential Generator Circuits
The gain settling time should be constant in wireless
communication system with consideration of Signal to Noise
Ratio (SNR). Constant settling time requires the AGC circuit is
exponentially controlled [6]. Thus, exponential generator is
necessary to convert DC control voltage to an exponential
signal. However, CMOS transistors work under square-law.
Exponential function is realized by pseudo-exponential and
Taylor series approximation functions. The exponential
generator circuits in this design apply a new approximation
functions proposed by [8], which is given by
k  (1  ax) 2
e2 ax  (1)
k  (1  ax) 2
where k is a constant whose value is given by (2) in the circuit
shown in Fig. 3.
I0
k (2)
K (VDD  | VTH )2
From Fig.3, the output current ratio I C 2 / IC1 is an
exponential function of control voltage VC . And the output


 Fig. 2. Circuit block of VGA stage

function can be shown as

2
I0  VC 
 1 
IC 2 K (VDD  | VTHP |)
(VDD  | VTHP |) 
2

 2
(3)
I C1 I0  VC 
 1 
K (VDD  | VTHP |) 2
(VDD  | VTHP |) 
Fig. 3. Circuit of exponential generator
C. Variable Gain Amplifier
VGA is the essential block in AGCs, which should offer D. Switched Dynamic Range and Other Circuits
variable gain and maintain good linearity. Fig.2 illustrates the As shown in (2), the constant k in exponential
VGA circuit. The control current I C 2 and I C1 in Fig. 3 are approximation is a function of I 0 . By controlling I 0 , different
mirrored to M 7 and M 8 respectively. Then, the gain of VGA approximation functions can be acquired without changing the
circuits. This can be achieved by adding digital switches to
amplifier circuits can be expressed as
control the current contributing to I 0 . Thus, coarse gain with
g m3,4 (W / L)3,4 I C 2
Adm   (4) large dynamic range and fine gain with little dynamic range is
g m5,6 (W / L)5,6 I C1 available.
Other parts of the AGC circuit were designed but not
Note that the dynamic range of Adm is half of I C 2 / IC1 ’s. A detailed for space reasons: peak detector, error amplifier,
two stage VGA is needed to acquire the same dynamic range passive filter, digital switches, and current-bias circuits.
with I C 2 / IC1 . With the two amplifying blocks shown in
III. MEASURED RESULTS
Fig.1, more than 60 dB gain variation is achieved. As there are
two current sources in each branch, the bias voltage of The AGC shown in Fig.1 including power block is
amplifying transistors can deviate, possibly. Therefore, a fabricated in the TSMC 0.18-μm RF CMOS process. The die
common-mode feedback circuit shown in Fig.2 is needed to photo is shown in Fig.5.
maintain a constant working condition. The two stage VGA was measured by using input signals
There are several ways to enhance the linearity of VGA from SONY AFG320. The output was measured by an Agilent
circuit, resistive degeneration, MOSFET working in triode MSO-X 2012A oscilloscope. Fig.4 shows measured gain
region, adaptive bias, and sub-band technology. Since most of versus control voltage. The measured gain has a linearity error
them consumes lots of power, a cross coupled pair topology is of less than 1 dB. Measured frequency responses of different
used in VGA to acquire good linearity and low power gains are shown in Fig. 6. The results show that the circuit can
consumption. As shown in Fig.2, M 3 , M 4 , M 3 ' and M 4 ' cover the required bandwidth of 10 MHz. The AGC simulation
rd results versus measurement results are shown in table 1.
form the cross coupled pair. The 3 order nonlinear coefficient
of output differential mode power is given by IV. DISCUSSIONS
(  C )  (W / L)1,2
3/2 3 3 
(W / L)3,4 The measured bandwidth decreases compared to simulation
c3   n ox   (5)
8  IC 2 I C1 results in table 1. After comprehensive consideration, the

 decrease is possibly caused by parasitical capacitance brought
By a careful design of (W / L)1,2 and (W / L)3,4 , c3 can be by oscilloscope. To verify this assumption, parasitical
capacitance was added to the AGC circuits to run an AC
eliminated.
response analysis. The value of capacitance is got from the


 TABLE I
SIMULATION AND MEASUREMENT RESULTS FOR THIS AGC

Simulation Measurement

Process 0.18μm RF CMOS 1P6M

Die size (with 50 pads) 0.9mm×2.5mm
Die size (AGC only) 200μm×150μm Fig. 5. Die photo of this AGC
65dBǃ50dBǃ 62dBǃ50dBǃ
AGC gain range
35dBǃ28dB 33dBǃ26dB
AGC gain accuracy İf1dB
72MHz@ Vc=1V --
VGA bandwidth
62MHz@ 14MHz@
Vc=1.3V Vc=1.3V
2.297%@600mV 5%@600mV
input input
THD
8.5%@800mV 9%@800mV
input input
AGC output voltage 1.3V 1.2V
Amplitude error of
İ10mV İ20mV
output
AGC settling time 5μs 8μs
Power supply 2V 2V
Itotal 3.5mA 3.6mA
Fig. 6. Measured frequency response of this AGC at different
gain settings

60

40

20
Gain (dB)

0
simulation
-20 measured
ideal
linearity error of 1dB
-40

0.0 0.5 1.0 1.5 2.0

Vc (V)
Fig. 7. Simulated frequency response of this AGC with parasitical
Fig. 4. Measured gain of this AGC versus control voltage capacitance of oscilloscope added

lable on MSO-X 2012A oscilloscope. The simulation result is
shown in Fig. 7. The 3 dB bandwidth with VC =1.3V changes
from 62 MHz to 16.65 MHz, which matches the measured
results. Thus, the parasitical capacitance of measurement
equipment changes the bandwidth. This can be solved by
adding output buffer to the circuits.
V. CONCLUSION
This paper presents a fully integrated CMOS AGC with
wide dynamic range and low power consumption. The output
voltage amplitude varies less than 20 mV with input signals of
peak to peak values. In addition, the dynamic range can be
switched by digital bits. This AGC achieves a more than 60 dB
linearity range while dissipating 3.6 mA from a 2-V supply.
ACKNOWLEDGMENT
This work is supported by the National High Technology
Research and Development Program of China under Grant
Nos. 2012AA8123012 and 2010CB327505, the Basic
Research Foundation of Beijing Institute of Technology under
Grant No. 20120542015, and the Academy of Satellite
Application under grant No. 2012-1692.
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