IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO.

2, FEBRUARY 1996 157

Low-Power CMOS Continuous-Time Filters

Rajesh H. Zele, Member, ZEEE, and David J. Allstot, Fellow, ZEEE

Abstract- A design technique for low-power continuous-time VDD

filters using digital CMOS technology is presented. The basic I I I I 1
building block is a fully-balanced integrator with its unity-gain
frequency determined by a small-signal transconductance and
a MOSFET gate capacitance. Integrator excess phase shift is
reduced using balanced signal paths, and open-loop gain is in- t
creased using low-voltage cascode amplifiers. Two-pole bandpass
and five-pole lowpass ladder filters have been implemented in a
1.2 pm n-well CMOS process. The lowpass prototypes provided
300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB
dynamic range with 1% total harmonic distortion (THD), and 30
pW/pole (300 kHz bandwidth) power dissipation with a 1.5 V
supply; the bandpass prototypes had a tunable center frequency
of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75
pW/pole (525 kHz center frequency) from a 1.5 V supply. The
active filter area was 0.1 “’/pole for both designs.

I. INTRODUCTION

L OW-POWER digital design has emerged as a major

challenge [I]. Although low-voltage design has also been
recognized as a difficult challenge, good results on 1.4 V SC
filters have been presented [ 2 ] .In this paper, the design of 1.5
V continuous-time filters using digital CMOS is described.
Performance characteristics of a fully-balanced integrator are (b)
developed in Section 11, experimental results from bandpass Fig. 1. (a) Single-ended continuous-time current-mode integrator and (b) its
small-signal model.
and lowpass IC’s are given in Section 111, and conclusions
comprise Section IV.
Analysis of the complete small-signal model of Fig. l(b) gives

11. FULLY-BALANCED
CONTINUOUS-TIME
INTEGRATOR

A. Motivation
Clock feedthrougldcharge injection effects limited the ac-
curacy of early switched-current (SI) integrators [3], [4], al-
though clever clocking schemes have recently eliminated such
errors [5]. The ultimate solution to this problem-removal
of all sampling switches-results in the continuous-time in-
tegrator of Fig. l(a) [6]. Neglecting output conductances and
parasitic capacitance C1 and assuming identical transistors,
analysis of Fig. I(b) yields if = S(ip - in).
The unity-gain frequency W O M ( g m / C 2 ) is established by
MOSFET gate capacitance C, at the input to the second stage.
Manuscript received July 15, 1994; revised July 6 , 1995. This work was
supported by the National Science Foundation Contract MIP-9114515 and by
a Grant from the Asahi Chemical Co. Ltd.
R. H. Zele is with the Radio Products Group, Motorola, Inc., Plantation FL
33322 USA.
D. J. Allstot is with the Department of Electrical and Computer Engineer-
ing, Oregon State University, Corvallis OR 97331 USA.
Publisher Item Identifier S 0018-9200(96)01288-7.
0018-9200/96$05.00 0 1996 IEEE
It is apparent that Qds causes phase lead at WO because of the
pole p l = w o / a where WO = gm/C2, and Q = -gm/4g& is
the low-frequency current gain. Parasitic capacitance C1 on
the input node causes excess phase lag at WO owing to the
nondominant pole pa = gm/C1. By designing for C, >> C1
and using cascodes to reduce output conductances, integrator
Q > 20 can be obtained at high frequencies [7]. However,
the unbalanced signal paths [Fig. 1(a)] limit high-frequency
performance because the first stage introduces a nondominant
pole which decreases the achievable integrator &.
B. Basic Principle
A fully-balanced integrator consisting of a pair of cross-
coupled current amplifiers is shown in Fig. 2(a) [8], [91.
Identical capacitors determine the dominant pole frequency.
Defining i = 4 , = in,io = -ion = iop,and U = -UA = UB,
Kirchoff‘s current law (KCL) analysis of Fig. 2(b) (neglecting
g& and C,,-J components) gives i o = 3
2
which for Fig. 2(a)
158 EEE JOURNAL ON SOLID-STATE CIRCUITS, VOL 31, NO 2 , FEBRUARY 1996

becomes io, - ion = %(ip - in). Scaled output currents are

obtained using additional output branches with M5 and h&
ratioed to M2 and M4, respectively.

C. Second-Order Effects
Small-signal analysis of Fig. 2(b) including gds and C,,
components gives

where

The low-frequency open-loop current gain is A0 = -,

and the unity-gain frequency is

The Cgda ( cgd4) causes a right-half plane (RHP) zero which

contributes phase lag at W O in integrator analysis.
Cancellation of the RHP zeros due to the output devices is
an interesting attribute of the resonator of Fig. 3. There are
two equal and opposite signal paths to node Y through b f s
i
and A&: One from wthrough cgd5, and another from x n

through C g d ~ aLikewise,
. since the signals through Cgdsa and
Cgd6, cancel at 2,the transfer function for (zOp1 - ion1)is
unaffected by RHP zeros. The RHP zeros caused by c g d 2 and
Cgd4are not cancelled; however, they do not contribute phase
lag at W O in resonator analysis.
Distributed-channel effects become significant at high fre-
quencies where the MOSFET behaves as a nonlinear RC
transmission line. Although a theoretically infinite number of
poles are contributed to the gm transfer function [lo], [ll],
distributed effects are well approximated with the addition of
(b)
a nondominant pole
Fig. 2. (a) A fully-balanced continuous-time integrator and (b) its
small-signal half-circuit model.
P2,ff.Ct1", = 2.5wt (7)

and the integrator Q [12] is

(Distributed effects of the current sources are ignored.) Since
the RHP zero is cancelled, (3) becomes
Sm
2gds
a, % a (9) From (6) and (10)
(I+ ;HI+ E)
where p l and p 2 are given by ( 5 ) and (7), respectively. From
(9), the excess phase lag at W O is

where 8 is a process channel-length modulation parameter

(0 = XL). Since the phase lead due to the dominant pole is
 ZELE AND ALLSTOT LOW-POWER CMOS CONTINUOUS-TIME FILTERS
159

VDD
7

ions

Fig. 4. Q-tuning circuit in which ML operates in nonsaturation with resis-

tance RL.

and
gm (1 + 7)
SRLC
H(s)= -
sc (1 + 9).
Thus, the series RL and CL introduces a left-half plane (LHP)
pole-zero pair separated by one octave in frequency. Similar
benefits can be obtained using an RC phase-lead network in
parallel with source degeneration resistors for M I - M ~(Fig. 3).
Q-tuning can be realized using amplitude-locked techniques
1131.

D.Noise Analysis
The equivalent input noise current of the integrator in Fig. 5
is [I41
4 K

GND i=l i=5

Fig. 3 . A two-integrator resonator showing feedthrough paths through
gate-drain capacitors.
proportional to L-l, and the phase lag due to the distributed
effects is proportional to L2, an optimum L can be found that
provides first-order phase error cancellation.
At frequencies approaching f T , excess phase lag can be
cancelled using the phase-lead network of Fig. 4 in which
M L operates in the triode region with resistance RL. The
admittance of the phase-lead network in parallel with C1 is
The second term is usually neglected since gml-4 > ~ ~ 5 - In 8 .
ladder implementations where each integrator has two output
-
branches, the thermal noise power is i&T = 1 6 k T g m A f .
Substituting gm = WOC,the input-referred current noise
spectral density is Sz(f ) l n t = 16kTwoC. Thus, the total output
noise power of a doubly-terminated second-order bandpass
filter is [12]
where Q is the filter quality factor, or equivalently
160
Fig. 5. A fully-balanced continuous-time integrator with equivalent-input
noise sources.
VDD
GND
Fig. 6. Low-voltage cascode current amplifier.
As expected, k T / C noise power is reduced using larger
integrating capacitors, and (18) reiterates the point that high-Q
filters exhibit high noise and low dynamic range.
IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL 31, NO 2, FEBRUARY 1996
VDD
vB1
t
1
d
A
Fig. 7. (a) Grounded-gate and (b) regulated-gate cascode current amplifiers.
E. Distortion Analysis
The variation of the transconductance with input current
creates potential limitations:
Total harmonic distortion (THD) increases as the modula-
tion index (peak signal level normalized to bias current)
increases, and
gm decreases with signal level, shifting the filter response.
Distortion performance of the fully-balanced integrator can
be inferred from simple current amplifiers [4]. For identical
circuits with bias I and inputs z and - 2 , the differential voltage
 ZELE AND ALLSTOT LOW-POWER CMOS CONTINUOUS-TIME FILTERS
161

VDD
:I, :1 ,

(b)
Fig. 8. (a) PMOS V,((W/L = (15 p d 3 pm)) and (b) source-to-bulk
leakage current versus VSB.

v is

Fig. 9. Bias current generator used to achieve (a) temperature-independent

gm; (b) temperature-independent small-signal gain where Vref is an on-chip
temperature-independent voltage reference and (W/L)2 = 4( W / L ) l ;(c)
which through a Taylor's series expansion becomes temperature-independent gain where AV, = V T ~ -VT~.

IM3 is
3
I M 3 Z ---z
4121
a3
+ --z258 al .4 +....
a5

Using (20) and (22)

THD increases in accordance with the odd high-order terms
while even harmonics are cancelled.
1) Zntermodulation Distortion: Third-order intermodula- (23)
tion distortion is particularly important in bandpass filters
since it may occur within the passband. Expressing the transfer For small values of IM3 where the first term is dominant
function as
162 IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 2, FEBRUARY 1996

Fig 10. Microphotograph of the two-pole bandpass filter with die area 0.19 mm2.

2) Effects of Transistor Mismatches on Distortion: where is the peak signal amplitude. Increasing (VGS-
Assuming identical P values and a threshold voltage VT)reduces THD but increases the minimum power supply
mismatch of AVT voltage.
3 ) Effects of MOSFET Capacitor Nonlinearities: If a
I . 2
MOSFET is used as an integration capacitor, its nonlinearities
must be carefully considered. In an n-well process, the PMOS
“bottom-plate’’ can be connected to V& (strong inversion) or
ground (accumulation). In strong-inversion
Again using a Taylor series gives

where VGB is the gate-bulk voltage and is the thermal

+
voltage [lo], 1151, [16]. With VGB = VGS ‘U where VGS is
the bias voltage and w is the small-signal voltage (with peak
value S), series expansion gives
where VT = ( V T +~ V T , ) / ~ .The fractional harmonic distortion
(HD) terms are

From Fourier analysis

ZELE AND ALLSTOT LOW-POWER CMOS CONTINUOUS-TIME FILTERS 163

NETWORK NETWORK
A:REF B:REF 0 MKR 430 750.000 Hz A:REF B:REF 0 MKR 910 000. 000 Hz
-25. 00 180. 0 T/R -34.6931 dB -25. 00 180. 0 T/R -36.3446 dB

DIV DIV START 100 000. 000 H z DIV DIV START 100 000.000 Hz
5.000 36.00 STOP 1 000 000.000 Hz 5.000 36.00 STOP 1 000 000.000 Hz
RBW: 100 Hz ST: 40.2 sec RANGE: Rs-10. T a - l O d B m RBW: 100 Hz ST: 40.2 sec RANGE: R=-10, T=-1OdBm
O S C l = -30.0 OEM
Fig. 12. Frequency responses of the bandpass filter as Ibias is varied from
Fig. 11. Bandpass filter response with Vdd = 1.5 V and Iblas= 5 p A 2-25 p~ with vdd = 3 v,
per branch.

1 ) VT Reduction Using Body Effect: The 1.5 V supply

A similar analysis applies for operation in accumulation goal was aggressive since the nominal VT’S ranged from
with VT replaced by the flat-band voltage VFB in (29)-(32). 0.7-1.0 v. with VT = 0.9 v and Vdsat = 0.25 v, the
If a linear capacitor is available, it can be connected between minimum Supply voltage was 1.65 v.
nodes A and B in Fig. 2(a). Since vA = -vB, only half the The PMOS threshold voltage is
capacitance is required, and the parasitics can be matched by
splitting it.
By exploiting the n-well process to apply a negative V&, VT
F. Low-Voltage Operation was reduced to allow 1.5 V operation. Fig. 8(a) shows that VT
can be varied by several hundred mV by varying VSB. As VSB
The integrator consists of cross-coupled current amplifiers
is increased, however, the source-to-bulk junction becomes
for which an important accuracy consideration is the ratio (6)
forward biased and ISB increases exponentially [Fig. 8(b)].
of input to output conductances. For simple current amplifiers
To mitigate latch-up concerns in our design, V& < 0.25 V
(Fig. 2), n = gm/gds. Using cascodes, gout is reduced to
was chosen to limit I S B to <1 nA.
gds/(gm/gds) with 6cascode = +(E)’, and the minimum
+
power supply voltage is Vdd(mln) 2 ~ V T 4Vdsat.
G. Dynamic Range Scaling
Fig. 6 shows a low-voltage cascode current amplifier [17]
with &highswing-cascode = (Ym G )2 and Vdd(min) 2 VTS3Vdsat.
3 Dynamic range is defined as the rms signal level at a
Its disadvantage is that as i increases, M I enters nonsaturation. given THD or TIMD divided by the total rms noise in a
Fig. 7(a) shows a circuit that uses grounded-gate negative specified bandwidth. It is maximized by scaling all integrators
feedback via M I and Ms to increase the input conductance to to have identical ill values [19]. A branch added to the output
integrator compensates for insertion loss.
gds(gm/gds)2 [181, [191. Hence, = (2) 2
and Vdd!mln) 2
+
VT 3Vdsat. Since the conductance at node A is high, the
upper current source can be a single device (M4,M5) which H. Temperature-Independent Operation
simplifies low-voltage design since the outputs contain only Since continuous-time filter response characteristics depend
two series devices. Biasing is easier because signal current on g, and C which vary with process, frequency tuning is
does not flow through M3. Since the potential at the input required for which gm can be controlled by adjusting the
+
node is VSGJ VBZ,lower distortion is obtained for higher bias current. Integrator Q can be tuned using a MOSFET-
(ill)values. Since the conductance at node B is high, errors C network as described earlier. In production designs, these
in the signal current through M I are negligible if I , is a techniques are often embedded in a phase-locked loop tuning
cascoded current mirror. network [21]-[23].
Further improvement in the conductance ratio can be ob- Another way to achieve high accuracy is to derive the
tained using a regulated-gate (RG) structure [20] [Fig. 7(b)] transconductance from a resistor using Fig. 9(a) wherein
where KRGfolded-cascode = (E)3 and Vdd(mm) 2 2% + with (W/L)4 = (W/L)5 and ( W / L ) 2 = 4(W/L)1,
3Vdsat. 1, is implemented as an RG mirror and I R as a simple I= 1
. The resulting unity-gain frequency is
2PnCox(F)LR2
mirror. The RG circuit provides higher accuracy but requires
a higher minimum power supply voltage and greater power
dissipation. Our designs used the cascode amplifier of Fig. 7(a)
which permitted power supply voltages as low as 1.5 V.
164 EEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 2, FEBRUARY 1996

NETWORK
1200.0 A:REF B: REF 0 MKR 392 5 0 0 . 0 0 0 H z
-25. 00 180. 0 T/R -35.4057 dB
C dB 1C deg 1 8 deq
1000.0 I I I I I I I I I I
t I I I I I I I I I
1
800.0
Center
Frequency
kHZ 600.0

400.0

200.0
0.0
' 10.0 20.0
I
30.0
lbias @A)
DIV DIV START 100 000.000 H z
5.000 36.00 STOP 1 000 000.000 Hz
Fig. 13. Center frequency of the bandpass filter versus bias current per RBW: 100 H z ST: 40. 2 sec RANGE: R--lO. T==-lOdBm
branch with V& = 3 V.
Fig. 14. Bandpass filter responses for vdd = 1.4-5 V with Ib,,, = 5 PA
per branch.
or equivalently
NETWORK
1 A:REF B:REF 0 MKR 430 750.000 Hz
WO = -. (35) -25.00 180. 0 T/R -34.6956 dB
RC C dB 1C deq 1 8 deq

Considering only gm variations, the response is process- and

temperature-independent to the degree that the trimmed resis-
tor is accurate and temperature-stable. For on-chip polysilicon
resistors, the temperature coefficient of resistance is typically
in the range of 500-1500 p p d " C .
Temperature-independent integrator gain is obtained using
the bias generators of Fig. 9(b), (c)

DIV DIV START 100 000.000 Hz

5. 000 36. 00 STOP 1 000 000.000 Hz
In Fig. 9(b), use of a temperature-independent voltage refer- RBW: 100 H z ST: 40. 2 sec RANGE: R=-10. T = - l O d B m
ence provides a bias current proportional to mobility ( p n ) ;
Fig. 15. Measured responses of 22 bandpass filters with Iblas = 5 pA per
another method uses a temperature-independent threshold volt- branch and Vdd = 1.5 V. Statistlcs: p w o = 434 kHz, ow0 = 11 kHz,
age difference as in Fig. 9(c) in which p~ = 8.56, and OQ = 0.7.

(37) isolated and controlled by backbias to provide the needed V,

1
A0 = __
vz
where V, = Vref [Fig. 9(b)] or V, = AVT [Fig. 9(c)]. A
disadvantage of this technique is that the bandwidth is more
sensitive to temperature which requires a larger frequency-
tuning range.
111. EXPERIMENTAL
RESULTS
Two-pole bandpass and five-pole lowpass filters were imple-
mented using a 1.2 pm n-well CMOS process. All integrators
were laid out using unit-cells, care was taken to minimize
crosstalk between signal lines, and parasitic capacitances were
matched. All bias voltages were generated locally. Input w-z
conversion was perfomled using on-chip polysilicon resis-
tors in conjunction with extemal transformers. A differential
current to single-ended output voltage conversion was imple-
mented using a transformer and off-chip resistors. Integration
capacitors were implemented as PMOS devices with their
sources and drains connected to an n-well; the backgates were
reduction for 1.5 V operation.
(38)
A. Two-Pole Bandpass Filter
A microphotograph of the two-pole bandpass filter is shown
in Fig. 10, and the measured responses are displayed in
Fig. 11. With a bias current of 5 pA per branch, the center
frequency was 430.75 kHz and the Q was 8.7; these values
agreed closely with HSPICE simulations of the circuit with
parasitics extracted from its layout.
Fig. 12 shows magnitude responses of the filter as the bias
current was varied from 2-25 p A per branch. The Q errors at
the higher bias currents are caused by cascode transistors leav-
ing saturation. Fig. 13 plots center frequency versus branch
bias current; the expected square-law dependence of gm on
bias current is observed.
Fig. 14 shows the effects of power supply variations. Q
remains approximately constant over a range of 1.4-5 V, but
the center frequency is weakly dependent on supply voltage
because of channel-length modulation effects. These variations
can be eliminated using cascoded bias current sources.
 ZELE AND ALLSTOT LOW-POWER CMOS CONTINUOUS-TIME FILTERS 165

Fig. 16. Microphotograph of the five-pole Chebyshev filter with area 0.47 mm2.

Twenty-four of 25 chips obtained from MOSIS were func-
tional; two exhibited gross response errors. Fig. 15 shows
the measured responses of the 22 best samples. The average
center frequency (pw,) was 435 kHz with an 11 HZ standard
deviation (cue), and p~ = 8.56 with CQ = 0.7.
B. Five-Pole Lowpass Filter
A microPhot%raPh of the five-Pole lowpass filter is shown
in Fig. 16. The frequency responses versus branch bias current
plotted in Fig. 17 show passband ripple variations of less than
166 IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 2, FEBRUARY 1996

1OOK 1M I OM
Frequency (Hz)

Fig. 19. Effects of supply voltage variations on the lowpass filter response.
Suffix b indicates where backgate bias was used to reduce VT.Iblas = 5pA
per branch.

dB

DIV DIV START 100 000.000 Hz

(b) 1. 000 36.00 STOP 1 0 000 000.000 H z
RBW: 100 H z ST: 40.2 sec RANGE: R- 0. T=-lOdBm
Fig. 17. (a) Frequency responses of a five-pole Chebyshev lowpass filter D I V= 1. 00000E+OO
with Iblas of 2-11 pA per branch and Vdd = 1.5 V. (b) Passband details.
Fig. 20. Measured responses of 22 lowpass filters with Iblas = 5 p A per
branch and Vdd = 1 5 V Statistlcs pLw0= 525 kHz, ouo = 16 kHz,
firIpple = 0 3 dB, and grlpple = 0 05 dB

Fig. 19 shows the effects of power supply voltage variations

on the passband characteristics of the lowpass filter. With a
power supply voltage of 1.4 V, the response tends to droop.
After applying backbias to the input transistors to reduce the
threshold voltage, passband accuracy improves.
Fig. 20 displays the responses of the 22 best samples in
which puo = 525 kHz and oWo= 16 kHz. The average
passband ripple is 0.3 dB with standard deviation of 0.05 dB.
Fig. 21(a) plots THD versus (irms/Iblas), and Fig. 21(b)
shows that THD increases by only 1 dB as the supply voltage
2.0 4.5 % 6.0 8.0 70.0 12.5 is reduced from 5 to 2 V. With backbias invoked to reduce
lbias (pd) VT,THD is reduced by 4 dB. Tables I and I1 summarize the
measured results.
Fig. 18. Measured cutoff frequency versus bias current per branch for the
lowpass filter.
IV. CONCLUSIONS
A technique for continuous-time filters using digital CMOS
0.2 dB. The cutoff frequency versus bias current is plotted in technology has been presented. The original single-ended inte-
Fig. 18. grators that evolved from a solution to the clock-feedthrough
ZELE AND ALLSTOT LOW-POWER CMOS CONTINUOUS-TIME FILTERS 167

-3 dB cut-off frequency (mean) 525 kHz

Passband ripple (mean) 0.31 dB
Power supply voltage 1.5-5 Volts
I
Power dissipation 75 pWfpole
(Vdd 1.5-V, Ibias 5 pA)
Total inband output noise 3.53 nAms
Maximum differential input current 0.8
modulation index (THD = 40dB)
~~~~ ~ ~~

Dynamic Range (1% THD) 67 dB

CMRR (inband) 70 dB

PSRR (minimum) IadB

Tuning range 3ookHz- lMHz
Area 0.1 mm2/polt3

developed by adding an output branch and a MOSFET ca-

Power supply voltage (V) pacitor. Consequently, phase errors were reduced because the
nondominant poles were moved further above the unity-gain
(b) frequency. The balanced circuit exhibited increased dynamic
Fig. 21. (a) Measured lowpass filter THD versus input modulation index range because the input range was doubled and even-order
(irms/Ihlas) with I/& = 1.5 v and rb,,, = 5 p A per branch with harmonics were cancelled. Integrator dc gain was increased
frequency = 50 kHz and bandwidth = 500 kHz. (b) Measured THD versus
supply voltage with differential modulation index = 0.8, frequency = 50 using a folded-cascode circuit topology which also increased
kHz, and Ih,,, = 5 @Aper branch. The dotted line indicates where backgate the input signal range. Experimental results from 1.2 pm
bias was used to reduce V,. CMOS prototypes demonstrated a 300 kHz-1 MHz tunable
bandwidth, a dynamic range of 67 dB with a 1.5 V supply,
and a power dissipation of 30 pWIpole at a branch current of
Ibias = 2 PA.

Center frequency (mean) 435 lrHz

ACKNOWLEDGMENT
-3 dB bandwidth (mean) 50.8 kHz
The contributions of Dr. S.-S. Lee, Dr. A. Barlow, K. Taka-
Power supply voltage I 1.5-5Volts suka, and T. Adachi are appreciated, and insightful comments
from the anonymous reviewers are gratefully acknowledged.
Power dissipation 60 pWJpole
(Vdd 1.5-V, Ibias 5 PA)
REFERENCES
Total inband output noise 1.788 “A,,
A. P. Chandrakasan, S. Sheng, and R. W. Broderson, “Low-power
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473483, Apr. 1992.
T. Adachi, A. Ishikawa, A. Barlow, and K. Takasuka, “A 1.4 V switched
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pp. 8.2.1-8.2.4.
Tuning range 300kH~-1MHz J. B. Hughes, N. C. Bird, and I. C. Macheth, “Switched currents-A

Area 1 0.1 mm’/pole
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Oct. 1991.
168 IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 2, FEBRUARY 1996

[7] S. S. Lee et al., “CMOS continuous-time current-mode filters for David J. AIlstot (S’72-M’78-SM’83-F’92)
high-frequency applications,” IEEE J. Solid-State Circuits, vol. 28, pp. received the B.S. degree in engineering science
323-329, Mar. 1993. from the University of Portland, Portland, OR, the
[8] R. H. Zele, S. S. Lee, and D. J. Allstot, “A 3 V-125 MHz CMOS M.S. degree in electrical and computer engineering
continuous-time filter.” in Proc. IEEE Int. Symp.
. - Circuits Syst., 1993, from Oregon State University, Corvallis, OR, and
pp. 1164-1167. the Ph.D. degree in electrical engineering and
[9] S. L. Smith and E. Sanchez-Sinencio,“3 V high-frequency current-mode computer science from the University of California
filters,” in Proc. IEEE Int. Symp. Circuits Syst., 1993, pp. 1459-1462. at Berkeley in 1979. His Ph.D. work dealt with the
1101 Y. P. Tsividis. Oaeration and Modeling of the MOS Transistor. New
L~ _ ” analysis, design, and implementation of switched-
York: McGraw-Hill, 1988. capacitor filters.
r l l l H. Khorramabadi and P. R. Gray, “High frequency CMOS continuous- He has held industrial positions with Tektronix,
- time filters,” IEEE J. Solid-State Circuits, vol. 19, pp. 939-948, Dec. Texas Instruments, and MOSTEK, and academic positions with UC Berkeley,
1984. Southem Methodist University, and Carnegie Mellon University. He is
[ 121 H. Khorramabadi, “High-frequency CMOS continuous-time filters,” currently Professor of Electrical and Computer Engineering at Oregon State
Ph.D. Dissertation, Univ. of California, Berkeley, Feb. 1985. University, Corvallis, OR. He has advised about 40 M.S. and Ph.D. students
[13] V. Gopinathan, Y. P. Tsividis, K. S. Tan, and R. K. Hester, “Design and has published more than 100 papers and one book with colleagues.
considerations for high-frequency continuous-time filters and implemen- Dr. Allstot’s professional service has included: Associate Editor of the IEEE
tation of an antialiasing filter for digital video,” IEEE J. Solid-State TRANSACTIONS ON CIRcurrs AND SYSTEMS, Editor of the IEEE TRANSACTIONS
Circuits, vol. 25, pp. 1368-1378, Dec. 1990. ON CIRCUTSAND SYSTEMS 11 ANALOG AND DIGTALSIGNALPROCESSING,
[ 141 P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Guest Editor for the IEEE JOURNAL OF SOLID-STATE CLRCUITS, Technical
Circuits, 3rd ed. New York: Wiley, 1993. Program Committee member of the IEEE Custom IC Conference, the IEEE
[ 151 R. S. Muller and T. I. Kamins, Device Electronicsfor Integrated circuits,
International Symposium on Circuits and Systems, the 1994 Symposium on
2nd ed. New York: Wiley, 1986.
Low Power Electronics, and member of the IEEE Circuits and Systems Society
[16] A. T. Behr, M. C. Schneider, S. N. Filho, and C. G. Montoro, “Harmonic
Board of Governors. He is currently a member of the Technical Program
distortion caused by capacitors implemented with MOSFET gates,”
IEEE J. Solid-State Circuits, vol. 27, pp. 1470-1475, Oct. 1992. and Executive Committees of the IEEE International Solid-state Circuits
[ 171 J. N. Babanezhad and R. Gregorian, “A programmable gain/loss circuit,” Conference. He was a co-recipient of the 1980 IEEE W.R.G. Baker Prize
IEEE J. Solid-state Circuits, vol. SC-22, pp. 1082-1090, Dec. 1987. Paper Award, and the 1995 IEEE Circuits and Systems Society Darlington
[18] J. B. Hughes and K. W. Moulding, “Switched current signal processing Award; he has received excellence in teaching awards from SMU, OSU and
for video frequencies and beyond,” IEEE J. Solid-State Circuits, vol. CMU. He is member of Eta Kappa Nu and Sigma Xi.
28, pp. 314-322, Mar. 1993.
[I91 R. H. Zele and D. J. Allstot, “Low-voltage fully differential switched-
current filters,” IEEE J. Solid-State Circuits, vol. 29, pp. 203-209, Mar.
1994.
[20] B. J. Hosticka, “Improvement of the gain of MOS amplifiers,” IEEE J.
Solid-State Circuits, vol. SC-14, pp. 1111-1 114, Dec. 1979.
[21] C. S. Park and R. Schaumann, “Design of a 4-MHz analog integrated
CMOS transconductance-C bandpass filter,” IEEE J. Solid-state Cir-
cuits, vol. SC-23, pp. 987-996, Aug. 1988.
. . J. M. Khoury, “Design of a 15-MHz CMOS continuous-time filter with
1221
on-chip tuning,” IEEE J. Solid-state Circuits, vol. 26, pp. 1988-1997,
Dec. 1991.
2231 B. Nauta, “A CMOS transconductance-C filter technique for very high
frequencies,” IEEE J. Solid-State Circuits, vol. 27, pp. 142-153, Feb.
1992.
[24] R. H. Zele, “Low-voltage CMOS continuous-time filters,” Ph.D. Dis-
sertation, Carnegie Mellon University, Pittsburgh, PA., Apr. 1994.

Rajesh H. Zele (S’90-M’95) received the

B.Tech.(Hon.) degree in electrical engineering
from the Indian Institute of Technology, Bombay,
India, in 1989, the M.S.E.E. degree in electrical
and computer engineering from Oregon State
University, Corvallis, OR, in 1990, and the Ph.D. in
electrical and computer engineering from Carnegie
Mellon University, Pittsburgh, PA, in 1994.
From 1989 to 1990, he was a graduate teaching
assistant at Oregon State University working
on CMOS high freauencv
U I , transconductors and
switched-current filters. In the Fall of 1991, he worked as an intem engineer
at Hewlett-Packard, Corvallis, on low-noise CMOS current-steering logic
for mixed-mode applications. His research interests are the CMOS analog
and digital circuits for low-voltage and low-power applications. His Ph.D.
work dealt with design and implementation of 1.5-V continuous-time
filters in digital CMOS process. Since 1994, he has been with Radio
Products Group, Motorola, Plantation, FL, where he is developing low-power
communication circuits.
Dr. Zele was awarded National Merit Scholarship from the Govemment
of India from 1984 to 1989. He was a co-recipient of SRC Inventor’s
Recognition Award in 1994. He is a member of Sigma Xi.