Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)

IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

Design of Two Stage CMOS Op-Amp with High

Slew Rate and High Gain in 180nm
Akhil Gupta* Shweta Singh
NIT Uttarakhand NIT Uttarakhand
Srinagar (Garhwal), Uttarakhand Srinagar (Garhwal), Uttarakhand
ag123akhil@gmail.com Shweta.ece15@nituk.ac.in

Abstract— This paper present a CMOS two stage op-amp
using 180nm technology. Keeping the 1.8 V dc supply with 50uA
bias current this amplifier produces a gain greater than 66dB
along with a very high slew rate of 95 V/us. On decreasing the
current the gain can be increase but the slew rate will also
decrease which will going to effect the sensitivity of the amplifier.
Therefore a high slew rate amplifier has design along with high
gain without any much power consumption. The various
parameter such as Gain Bandwidth Product, Phase margin,
Power consumption are measured. The results shows that the on
decreasing the size of MOSFETs the power dissipation also
decreases.
Keywords— Compensation Capacitor, Phase Margin, Gain
Bandwidth Product, CMRR, ICMR, CMOS Analog circuit.
pole which is nearer to 0 frequency is tried to decrease in such
a way that the 0dB frequency is achieved before the second
pole. So that our system can behave like a single pole system.
By the miller effect it can be concluded that if any capacitor is
added between input and output of any system then it can be
split into two capacitor one of input side C(1+Av) and of
output side C(1+1/Av). Now the C(1+Av) will also come in
parallel with differential amplifier parasitic capacitance,
therefore the net capacitance will increase and the dominant
pole will decrease. The block diagram of two-stage op-amp is
shown in Fig.1.The output buffer is normally present only
when resistive loads needs to be driver. If the load is purely
capacitive, it is not needed.

I. INTRODUCTION

T HE op-amps are one of the most versatile and important

building block in analog circuit design. Operational
amplifier have high forward gain and used mostly as a
feedback system. But when there is a requirement of very high
gain a two stage op-amps are used because a single stage op-
amps or a differential amplifier can’t provide very high gain.
So to increase the gain there must be one more component
after the differential amplifier [7]. And the simplest amplifier
Fig. 1 Block diagram of two stage op-amp
can only be common source amplifier. The common source
amplifier can be of NMOS or the PMOS. The PMOS common But the miller theorem cannot be apply here because of
source amplifier is generally used because NMOS common many regions like pole splitting and at very high frequency the
source amplifier limits the swing. Therefore the two stage op- Cc will become short circuit and current will flow through it.
amp will have two stages, one is the differential stage and But circuit comes after applying the miller theorem do not
another one is common source stage. In case of single stage follow it. Therefore there is need to derive the transfer
op-amps there is no issue regarding the phase margin or function manually.
stability because differential amplifier is single pole system.
But in two stage op-amps two poles are there one due to the
parasitic capacitance of differential amplifier and common
source and the other due to the load capacitance [2]. Therefore
the stability factor should be consider during the design of
amplifier.

II. BLOCK DIAGRAM OF TWO STAGE OP-AMP

The bode plot of two stage shows two pole before the gain
becomes 0dB. Due to this the phase margin of amplifier comes
out to be the very less which is not feasible. Therefore to
Fig.2 Internal circuit of two stage op-amp
increase the stability dominant pole method are applied. The

978-1-5386-1442-6/18/$31.00 ©2018 IEEE 341

 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

decrease therefore it is tried to keep it away from the GBW

frequency. At the same time the zero should we far away from
the GBW therefore it can be taken as Z=10xGBW.
(1) The angle can be calculated by below equation:

(2)

By solving the above two equation the net transfer function of At the GBW frequency the phase margin can be calculated by
the two stage op-apm has calculated and then compared with putting the values of Z, P1 and P2.
the general equation of two pole system having one zero.

General equation:
We have to make this angle >60 degree. The phase margin
(3) will be the difference between the angle at P2 and angle at
GBW frequency. For the 60 PM it should be P2 2.2xGBW
Here P1, P2 are the poles of the system, Z is zero and ADC is (9)
the DC gain of the amplifier. From the above it can be
concluded that if P2>>>P1 then the term S( 1/P1 + 1/P2) will
become S/P1. After comparing the coefficient the expression
of DC gain, location of P1, P2 and Z will come out as follows:

(10)

by solving the Eq. 9 and Eq.10 the Cc can be calculated as

III. DESIGN PROCEDURE

From the Eq.5 and Eq.7 the Gain-bandwidth product can be Steps in Designing Two stage CMOS Op-Amp
find out.
1. The length of transistor is taken to
(8) avoid the Chanel length modulation.
L=500nm

2. The minimum value of the compensation capacitor

should be greater than the 0.22CL.
A. Slew Rate
Slew rate is the rate of change of output means how much CC=400fF
quickly the output can change. If a sudden change in input
occurs at in+ terminal than the current flowing through circuit
3. Slew rate is used to find out the tail current I 5 of the
will not change quickly but the MOSFETs M1, M3, M4 are in
off stage. It means the current will flow through the capacitor amplifier.
Cc. Therefore the output voltage will increase suddenly. And 4.
the rate of change of Vout is called the slew rate.
I5 = 50 uA

5. The aspect ratio of M1 and M2 are find out from

B. Phase Margin GBW.
On the GBW frequency the phase comes out to be between
-90 to -180. If it is very close to 180 then our phase margin will
be very less therefore it should be >45 otherwise not
acceptable. At P2 the phase is approx. 180. If the P2 move gm1 = 160u A/V
towards the GBW frequency then the phase margin will

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 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

For calculating the value of Kp and Kn a separate By putting the value of Vgs1(max) in term of current
diode connected circuit has made up. The graph of the ICMR can be express as follows:
the output current has plotted. And by putting the
value of Vth, Vgs, W/L and Id in below equation the
Kp, Kn has calculated.

By solving the Vdsat5 comes out to be very small

therefore there is need to increase the Vds5 to keep
M5 in saturation. Otherwise the size MOSFET
Kn=233.77 should be very large to keep it in saturation. But if
M5 is very large the corresponding MOSFET in next
Kp=47.23 stage M7 will also going to increase which leads to a
gain reduction. To solve this issue the W/L ratio of
Now by putting the values of gm1, Kn, Id in Eq. 11 MOSFET is taken large so that the drop across M1
the aspect ratio of MOSFETs M1 and M2 has will become very small and a large drop will occur at
calculated as the Vds5.By putting the value Kn, Id5 and Vdsat
W/L5 can be calculated.

8. Aspect ratio of M6 can be find out from 2 stage gain

and size of M3 and M4.
6. Aspect ratios of M3 and M4 are find from the max of
ICMR. To work as amplifier all the transistor must be For the 60 phase margin .
in saturation. Since the MOSFET M3 is a diode
If the M3 and M4 is properly mirrored than the Vgs
connected load it will always be in saturation. But the
and drain voltage of both will be the same. Therefore
MOSFET M1 have some constrain if the Vin is
and Vgs3=Vgs4=Vgs6 the
increasing there is a possibility that MOSFET M1 current flowing in these transistor will be
may enter in triode region. So for M1 to be in proportional to their W/L ratio.
saturation the Vds> Vgs –Vth or the Vin(max)= Vd1
+ Vt1.
By putting the value of Vd1 in term of current the
ICMR can be express as follows:
By putting the value of W/L4 , gm6 and gm4 values
the aspect ratio of M6 has calculated.

To find out the min and max value of Vth of different

transistor the differential amplifier circuit is made in
simulator and the Vcm(max) and Vcm(min) is
applied on the input side and corresponding to that
Vth is calculated. Now by putting the value of Vdd,
Id3, Kn, ICMR+, Vth3max, Vth1min in Eq.12 we get
I6=260 uA

7. Aspect ratio of M5 can be determine from the min of

ICMR. If the Vin going to decrease the Vds of M5
will decrease and it may happen that M5 may enter in
the triode region. Therefore to work the M5 in
saturation region .

978-1-5386-1442-6/18/$31.00 ©2018 IEEE 343

 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6

IV. SIMULATION RESULT

Fig.3 Schematic diagram of two stage CMOS op-apm Fig.6 Output of step response

Fig.3 shows schematic diagram of two stage op-apms which

has been design according the above procedure. To plot the
frequency response a ac signal of 1mV is applied at the input
and frequency is swept from 0 to 1000 MHz. From this graph
the GBW Product, Phase Margin, Dominant pole frequency,
Differential gain is calculated. The differential gain is found to
be 66dB and phase margin of 58.5 degree which is good
enough for operation at high frequency. The GBW came out to
be 60MHz. Fig.5 shows the common mode gain which is
calculated by apply common voltage to both input of the
amplifier. The common mode gain is found to be around 6dB
which is very less.

TABLE 1. COMPARISON WITH PREVIOUS RESULT

Results
[7] [8] Proposed
Fig.4 Differential gain, Phase margin, GBW and Dominant pole frequency Technology(nm) 180 180 180
Power supply(V) - 1.8 1.8
Bias Current(uA) 160 20 50
Cc(fF) 100 600 500
Open loop 53 65 66
gain(dB)
Phase 60 60 58.5
margin(degree)
Gain Bandwidth 668 34 60
Product(MHz)
Slew rate(V/us) - 20 95
ICMR(+)V 1.6 1.6 1.7
ICMR(-)V 0.8 0.8 0.9
Power 3582 301 558
Fig.5 Common mode gain of two stage CMOS op-apm consumption(uW)

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 Proceedings of the Second International conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC 2018)
IEEE Xplore Part Number:CFP18OZV-ART; ISBN:978-1-5386-1442-6
The Fig.6 shows output voltage graph when the step input is
applied on the positive gate terminal of the amplifier. From
this graph slew rate is calculated (Slew rate=95 V/us) by
taking the slope of the curve. The power consumption in the
amplifier circuit can be find out by calculating the total current
x Vdd. The power consumption is found to be 558 uW. The
table shown above shows that a very high gain is achieved
along with very high slew rate without using much power
consumption.
V. CONCLUSION
A two stage op-amp is simulated in 180nm technology.
Effective procedure are applied to provide a better
specification like high gain, Phase Margin, GBW, Slew rate
etc. The gain of two stage op-amp was found to be 65dB with
the phase margin of 58.5 degree. If the current will increase
then the gain will going to decrease because the so
if Id is high the gain will going to decrease but at the same
time for a very high slew rate a very high bias current is
required. Therefore if very high gain is required then the size
of MOSFETs M1 and M2 can be increase because the gm will
increases and gain is proportional to gm. MOSFETs M3 and
M4 are controlling the maximum of ICMR. So for very high
ICMR the size of MOSFETs M3 and M4 should be very large.
But at the same time their resistance will we very less due to
that gain will decrease. Therefore an optimal solution should
be find to satisfy the specification. Cc have no effect on gain it
can be increase or decrease but it going to effect on the GBW
product. If Cc is decrease then the GBW product will increase
and for a high slew rate the Cc value should be very large.
978-1-5386-1442-6/18/$31.00 ©2018 IEEE
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