2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

Low-voltage CCII+ Cells-based Tunable,

Variable Gain Instrumentation Amplifier for
Sub-Audio Frequency Signal Processing
Tripurari Sharan
Department of Electronics and
Communication Engineering
North Eastern Regional Institute of
Science and Technology, Deemed to be
University
Itanagar, India
tsh1962mzp@gmail.com
Anil Kumar Gautam
Department of Electronics and
Communication Engineering
North Eastern Regional Institute of
Science and Technology, Deemed to be
University
Itanagar, India
anilgautam19@gmail.com

Abstract —This paper presents a variable gain instrumentation

amplifier (IA) which does not use any passive resistor. It has
utilized two-CCII+ cells and active load made of two-shunt
connected nMOS transistors which produce a varying active
load resistor when activated by adjustable DC voltage in the
range of ±0.2 V. This tunable gain IA provides variable gain
ranging in 40 dB to 80 dB. The input core of CCII+ cell has
used symmetric bulk-driven current mirror OTA with self
cascode load and partial positive feedback to ensure enhanced
input common mode range (ICMR) and small signal
performances even with low-DC voltage supply. The designed
IA possess very high common mode rejection ratio (CMRR)
and power supply rejection ratio (PSRR).
Keywords— OTA, current conveyors, SIMO Biquadratic filter,
Tunable gain, Instrumentation amplifier.
I. INTRODUCTION
The operational amplifier (OA), operational
transconductance amplifier (OTA), current conveyors
(CCs), and current feedback operational amplifier (CFOA)
are various analog design cells used in various analog
processing circuits [1]. OA are used in voltage mode circuit
approach whereas OTA, CCs, CFOA are equally usable in
voltage mode as well as current mode signal processing
circuits. The OTA is an important analog amplifier which is
used in the input core of almost all other cells such as OA,
CCs and CFOA [2, 3]. So, very promising and high
performance OTAs are required for low-voltage and low-
power circuits. Downscaling reduces the CMOS size, but
the threshold voltage of CMOS transistors does not decrease
in the same proportion as does the supply voltage, so there
exits the burden of device threshold voltage in the path of
low-voltage circuits [4, 5]. To ensure increased input
common mode range (ICMR) and output voltage swing
circuit designers prefer bulk-driven approach which favors
low-voltage operation [6].
The bulk-driven (BD) differential pair (DP) topology
comes with its own merits and demerits. Low-voltage
realization with high ICMR and good linearity comes at the
cost of reduced bulk-transconductance (gmb) as compared to
gate-transconductance (gm), reduced gain bandwidth (GBW)
and increased input referred noise [6]. To mitigate this
performance reduction circuit designers, use some shorts of
partial positive feedback (PPF) either in input core of DP
(TE1 approach which produce a negative resistance) or
towards its active load ends (TE2 method called current
starvation approach) [6, 7]. The TE1 approach is considered
for the design of OTA section of CCII+ cell.
The instrumentation amplifier can be realized using
OAs, CCII+ cells or CFOA cells. This work realizes an IA
using few second-generation current conveyors. The CCII+
cells need OTA in its input core. So, at first a low-voltage
bulk-driven current mirror load V to I converter, i.e. OTA
named as (CM-OTA) with PPF is realized. This
performance enhanced OTA is converted into CCII+ cell by
adding two-CMOS inverters to yield the low-impedance X
node and high impedance Z node of CCII+ cell.
The second-generation current conveyors is also used in
the design of single-input multiple output (SIMO)
biquadratic multi-function filter, multiple input single output
(MISO) second order filter, IAs and variable gain
amplifiers, two-phase or three-phase oscillators, integrators,
etc. [8-11].
In this paper a BD-MOST symmetric current mirror
load-based OTA is designed. This is converted to CCII+ cell
using two-inverters and at last this CCII+ cells are utilized
to design a SIMO filter and an active loaded variable gain
instrumentation amplifier of high CMRR and PSRR.
The remaining portion of the paper is organized as
follows. Section II presents realization of bulk-driven
current mirror cum self-cascode load OTA-based CCII+ cell
that has been used to design the CMOS IA. Section III
illustrates its use in SIMO biquadratic filter and Section IV
presents realization of tunable gain IA and its simulation
results. Finally, section V concludes the paper.
II. CIRCUIT SCHEMATIC OF CCII+ CELL
The Fig. 1(a), 1(b), and Fig. 2 show circuit symbol cum
matrix version representation, circuit schematic and block
level diagram of a second-generation current conveyor,
respectively. It uses an OTA in its input core and 2-CMOS
inverters. Its matrix representation depicts that in ideal case
VX = VY, IY = 0 and IZ = IX. It offers a good voltage
buffering action in between its Y and X terminals and very
good current buffering action in between Z and X terminals.
Due to some mismatch occurring in CMOS fabrication
ª IY º ª0 0 0 º ªVY º
« » « »« »
«VX » = «1 0 0 » « I X »
«¬ I Z »¼ «¬0 ± 1 0 »¼ «¬VZ »¼
Fig. 1(a) Circuit symbol cum matrix representation of CCII+ cell

XXX-X-XXXX-XXXX-X/XX/$XX.00 ©20XX IEEE

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 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN)

Fig. 1(b) Circuit schematic of BD-CM-OTA cum CMOS inverter-based CCII+ cell

swing. The rail side device of self-cascode load operates in

+
Vo Z
saturation region whereas its cascode device stays in ohmic
Y
OTA Inverter (linear) region and it favors low voltage operation with
í
enhanced output impedance and voltage gain [13]. The
CC output impedance at output node of OTA is given by:
Inverter ro = roP || roN (1)
X Where roP and roN are given by (2) and (3).
CC roP = g m 9 g m 10 ro 9 (2)

Fig.2. Block diagram of CMOS CCII+ cells roN = g m 7 g m 8 ro 7 (3)

process its voltage gain, Į = VX/VY may slightly differ from The voltage gain of OTA is given by:
unity. Similarly, its current gain, ȕ = IZ/IX may also slightly
deviate from ideal value of unity. AV ( OTA ) = g meff ro (4)
The output node (Vo) of OTA drives both the CMOS This BD-CMOTA provides a single ended voltage gain of
inverters see Fig. 2. The left side inverter utilizes a 100 % 56 dB and GBW of 130 kHz and stable phase margin of 78o.
negative shunt-current feedback from its output to inverting This OTA section is followed by two-CMOS inverters
input of OTA. This feedback severely reduces the composed of transistor pairs, N9 P11 and N10 P12. The Fig. 2
impedance of X node and realizes the current input terminal presents block level diagram of CCII+ cell. The Table I lists
of CCII+ cell. The right-side CMOS inverter does not use the device size and components used in CCII+ cell.
such negative feedback and offers a very high input
impedance node called Y node, suitable to drive voltage TABLE I. SIZE OF COMPONENTS USED IN CCII+ CELL
mode input signal. Name of the
W/L (μm/μm) and M
Size for WI region
Fig. 1(b) presents the overall circuit of bulk-driven CM- Device
P5, PB 5/0.75, M=1 5/2, M=1
OTA and two-inverters-based CCII+ cell. Each of its
inverter section contains Millers cum zero nulling resistor- P1, P2, P3, P4 30/0.75, M=1 30/0.75, M=1
based frequency compensation circuit comprised of series P7, P9 40/1, M=1 5/1, M = 1
connected resistance, RN and capacitance, CC. This circuit is
biased using dual power supply of ± 0.4 V and DC bias P6, P10 40/1, M=4 50/1, M = 2
current of 10 μA. Its OTA section has utilized bulk driven, P11, P12 50/1, M = 2 50/1.5, M=2
symmetric current mirror cum self-cascode load based
N2, N4, N6, N8 40/1, M = 2 50/1, M = 1
design topology. Further, the OTA’s performance is
enhanced by inserting a PPF loop made of two cross- N1, N3, N5, N7 20/1, M = 1 2.5/1, M = 1
coupled pMOS transistor named (P3, P4) which generates a
N9, N10 40/1, M=1 50/1, M=1
negative resistance in the input core of its main differential
pair pMOS transistor (P1, P2). This arrangement boosts the N11, N12 (see Fig. 30/1, M=1 30/2, M=1
transconductance of differential pair. 8)
2 x RN 2 x 30 kŸ Not used
The three self-cascode current mirrors, each of current
mirror ratio 1: 1 has been used in its OTA section. The self- 2 x C C, C L 2 x 1pF, 15 pF 2 x 1pF, 15 pF
cascode composite pair-based load invests head room Load resistors 10 kŸ each 10 kŸ each
voltage of a single device and offers high output voltage used at X, Z node

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TABLE II. SIMULATED PERFORMANCES OF OTA AND CCII+ input impedance at this node to a level of 56.7 Ÿ. This node
Region SI/WI SI WI is called X node of CCII+. There is no such negative
Parameters OTA CCII+ feedback at the output of second CMOS inverter and this
OTA CCII+
node (called Z node) offers very high output impedance of
CMOS Process (μm) 0.18 0.18 0.18 0.18 1.28 MŸ. The Y input node has offered very high input
Supply voltage ± 0.4 ± 0.4 ± 0.4 ± 0.4 impedance of 648 MŸ, (see Table II). Its current gain (IZ/IX)
Capacitive Load (pF) 15 and CC 15 and CC =
is 1.00086 and voltage gain (VX/VY) is 0.9862. The 3-dB
15 15 bandwidth of CCII+ cell is 1.18 MHz and 1.16 MHz at X
= 1pF 1pF
DC gain (dB) 0 dB at and Z node, respectively when load CL of OTA section was
56 71.5 0 dB at 1Hz
1Hz absent. The 3-dB bandwidth of CCII+ cell reduces to
3-dB bandwidth with 394, 398 at 24.2, 24.4 at 394 kHz and 398 kHz at X and Z node, respectively when
0.225 0.124
CL and RL (kHz) X, Z X, Z
3-dB bandwidth 1180, 1160 98, 101 at X, CL of 15 pF is used in OTA section. It offered high average
– – slew rate of 597 V/ms, and 454 V/ms at X and Z node,
without RL (kHz) at X, Z Z
Impedances at Y, Z
– 648, 1.28 – 155000, 1 respectively. The OTA section in SI and WI regions offered
(MŸ) gain and phase responses as shown in Fig. 3(a) and 3(b),
Impedance at X node
(Ÿ)
– 56.7 – 19.4 respectively.
Voltage gain Į, 0.9862, at 0.994, at X, III. SIMO VOLTAGE MODE BIQUADRATIC
– –
(VX/VY) X, Z Z FILTER
Current gain ȕ, (IZ/IX) – 1.00086 – 1.000033 The Fig. 4 shows the single input multiple outputs voltage
PM (deg) mode biquadratic filter [14] which utilized four numbers of
78 – 80 –
CCII+ cells, two capacitors, and five resistors as proposed in
UGF (kHz) 130 – 26 – [14]. The routine analysis of this SIMO type voltage mode
DC offset error (μV)
82
í2.6 í2.9
í2.4
í20.7, í26 at filter provides input and output relation given by:
Power dissipation
at X, Z X, Z
Vo ( s ) s 2 C1C2 G1 − s C1G1G2 + G1G2 G3
8.86 18.55 0.272 6.6 = (5)
(μW) Vin ( s ) s 2 C1C2 G1 + s C1G1G2 + G1G2 G3
CMRR (dB)(@1Hz) 71 – 129 – This filter provides LP at node VLP, BP at node VBP, all pass
PSRR+ (dB) 61.7 – 71.5 – (AP) at node VAP for (R4 = R1), HP at node VHP and band
PSRRí(dB) reject responses at node VN (see Fig. 4).
66 – 122 –
Its central frequency and quality factor are given by (6-7).
SR, average (V/ms) 597, 454 at 597, 454 at
249 6.2 ω0 = 1 C1C2 R2 R3 (6)
X, Z X, Z
THD (dB) for í42, í42 í42, í42 at
– í40
330mVpeak @1kHz) at X, Z X, Z
THD (dB) (for í49, í49 í54, í54 at
í54.6 í55
10mVpeak @1kHz) at X, Z X, Z
Input referred noise at
0.181 0.131 0.397 0.412
1 kHz (μV/¥Hz)

Fig. 4. Four-CCII+ based voltage mode SIMO Filter [14]

C2 R2 R3
Q= (7)
R1 C1
The Fig. 5 shows the AC response result of this SIMO
biquadratic multi-function filter when five equal value
resistors each of 10 kŸ and two equal value capacitors each
of 10 nF is used.
Fig. 3(a) AC gain and phase response of SI-region OTA section

Fig. 3(b) AC gain and phase response of WI-region OTA section Fig. 5. AC response of SIMO Filter
The Table III lists the corner frequencies, central or notch
The output of first inverter is fed back to inverting input of frequency and quality factor (Q) related to low-pass filter
OTA. This current shunt negative feedback reduces the (LPF), high pass filter (HPF), band pass filter (BPF), and

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band-reject filter (BRF). This SIMO filter is simulated using The Fig. 7 shows another IA (first proposed by [19]) which
all equal value resistor each of 10 kŸ and two equal value utilizes three-CCII+ cells. In this IA, the CCII2+ cell
capacitors each of 10 nF. Considering equal component- functions as negative current buffer and CCII1+ cell as
based design its theoretical quality factor is unity and positive current. The negative current IZ2 is converted to
realized quality factor is as shown in Table III. It dissipates positive current flowing out of Z3 terminal of CCII3+ cell. A
total power of 74.42 μW. If capacitor of 1 nF is used, then load resistor RL connected across the common output node
central frequency shifts to 16.2 kHz which is enough to (Z1 and Z2) and analog ground produces a single ended
process audio-range frequencies. output of two-times across this grounded load. A voltage
gain of this IA can be varied either by varying RG or RL or
TABLE III. CUT-OFF FREQUENCIES OF SIMO BIQUADRATIC FILTER both resistors. This circuit requires two-passive resistors.
AC Response Results of SIMO Filter
Filter
type Upper Corner Lower Corner Central Q
frequency fH frequency fL freq. (fo)
LPF 2010 Hz – – –

HPF – 1320 Hz – –

BPF 2500 Hz 1010 Hz 1589 Hz 1.066

BRF 1005 Hz 2640 Hz 1628.8 Hz 0.996

IV. CCII+ CELLS-BASED IA AS VGA

The high CMRR instrumentation amplifier is required to

amplify very small signal generated by transducers [15]. Fig. 7. Three-CCII+ cells based single ended output cum FD-output IA
These signals are generally buried in stray common mode having grounded load [19, 22]
noise. Recently authors have addressed some high CMRR
IA which is useful to amplify desired transduced signal The Fig. 8 shows another version of tunable gain IA which
producing very high signal to noise ratio at output node of uses an active load composed of two shunt-connected
IA [16-17]. The Fig. 6 shows two-CCII+ cells-based IA nMOS transistor pair N11 and N12. N11 is diode connected
reported by [18]. The voltage buffering action between Y and gate voltage of N12 is a varying control voltage (VG).
and X terminal sets small signal current This pair offers a variable equivalent resistor, say R which
produces a varying output voltage. Thus, the voltage gain of
of i X1 = −i X 2 = (V1 − V2 ) ( RG + RX 1
+ RX 2 ) when
this IA is adjustable by varying the gate control voltage VG
differential input V1 and V2 are applied to the IA. In this in certain specified range.
expression RX1 and RX2 are the input impedances at X1 and The major advantages of this variable gain (IA) amplifier is
X2 nodes of used CCII+ cells. The current buffering action that it does not use any passive resistance in its circuit, and
between Z and X terminal sets same small signal current in it will consume less chip area in fabrication process.
both of RL load resistances but of opposite polarity. So, two-
single ended outputs exist across the grounded load resistors
(each of value RL) given by
Vo + = −Vo − = (V1 − V2 ) RL ( RG + RX 1
)
+ RX 2 . However, if
a floating resistor be connected across Z1 and Z2 two-fold,
fully differential output is produced which increases the gain
by 6 dB as compared to single ended case. The CCII+ cells-
based IA provides 3-dB bandwidth independent of the gain
and removes the gain-bandwidth constraints [20]. Their gain
and bandwidth can be independently set by setting the value
of RL and RG, respectively [20].
Fig. 8. Two-CCII+ cells based single ended output IA having active
+ grounded load made of two-nMOS transistors [18]
Y1
v1 CCII+ Z1 VO+ The input signal is differentially applied in between X1 and
X1 Y1 terminal of CCII1+ cell. The current associated with the
RL X1 and X2 terminals is given by:

RG
i X1 = −i X 2 = (V1 − V2 ) ( RX 1
+ RX 2 ) (8)

RL Also, iZ1 = −iZ 2 = (V1 − V2 ) ( RX 1

+ RX 2 ) (9)
X2
The nMOS transistors N11 and N12 are biased in ohmic
CCII+ Z2 region and they present an equivalent resistance of, say R
v2 í
Y2 VOí across the Vo and VSS terminal [18].
Then output voltage Vo is given by:
Fig. 6. Two-CCII+ cell based single ended output cum FD-output IA
having floating load [18, 21]

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(V1 − V2 ) R The minimum to maximum gain has been varied from

Vo = (10) 34 dB to 77 dB for SI region operated CCII+ cell-based IA.
( RX 1
+ RX 2 ) However, its 3-dB bandwidth is nearly constant at a value of
Let consider ac equivalent signal model in which VSS node nearly 320 Hz. This IA has consumed a total power of
is equivalent AC signal ground, then VGS11 = Vo and VGS12 160 μW (see Table IV).
=VG. If Vo < VTH then M11 and M12 operate in ohmic
region, applying square law-based CMOS current vs voltage
relation in ohmic region the drain currents of active load
devices (M11, M12) are given by (11) and (12).
μC W
iD1 = n OX ª(Vo − VTH ) Vo − Vo2 2 º (11)
L ¬ ¼
μn COX W ª
¬( G TH ) o o ¼
iD2 = V − V V − V 2 2º (12)
L
Where parameters related notations of CMOS transistors in
(11) and (12) have their usual meanings. Let the current IZ1
flowing into active resistor to be iT then it is given in (13).
iT = iD1 + iD1 (13) Fig. 10. AC gain phase response of tunable IA
From (11), (12), and (13)
TABLE IV. OPEN LOOP GAIN VS TUNING VOLTAGE VG FOR SI-CCII +
μC W
iT = n OX ª¬(VG − 2VTH ) Vo º¼ (14) CELLS BASED IA
L Tuning voltage (VG) Open-loop gain
The equivalent active resistance, R is given by: 0.2 V 34 dB
V L
R= o = (15) 0.15 V 37 dB
iT μn COX W (VG − 2VTH )
0V 54 dB
Thus, R is dependent on gate bias control voltage VG.
Varying gate bias equivalent resistor changes and voltage í0.2 V 70 dB
gain, AV is í0.1 V 77 dB
V Vo R
AV = o = = (16)
Vi (V1 − V2 ) R X + RX ( 1 2
) The IA shown in Fig. 8 has also been simulated using
From (15) and (16) the AV becomes CCII+ cell operating in WI region. The minimum to
L maximum gain has been varied from 44.7 dB to 88.2 dB
AV = (17) with VG variation in range of ± 0.2 V. However, its 3-dB
( )
RX1 + RX 2 ¬ μn COX W (VG − 2VTH ) º¼
ª
Thus, the voltage gain of IA is tunable by varying the tuning
voltage applied to the gate of nMOS active load [18-19].
The Fig. 9 shows the extended version of IA of Fig. 8. It
uses an additional CCII+ cell3 to produce a buffered output
at node X3 of this new cell. The voltage output (Vo)
produced at Z1 node is inserted into the high impedance
node Y3. The voltage buffering action of Y and X terminal
provides a buffered output voltage (Vo1) at X terminal of
CCII3+ [18, 20]. It can drive low-impedance load.
Fig. 11. AC gain phase response of tunable IA made of WI-CCII+ cells

TABLE V. OPEN LOOP GAIN VS TUNING VOLTAGE VG FOR WI-CCII

BASED IA

Tuning voltage (VG) Open-loop gain

CCII+ Z3

0.2 V 44.7 dB

0.1 V 47.8 dB

0.05 V 50.6 dB

0V 56.4 dB

í0.05 V 65 dB
Fig. 9 Three-CCII+ cells based single ended buffered output IA having í0.1 V 84 dB
active grounded load made of two-nMOS transistors [18]
í0.15 V 88.2 dB
The Fig. 10 shows the AC gain and phase response for
varying gain IA when the gate voltage of its active
bandwidth is nearly constant at a value of nearly 340 mHz.
resistance has been varied in the range of ± 0.2 V. This IA has consumed a total power of 13.4 μW only (see

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Table V). The phase margin of this IA is found to be 55o for
gain of 88.2 dB and 87.4o at the gain of 43.7 dB.
The CMRR of weak inversion operated CCII+ cells-
based IA is 102 dB when its open loop gain is set to 88.2 dB
see Fig. 12.
Fig. 12. CMRR of tunable IA (made of WI-CCII+ cells) at its open loop
gain of 88.2 dB
The PSRR of weak inversion operated CCII+ cells-based
IA is found to be 99 dB at its open loop gain of 88.2 dB as
shown in Fig. 12. Thus, this IA has offered high CMRR and
PSRR which makes it suitable as bio-signal amplifier to
amplify bio-signal buried in noise.
Fig. 13. PSRR of tunable IA (made of WI-CCII+ cells) at its open loop gain
of 88.2 dB
V. CONCLUSION
This paper has presented the design of a CCII+ cell,
revisited a SIMO filter and some variable gain
instrumentation amplifiers. The CCII+ cell has utilized a
gain enhanced CM-OTA in its input core. The simulation
results of OTA section and CCII+ are simulated using
standard n-tub bulk 180 nm CMOS process technology. The
designed CCII+ cells are used to implement a SIMO
multifunction filter and an IA as VGA. The gain of IA is
tunable by changing a gate control voltage VG into a nMOS
transistor. This CCII+ cell and variable gain IA operating in
WI and SI regions are suitable to process biomedical as well
as audio signals, respectively.
ACKNOWLEDGMENT
This work has been simulated using Mentor Graphics,
Tanner EDA Tool of version v 16.1 utilizing 180 nm
standard n-tub bulk CMOS process technology in VLSI
Laboratory of ECE Department of NERIST, deemed to be
University, Itanagar, Arunachal Pradesh, India. Finally, the
authors declare that there is not any conflict of interest
regarding the publication of this paper.
REFERENCES
[1] Rasoul Dehghani, Design of CMOS Operational Amplifiers,Artech
House, Boston, London, 2013, pp. 86–105.
[2] P. Allen and D. Holberg, CMOS Analog Circuit Design, 3rd ed.
Oxford, U.K.: Oxford Univ. Press, 2011, pp. 302–306.
229
[3] D.M Binkley, “Tradeoffs and Optimization in Analog CMOS
Design,” John Wiley & Sons Ltd. 2008.
[4] G Chatterjee, S., Tsividis, Y., & P. Kinget, “0.5-V analog circuit
techniques and their application in OTA and filter design,” IEEE
Journal of Solid-State Circuits, Vol. 40 , No. 12, pp. 2373–2387,
2005.
[5] Blalock, B. J., Allen, P. E., & G. A. Rincon-Mora, “Designing 1-V op
amps using standard digital CMOS technology,” IEEE Transactions
Circuits Systems II: Analog and Digital Signal Processing, Vol. 45,
No. 7, pp. 769–780, 1998.
[6] Raikos G., S. Vlassis, “0.8 V bulk-driven operational amplifier,”
Analog Integr. Circ. Sig. Process vol. 63, No. 3, pp. 425–432, 2010.
[7] Wang, R., & R. Harjani, “Partial positive feedback for gain
enhancement of low-power CMOS OTAs,” Analog Integrated
Circuits and Signal Processing, Vol. 8, No 1, pp. 21–35, 1995.
[8] A. S. Sedra and K.C. Smith, “A second generation current conveyor
and its applications,” IEEE Trans. Circuit Theory Vol. 17, pp. 132–
134, February (1970).
[9] Toumazou, C., Lidgey, F. and D. Haigh, “Analogue IC Design: The
Current-Mode Approach,” 1990th ed. Edition. IEE Press, (1990).
[10] A. S. Sedra, G.W. Roberts, and F. Gohh, “The current conveyor.
History, progress and new results,” IEE Procs., Part G: Electronic
Circuits and Systems 137, pp. 78–87, (1990).
[11] Prokop, R. & V. Musil, “Current conveyor CCII as the most versatlie
analog circuit building block,” Annual Journal of Electronics, pp. 73–
76, 2009.
[12] J. W. Horng, “Voltage/current-mode universal biquadratic filter using
single CCII+,” Indian Journal of Pure and Applied Physics, Vol. 48,
pp. 749–756, 2010.
[13] S. Kundra, P. Soni, R. Naaz, “Folded cascode OTA using self cascode
technique,” Internation Journal of Scientific and Research
Publications, Vol.2, No.1, January 2012, ISSN 2250-3153.
[14] J. W. Horng, W. Y. Chiu, “High input impedance voltage-mode
biquad with one input and five outputs employing four CCII ICs,”
Indian Journal of Pure and Applied Physics, Vol. 54, pp. 577–582,
2016.
[15] M’harzi, Z., Alami, M. & Temcamani, F. Low voltage, high CMRR,
and wide bandwidth novel current mode current controlled
instrumentation amplifier. Analog Integr Circ Sig Process 90, 199–
205 (2017). https://doi.org/10.1007/s10470-016-0873-3
[16] M. A. Eldeeb, Y. H. Ghallab, Y. Ismail, Hassan El-Ghitani, “A 0.4 V
Miniature CMOS Current Mode Instrumentation Amplifier,” IEEE
Tran. On Circuit and System II: Express Brief, pp. 1-5, 2018,
DOI:10.1109/TCSII.2017.2685589.
[17] L. Safari, G. Ferri, S. Minaei, V. Stornelli, “Current-Mode
Instrumentation Amplifiers,” Analog Circuits and Signal Processing
ISBN 978-3-030-01342-4, Springer Nature Switzerland AG 2019.
[18] H. ERCAN, S. A. TEK ࡆIN, Mustafa ALCI, “Voltage-and current-
controlled high CMRR instrumentation amplifier using CMOS
current conveyors,” Turk J Elec Eng & Comp Sci, Vol. 20, No.4, pp.
x-y, 2012.
[19] Leila Safari, Shahram Minaei, “A Novel Super Transistor-Based
High-Performance CCII and Its applications,” ELEKTRONIKA IR
ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 24, NO. 2, 2018.
[20] R. Senani, D. R. Bhaskar, A. K. Singh, “Current Conveyors Variants,
Applications and hardware Implementations,” Springer, New York,
2015.
[21] B. Wilson, “Universal conveyor instrumentation amplifier,” Electron
Letter, Vol.,25, pp. 470–471, 1989.
[22] Khan AA, Al-Turaigi MA, El-Ela MA, “An improved current-mode
instrumentation amplifier with bandwidth independent of gain,” IEEE
Trans. Instrum. Meas. 44, 1995.