Microelectronics Journal 92 (2019) 104606

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A 0.25-V fifth-order Butterworth low-pass filter based on fully differential

difference transconductance amplifier architecture
Paulo M. Pinto, Luís H.C. Ferreira ∗ , Gustavo D. Colletta, Rodrigo A.S. Braga
Institute of Systems Engineering and Information Technology, Federal University of Itajubá, Itajubá, 37500-903, Brazil

A R T I C L E I N F O A B S T R A C T

Keywords: This paper presents a fifth-order Butterworth low-pass filter based on the fully differential difference transcon-
Fifth-order Butterworth filter ductance amplifier (FDDTA) building blocks. At first, the FDDTA has been stated and its operation has been
Weak inversion
evaluated. Then, a practical implementation using two fully differential inverter-based operational transconduc-
Analog filtering
tance amplifiers (OTA) was investigated. This particular FDDTA implementation relies on two main features:
Fully differential difference transconductance
amplifier
the intrinsically matched transistors that assure similar transconductances and output conductances for both
Ultra-low-voltage and ultra-low-power circuits inverter-based OTA instances; and the inverter-based approach without internal nodes that reduces circuit com-
and applications plexity and power consumption since it requires no supplementary external calibration circuit such as tail current
or bias voltage sources. Finally, the filter architecture, which consists of one inverter-based OTA input stage and
five FDDTAs in a cascade connection has been evaluated, showing that it presents the expected fifth-order trans-
fer function according to the Butterworth theory. The prototypes, implemented in a 130 nm CMOS process,
operate in weak inversion supplied with 0.25 V and consumes 603 nW. Furthermore, they feature a DR of 57 dB
in a 100 Hz bandwidth and a maximum THD of 54 dB, therefore, accomplishing specifications that suit for
low-frequency applications.

1. Introduction
Nowadays, practical Butterworth filter implementations target the
analog front-ends (AFE) for wearable biomedical applications, like ECG
monitors, where they are used as anti-aliasing filters [1–3]. Modern
AFEs are mobile devices that communicate wirelessly to a smartphone
or cloud services, and therefore they require low power circuit solutions
[4–7].
Regarding the system on chip (SoC) solutions, the main strategy
to save power relies on reducing the number of active elements in
the Gm -C Butterworth filter implementations. In general, the conven-
tional transconductor element based on the operational transconduc-
tance amplifier (OTA) has been replaced by the fully differential differ-
ence transconductance amplifiers (FDDTA) [8–10]. Moreover [9,10],
operate in weak inversion to reduce power consumption, but they
require a triple well CMOS process and controller circuits to stabilize
and tune the transconductance of the transconductor building block.
The FDDTA is a six-terminal device that comprises two differential
voltage input ports which converts them into a differential current
output stage. Since they are intended to build Gm -C filters, a high
linear and low transconductance, and a high output impedance are the
main requirements. Moreover, some FDDTAs implementations using
uniform transistors operating in strong inversion have been reported
in Ref. [11], while a floating gate (FG) transistor implementation
operating with a reduced supply voltage was reported in Ref. [12],
and a quasi-floating gate (QFG) transistor implementation has been
reported in Ref. [13].
Although we can see significant improvement in the FDDTA archi-
tectures over the years, they still require controller circuits to stabi-
lize or tune the transconductance, and therefore they consume more
power.
Regarding this scenario, we propose a low complexity circuit imple-
mentation of a fifth-order anti-aliasing Butterworth filter that also relies
on a particular implementation of the FDDTA. Since our filter does
not require tuning, the FDDTA implementation uses two intrinsically
matched inverter-based transconductors without external circuit for
common mode control or tuning. Therefore the whole filter benefits
of power savings.

∗ Corresponding author.
E-mail addresses: pmarcos@unifei.edu.br (P.M. Pinto), luis@unifei.edu.br (L.H.C. Ferreira), gustavo.colletta@unifei.edu.br (G.D. Colletta), rodrigobraga@unifei.
edu.br (R.A.S. Braga).

https://doi.org/10.1016/j.mejo.2019.104606
Received 6 June 2019; Received in revised form 4 August 2019; Accepted 22 August 2019
Available online 29 August 2019
0026-2692/© 2019 Elsevier Ltd. All rights reserved.
P.M. Pinto et al.
The remainder of this manuscript is organized as follows: Section 2
states the FDDTA building block operation and implementation. Section
3 provides the proposed fifth-order Butterworth low-pass filter archi-
tecture. The circuit characterization and discussions are presented in
Section 4. Section 5 concludes our contributions.
2. The fully differential difference transconductance amplifier
This section describes the operation and implementation of the
FDDTA that we use as a building block to accomplish the fifth-order
Butterworth filter. Furthermore, it explains the reasons that make the
inverter-based transconductor reported in Ref. [14] a good candidate
to implement the FDDTA.
The FDDTA, illustrated in Fig. 1a, is a six-terminal device that
comprises two differential voltage input ports, (Vpp − Vpn ) and
(Vnp − Vnn ) which converts the two differential voltages into a differ-
ential current output stage (Iop − Ion ). Operating in the linear range,
the output is
Iop − Ion = Gm [(Vpp − Vpn ) − (Vnp − Vnn )] ,
where Gm states the FDDTA transconductance.
In this sense, we propose to implement the FDDTA architecture,
illustrated in Fig. 1b, in terms of two fully differential OTA instances
operating in weak inversion with short circuit outputs.
In addition, we can apply two small differential signals (vid1 , vid2 ) to
the FDDTA inputs according to
vid1 vid1
Vpp = VCM + , Vpn = VCM − ; (2a)
2 2
and
vid2 vid2
Vnp = VCM + , Vnn = VCM − , (2b)
2 2
where VCM is the common-mode voltage.
Moreover, the small-signal AC model, illustrated in Fig. 1c, shows
that the differential output voltage is
Gm1 vid1 (s) − Gm2 vid2 (s)
vod (s) = , (3)
(CP1 + CP2 )s + Go1 + Go2
where Gm stands for the OTA transconductance while CP and Go stand
for the OTA output (parasitic) capacitance and output conductance,
respectively, per each single-ended output branch. Assuming two iden-
tical matched OTAs, Gm1 = Gm2 = Gm , CP1 = CP2 = CP and Go1 = Go2 =
Go , leads to the output voltage,
vod (s) Gm
= ,
vid1 (s) − vid2 (s) 2CP s + 2Go
showing that the FDDTA features the same transconductance of a sin-
gle OTA and an increased output admittance. For low frequencies, the
differential output current, iod = iop − ion , can be given by
iod = Gm (vid1 − vid2 ),
showing that the differential current in terms of the original input sig-
nals, Vpp , Vpn , Vnp , and Vnn leads to (1); hence testifying the FDDTA
operation.
Although we can pick any fully differential transconductor to imple-
ment the FDDTA block illustrated in Fig. 1b, our choice relies on the
inverter-based OTA that we previously reported in Ref. [14], since it
operates in weak inversion with a power supply of 0.25 V and requires
no supplementary external calibration circuits, and therefore saves
power. In addition, it uses the design technique of distributed layout
transistors that matches all the base inverters, enabling an efficient
(low-complexity) approach to improve the common-mode voltage con-
trol.
All unity pMOS and nMOS transistors within the distributed lay-
out have their aspect ratio (W∕L) equal to (2.0 μm/2.0 μm) and
Microelectronics Journal 92 (2019) 104606
(0.4 μm/0.6 μm), enabling threshold voltages of 230 mV and 190 mV
respectively.
Furthermore, its intrinsically matched feature assures the same
transconductance and output impedance to both OTA instances; hence
simplifying the FDDTA overall design. For your convenience, we
reprinted the inverter-based OTA in Fig. 1d and the performance bench-
marks in Table 1.
The inverter-based OTA features a high-linear and low transconduc-
tance of 2.46 μS, which is mandatory for Gm -C applications. In addition,
the power consumption of 55 nW is appropriate for low-power applica-
tions.
Since the inverter-based OTA presents no internal nodes, the invert-
ers Inv3, Inv4, Inv5, and Inv6 of both OTA instances are connected in
parallel when we short circuit the outputs of the two OTA instances.
Fig. 1e shows that the parallel connected inverters, in fact, act as single
inverters with doubled aspect ratios, and therefore simplify the overall
circuit.
In summary, the proposed FDDTA architecture adds two input
inverters to the OTA architecture and doubles the aspect ratios of the
(1) inverters Inv3, Inv4, Inv5, and Inv6, still keeping the low-complexity
approach to control the common mode voltage. Moreover, since the
proposed FDDTA architecture requires no additional voltage drops it
still operates supplied with 0.25 V.
In fact, a similar transconductor has been reported in Refs. [9,10],
where simulations validated its use in applications of radio-frequency
communications such as Zigbee and Bluetooth. It is constructed in a
triple well CMOS process that enables to stabilize and tune the transcon-
ductance through the bulk of the transistors. Although it operates in
weak inversion it still requires a controller circuit and therefore con-
sumes additional power.
Since low-frequency anti-aliasing filters, in general, do not require
tuning, our approach relies on a digital CMOS process with transistors
that features reduced threshold voltages and smaller channel lengths.
Thereby, our transconductor can operate in weak inversion at a reduced
supply voltage of 0.25 V. In addition, the distributed layout technique
assures a stable transconductance, eliminating the controller circuit,
and therefore saving power.
3. Proposed fifth-order Butterworth filter
This section details our proposed fifth-order Butterworth filter archi-
tecture built with the FDDTA blocks. Furthermore, we carried a circuit
analysis showing that we can, in fact, accomplish a fifth-order Butter-
worth filter by setting the appropriate values to some parameters.
Feasible implementation of a low-pass filter may rely on the Butter-
(4)
worth theory [15], that shows an m-order low-pass filter design accord-
ing to
T0
T (s ) = ( ) , (6)
Bm 𝜔s
c
(5) where 𝜔c is the cutoff frequency and T0 is the DC gain. The polynomials
are normalized by setting 𝜔c = 1, therefore presenting the form of
∏[ (
2k + m − 1
) ]
Bm (s) = (s + 1) s2 − 2s cos 𝜋 + 1 , m = odd. (7)
2m
k
where, for a normalized fifth-order Butterworth polynomial, the coeffi-
cients are
B5 (s) = (s + 1)(s2 + 0.6180s + 1)(s2 + 1.6180s + 1) , (8)
showing that there is one pole located at 0◦ and that the others are
apart by multiples of 36◦ [15].
The conventional fifth-order Butterworth low-pass Gm -C filter imple-
mentation, depicted in Fig. 2a, shows that it requires eleven transcon-
ductors properly connected. Our approach intends to reduce the num-
ber of circuit elements by replacing the highlighted transconductors
2
P.M. Pinto et al. Microelectronics Journal 92 (2019) 104606

Fig. 1. The FDDTA block: symbol and implementation.

by the FDDTA building block, since the differential outputs of those and OTA2b, OTA3a and OTA3b, OTA4a and OTA4b, and OTA5a and
transconductors are connected in short circuit, in the same fashion of OTA5b are replaced by five FDDTA instances. Thereby, the proposed
the FDDTA block. Therefore, the instances OTA1a and OTA1b, OTA2a filter architecture, depicted in Fig. 2b, comprises one inverter-based

3
P.M. Pinto et al. Microelectronics Journal 92 (2019) 104606

Table 1 And finally, assuming C5 ≫ CP , the fifth FDDTA (FDDTA5) transfer

Summary of inverter-based OTA performance [14]. function is
Parameter Value vop (s) − von (s) Gm
= . (13)
Technology 130-nm [von (s) − von4 (s)] − [vop (s) − vop4 (s)] 2sC5 + 2Go
Power supply 0.25-V
Transconductance 2.46-μS Manipulating (9), (10), (11), (12) and (13), give us the transfer func-
Output conductance 56.73-nS tion of the complete architecture according to
Open loop gain 24.92-dB
Output (parasitic) capacitance 13.4-pF
√ vod (s) G5m
T (s ) = = 5 , (14)
White noise floor 139-nVrms ∕ Hz vid (s) 𝛼 s + 𝛽 s + 𝛾 s3 + 𝛿 s2 + 𝜖 s + 𝜃
4
Linear input range HD3 ≤ 0.1% 18.8-mVpk @10-Hz
Offset voltage ≤0.78-mV where vid (s) = vip (s) − vin (s) and vod (s) = vop (s) − von (s). Table 2
Power consumption 54.75-nW summarizes the coefficients values. Note that, all coefficient values
(𝛼, 𝛽, 𝛾, 𝛿 and 𝜖 ) rely on the constant values C1 , C2 , C3 , C4 , C5 , Go ,
and Gm . It means that we can accomplish the fifth-order Butter-
worth filter stated in (6) by choosing appropriate values for the
OTA input stage (OTA1 ) and five FDDTAs stages (FDDTA1 -FDDTA5 ) capacitance, conductance, and transconductance parameters. In addi-
associated in a cascaded connection. tion, the open loop gain is -6dB when Gm > Go , because T (0) =
Assuming C1 ≫ CP , the transfer function of the first FDDTA stage G5m ∕𝜃 ≈ 1∕2. Moreover, Fig. 3 shows the location of the poles for
(FDDTA1 ), including the OTA input stage (OTA1 ), is the transfer function with a Butterworth response, where each pole
lies along a semicircle in the left half-plane and are spaced at
vop1 (s) − von1 (s) Gm equal angular distances, as required by (8) to be a Butterworth
= .
[vip (s) − vin (s)] + [von2 (s) − vop1 (s)] − [vop2 (s) − von1 (s)] 2sC1 + 3Go filter.

(9)
4. Measurements and results
Assuming C2 ≫ CP , the transfer function of the second FDDTA
stage (FDDTA2 ) is Fig. 4 shows the micrograph of the fabricated circuit obtained
with Cascade Microtech MPS150 Probe Station where the layout
vop2 (s) − von2 (s) Gm is overlaid for better visualization. Our current layout for the
= . (10)
[von3 (s) − von1 (s)] − [vop3 (s) − vop1 (s)] 2sC2 + 2Go proposed fifth-order Butterworth filter architecture, actually, reuses
the layouts of the OTA circuit that we have previously published
Assuming C3 ≫ CP , the transfer function for the third FDDTA in Ref. [14].
(FDDTA3) is We have interconnected the OTAs to build the FDDTAs build-
vop3 (s) − von3 (s) ing blocks, then we made a cascade connection of the FDDTAs,
Gm
= . (11) leading to the proposed filter architecture. For measurement conve-
[von4 (s) − von2 (s)] − [vop4 (s) − vop2 (s)] 2sC3 + 2Go
nience, we used external capacitors within the commercial range.
Assuming C4 ≫ CP , the fourth FDDTA (FDDTA4) features the The whole architecture has been simulated in the Spectre simulator
transfer function according to, using BSIM4 models and implemented using the GF 130-nm CMOS
process.
vop4 (s) − von4 (s) Gm Fig. 5a shows the measured frequency response of the fifth-order
= . (12)
[von (s) − von3 (s)] − [vop (s) − vop3 (s)] 2sC4 + 2Go Butterworth filter taken with the Keysight 35670A Dynamic Signal Ana-

Fig. 2. Fifth-order Butterworth low-pass filter implementations.

4
P.M. Pinto et al. Microelectronics Journal 92 (2019) 104606

Table 2
Coefficients values of the filter transfer function.
Coefficient Value
𝛼 32C1 C2 C3 C4 C5
𝛽 16Gm [C1 C2 C3 C4 + C2 C3 C4 C5 ] + 16Go [2C1 C2 C3 C4 + 2C1 C2 C3 C5 + 2C1 C2 C4 C5 + 2C1 C3 C4 C5 + 3C2 C3 C4 C5 ]
𝛾 8G2m [C1 C2 C3 + C1 C2 C5 + C1 C4 C5 + C2 C3 C4 + C3 C4 C5 ] + 16G2o [2C1 C2 C3 + 2C1 C2 C4 + 2C1 C2 C5 + 2C1 C3 C4 + 2C1 C3 C5 + 2C1 C4 C5 +
3C2 C3 C4 + 3C2 C3 C5 + 3C2 C4 C5 + 3C3 C4 C5 ] + 8Go Gm [2C1 C2 C3 + 2C1 C2 C4 + 2C1 C3 C4 + 5C2 C3 C4 + 2C3 C4 C5 + 2C2 C3 C5 + 2C2 C4 C5 ]
𝛿 4G3m [C1 C2 + C2 C3 + C2 C5 + C3 C4 + C1 C4 + C4 C5 ] + 4Go G2m [4C1 C2 + 2C1 C3 + 4C1 C5 + 5C2 C3 + 3C2 C5 + 2C2 C4 + 2C1 C4 + 5C4 C5 +
4C3 C4 + 2C3 C5 ] + 8G2o Gm [2C1 C2 + 2C1 C3 + 5C2 C3 + 2C1 C4 + 5C2 C4 + 2C2 C5 + 5C3 C4 + 2C3 C5 + 2C4 C5 ] + 16G3o [2C1 C2 + 2C1 C3 +
2C1 C4 + 2C1 C5 + 3C2 C3 + 3C2 C4 + 3C2 C5 + 3C3 C4 + 3C3 C5 + 3C4 C5 ]
𝜖 2G4m [C1 + C2 + C3 + C4 + C5 ] + 2Go G3m [4C1 + 7C2 + 4C3 + 7C4 + 4C5 ] + 4G2o G2m [6C1 + 8C2 + 7C3 + 7C4 + 8C5 ] + 8G3o Gm [2C1 + 5C2 +
5C3 + 5C4 + 2C5 ] + 16G4o [2C1 + 3C2 + 3C3 + 3C4 + 3C5 ]
𝜃 48G5o + 40G4o Gm + 52G3o G2m + 28G2o G3m + 11Go G4m + 2G5m

Fig. 3. The pole plot of the filter transfer function.

Fig. 4. Circuit micrograph overlayed with layout.

Fig. 5. Fifth-order Butterworth measurements.

lyzer. In addition, it also shows the ideal simulation (dashed line) for
reference. Using C1 = C5 = 1 nF, C2 = C4 = 2.7 nF, and C3 = 3.3 nF
we can set the cut-off frequency to 100-Hz which is compliant to
biomedical applications. Although we have ranged the differential input
with the amplitudes of 14.2 mVpk , 28.4 mVpk , and 42.6 mVpk , the cir-
cuit keeps the low-pass characteristic with a 100 dB/dec roll-off. There-
fore, our proposed circuit, in fact, performs a fifth-order Butterworth
filter.
Some minor divergences around 100 Hz in both magnitude and
phase are due to the tolerance of 20% of the external capacitors. Above
350 Hz the signal amplitude is attenuated outside the instrument mea-

5
P.M. Pinto et al.
Fig. 6. Fifth-order Butterworth Monte Carlo analysis.
surement range, and therefore some measurement fails occurs. For
instance, at 350 Hz the attenuation is – 60 dB, which represents 14
μVpk for a given input of 14 mVpk . Since the resolution of the Keysight
Fig. 7. Fifth-order Butterworth noise and signal analysis.
6
Microelectronics Journal 92 (2019) 104606
35670 A Dynamic Signal Analyzer is 250 μVpk , the measurements above
350 Hz are not reliable.
We also have evaluated the dynamic performance of the pro-
posed Butterworth filter by carrying an FFT analysis using the 35670A
Dynamic Signal Analyzer. Fig. 5b shows the measured output spec-
trum with 31.25 mHz resolution where a 125 mV common mode
voltage was applied to both inputs with three differential sinusoidal
signals of 10 Hz and amplitudes of ±14.2 mVpk , ±28.4 mVpk , and
±42.6 mVpk at each time. Increasing the amplitude of the input volt-
age enables us to investigate the second and third harmonic distor-
tions. In both scenarios the THD, closer to HD3 , reveals a controlled
HD2 .
Since we use an intrinsically matched FDDTA building block, we
expect the fifth-order Butterworth filter presents the same feature.
Therefore, we conducted some Monte Carlo simulation to validate this
feature by evaluating the THD and HD2 distribution due to mismatch
variation. Fig. 6a shows the 1000 runs Monte Carlo simulation for
THD regarding the three input voltages of 14.2 mVpk , 28.4 mVpk , and
42.6 mVpk . In addition, process, power supply, and temperature are
in the typical range. Increasing the input voltage leads to increases
in the THD as expected. Furthermore, the THD spreads over a 6 dB
range within 99.74% of confidence regarding the worst spread scenario
(14.2 mVpk ).
Fig. 6b shows the 1000 runs Monte Carlo simulation for HD2 regard-
ing the same three input voltages and the same process, power sup-
ply, and temperature conditions. Increasing the input voltage leads
to a minor increase in the HD2 ; hence, showing that HD2 is under
control. In addition, the HD2 features practically the same distri-
bution for the three input voltages, highlighting that it is under
control.
In summary, the Monte Carlo simulations validate the intrinsically
matched feature of the fifth-order Butterworth filter, once the HD2 is
low and under control.
The measured power spectral density of input-referred noise is illus-
trated in Fig. 7a. Integrating the in-band noise from 62.5 mHz to
100 Hz provides an input-referred noise voltage value of 4.7 μVrms .
Fig. 7b depicts the relationship between the differential input range
and the signal-to-noise and distortion ratio (SINAD) of the filter. The
frequency of the input signal is fixed at 10 Hz. The dynamic range
is 57 dB under a 0.25-V power supply. Table 3 shows a performance
comparison between this work and other low-voltage Butterworth
filter where our proposed architecture features one of the smallest
THDs and high DR within the hundreds of nW range, operating under
0.25 V. Moreover, the proposed filter presents the lowest input referred
noise.
P.M. Pinto et al. Microelectronics Journal 92 (2019) 104606

5. Conclusion

TBioCAS 2009 [21]

Fully Differential
This paper presents a fifth-order Butterworth low-pass filter archi-

Butterworth

300-μVrms
0.13 mm2
tecture which relies on the FDDTA building block. Since the FDDTA

90.6-nW
453-nW

48.6-dB
50.0-dB
180-nm

250-Hz
1.0-V
building block is intrinsically matched, the proposed Butterworth fil-

OTA
ter requires no supplementary external calibration circuit, such as

5
tail current or bias voltage sources, and therefore reduces circuit
TBioCAS 2013 [20]

complexity.
The prototypes, implemented in a 130 nm CMOS process, operate
Butterworth

Differential
in weak inversion supplied with 0.25 V and consumes 603 nW. Fur-
0.11 mm2

31-μVrms
3.75-nW

55.2-dB
66.7-dB
350-nm

100-Hz
15-nW
thermore, they feature a DR of 57 dB in a 100 Hz bandwidth and a
3.0-V
SSF

maximum THD of 54 dB; hence accomplishing specifications that suits

4

for low-frequency applications.

Springer 2013a [10]

Fully Differential

43.84–43.67-dB
Acknowledgment

MODI-OTA: multiple-output differential-input – operational transconductance amplifier. DDA: differential difference amplifier. SSF: subthreshold-source-follower.
69–90-μVrms
Butterworth

2.77-mW

1–2-MHz

This work was supported in part by the Brazilian National Council

230-μW
130-nm

FDDTA

0.5-V

for Scientific and Technological Development (PQ 303090/2018-9 and

12

GD 140929/2017-7) and FAPEMIG. The authors would like to thank

MOSIS for the chip fabrication.
TCAS II 2017 [19]

Fully-Differential
Butterworth

0.21 mm2

1.35-mW
8.07-mW

65-MHz
180-nm

Appendix A. Supplementary data

1.8-V
DDA
6

–
–
–

Supplementary data to this article can be found online at https://

doi.org/10.1016/j.mejo.2019.104606.
0.09–1.96-MHz
MEJ 2018 [18]

1.6–2.1-mW
Butterworth

Differential

0.35 mm2

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