2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi,

UAE

A Chopper Capacitive Feedback Instrumentation

Amplifier with Input Impedance Boosting Technique

Mohamed Saad Mohamed El-Nozahi and Hani Ragai

Deep Sub Micron Division Electronics and Communication Engineering Department
Mentor Graphics Corporation Ain Shams University, Cairo, Egypt
E-mail: mohamed saad@mentor.com E-mail: {mohamed elnozahi, hani ragaai}@eng.asu.edu.eg

Abstract—A chopper capacitive feedback instrumentation am-

plifier (CCFIA) with proposed input impedance boosting tech-
nique is presented. Using a negative capacitance circuit, the
proposed boosting technique achieves higher input impedance
across frequency when compared to traditional approaches with-
out injecting current back to a biopotential electrode attached
to human body. Moreover, boosting the input impedance is at
no expense of the input referred noise of the CCFIA. A ripple
reduction loop (RRL) is employed for suppressing the output
chopping ripples. Also, a DC servo loop is designed for filtering
out the electrode DC offset. Simulation results, using UMC 65
nm CMOS technology, demonstrate that the proposed input
impedance boosting technique achieves much higher than 2 GΩ
input impedance. In addition, the maximum input referred ripple
is less than 1 µV. The CCFIA can tolerate up to 20 mV of electrode
DC offset. The overall√CCFIA achieves an input referred noise Fig. 1: Schematic diagram of proposed CCFIA with input
PSD equals to 35 nV / Hz and bandwidth equals to 450 Hz with impedance boosting
supply voltage equals to 1.2 V.

I. I NTRODUCTION
Signal conditioning circuits for biomedical applications
require high input impedance to avoid signal attenuation and
measurement errors due to generated offset currents with
various biopotential electrodes [1]-[6]. These electrodes can
be modeled as a nano-Farad capacitor in parallel with a
resistance typically in the mega-Ohm range. The capacitor
forms an undesired parasitic high pass pole in the signal path.
Also, the electrode resistance accompanied with conditioning
circuit of low input impedance attenuates the input signal [1].
To maintain undegraded signal to noise ratio, the chopper
capacitive feedback instrumentation amplifier (CCFIA) must
have high input impedance which is typically in the range
of giga-Ohms. Moreover, chopping stabilization technique is
applied to mitigate the in band 1/f noise as well as the DC
offset of the CCFIA circuits.
Capacitive feedback instrumentation amplifiers (IA) are
widely used more than current feedback ones to realize a com-
pact IA. The capacitive feedback architectures are character-
ized by optimum noise efficiency as their noise is dominated by
that of the input transconductance. However, current feedback
architectures require input and feedback transconductance with
current branches limiting their power efficiency along with in-
creasing the noise floor. Capacitive feedback architectures have
high gain accuracy limited by the matched input and feedback
capacitors. In counter to gain accuracy of current feedback
architectures limited by high mismatches between input and
feedback transconductances [2]. However, both approaches
suffer from low input impedance arising from the switched
capacitor (SC) resistor formed by the input chopper and input
or parasitic capacitances [2], [3]. In this case, the conventional
input impedance is expressed as Zin,con = 1/2fch Cin where
fch is the chopping frequency and Cin is the input capacitance.
Reducing Cin for boosting the input impedance results in
higher amplitude of the output chopping ripples and increases
the input referred noise of the CCFIA. While reducing fch is
governed by the 1/f noise corner frequency and also increases
the amplitude of the output chopping ripples [2].
Several techniques have been proposed to boost the input
impedance of the CCFIA. An off-chip coupling capacitor
placed at the input of the CCFIA results in a high input
impedance. However, this technique fails in fully integrated
low cost and multi channel solutions. In [4], moving the input
chopper to the virtual ground node after the input capacitor
boosts the input impedance. However, the common mode
rejection ratio (CMRR) is degraded due to unmodulated input
capacitor mismatches. Active and passive partially positive
feedback loops were proposed in [2] and [5] to supply current
back to the signal source compensating the current drawn from
it thus boosting the input impedance. However, it is difficult to
realize such loops because their capacitors are very sensitive
to parasitics. Thus, various tuning techniques for achieving
high input impedance are required. Moreover, the compensated
signal source may be a biopotential electrode attached to

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 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE

human body that is impossible to inject current through it.

In addition, passive positive feedback loops are nonfunctional
at DC. In this paper, a proposed input impedance boosting
technique is introduced. The proposed technique is based on
a negative capacitance circuit to boost the input impedance of
CCFIA. The paper is organized as follows: In Section II, the
CCFIA architecture along with the proposed input impedance
boosting technique are introduced. The circuit implementation
is discussed in Section III. Simulation results are presented in
Section IV prior to the conclusion in Section V.

II. CCFIA A RCHITECTURE

The basic topology of the proposed CCFIA, shown in Fig. 2: (a) Conventional input impedance, (b) Boosted input
Fig. 1, is similar to the one in [2] without including the impedance, (c) Circuit schematic of proposed negative capac-
input impedance boosting block. The topology is based on itance circuit
a capacitive feedback loop built around two stage Miller-
compensated operational transconductance amplifiers (OTA).
This OTA is composed of an input transconductance (GM1 )
and an integrator built around an output stage (GM2 ). The
input signal is initially modulated to fch , then demodulated
back to DC and simultaneously modulating the in band 1/f
noise and DC offset that are filtered by GM2 integrator. The
DC common mode voltage (Vcm ) for GM1 is biased through a
pair of back to back diodes (D1−4 ) clamping Vcm to reference
voltage in case of large input transients. The small signal gain
of the CCFIA is approximately equal to the ratio Cin /Cf b .
The high open loop gain of the two stage OTA is beneficial
in achieving high gain accuracy. The total input referred noise
of the CCFIA is dominated by that of GM1 . While the 1/f
noise and DC offset of GM2 is significantly attenuated by the
gain of GM1 . Fig. 3: Schematic diagram of RRL

A. Proposed Input Impedance Boosting Technique

As mentioned in Section I, the CCFIA suffers from low
input impedance arising from the SC resistor formed by the
input chopper and Cin as shown in Fig. 2(a) [2]. Generating
a negative capacitance (Cneg ) equals and parallel to the input
positive capacitance Cin1,2 at the nodes (X) and (Y ) results a
total zero capacitance. Therefore, an infinite input impedance
can be achieved in ideal situation of total zero capacitance. An
additional blocking capacitor (Cb1,2 ) is placed in series with
the circuit generating the negative capacitance to prevent any
DC current from backward injection to the signal source as
shown in Fig. 2(b). The total impedance (Zx,y ) at nodes X
and Y , shown in Fig. 2(b), can be formulated as
Zx,y = Zin //(Zb + Zneg1,2 )
where Zin =1/sCin , Zb =1/sCb and Zneg1,2 represent the total
output impedance of the active circuit generating a negative
capacitance. According to the input impedance boosting tech-
nique, the RHS of (2) must be designed to zero capacitance
magnitude, therefore achieving maximum input impedance. It
is important to mention that the proposed input impedance
boosting technique does not add noise to the total input referred
noise as will be presented in Section III.
B. Ripple Reduction Loop (RRL)
The traditional drawback of the chopping stabilization
technique is the generation of high amplitude voltage ripples
at the output of the CCFIA due to up modulated offset and
1/f noise. The amplitude of these chopping ripples is also
directly proportional to the transconductance of GM1 . The
presence of such chopping ripples would consume the output
voltage headroom. This is problematic in low voltage supply
applications. Therefore, a RRL is required to significantly
suppress the chopping ripples. The topology of the RRL,
shown in Fig. 3, is similar to the one in [2]. It is composed of
bypass capacitors converting the high amplitude voltage ripples
at the CCFIA output to AC current equals to Cbp (dVripple /dT )
that is demodulated back to DC. The demodulated current is
continuously integrated by the integrator built through (GM3 )
and (Ci ). The integrator output voltage is converted again by
(1)
(GM4 ) into a current compensating GM1 offset current until
the output of the CCFIA is ripple free at steady state. The
ripples are suppressed by a factor equal to the RRL gain.
C. DC Servo Loop
The sensing electrode adds DC offset in the range of tens
of millivolts to the input signal which can easily saturate the
CCFIA. Minimizing the gain of the CCFIA is not an option
because of very low amplitudes of the input signal which
necessitate a high gain from the CCFIA. Therefore, a DC
servo loop is required for filtering the electrode DC offset.
The topology of the DC servo loop, shown in Fig. 1, is similar
to the one in [6]. It employs a large time constant integrator

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 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE
Fig. 4: Circuit schematic of GM1 , GM2 and CMFB
built around (GM5 ) for extracting the DC component from
the CCFIA output. The following chopper modulates the DC
output of the integrator and the capacitors (Chp1,2 ) feed up
the modulated voltage to the input of GM1 . The output of
the CCFIA is continuously integrated until it is DC free. The
maximum electrode DC offset voltage that the CCFIA can
tolerate is governed by the ratio (Cin1,2 /Chp1,2 ) for maximum
output voltage equals to VDD . The time constant of the DC
servo loop integrator defines the high pass corner of the CCFIA
gain. The main challenge facing the DC servo loops is realizing
this very large time constant integrator because of very low
high pass cut-off frequency required for filtering out the DC
offset. In manner similar to [6], a duty cycled resistor is used to
implement very large resistors on chip. The resultant resistance
value is inversely proportional to the duty cycle.
III. C IRCUIT I MPLEMENTATION
As shown in Fig. 4, GM1 is implemented as a folded
cascode OTA with PMOS input transistors to lower 1/f noise.
GM2 is implemented as common source output stage for large
output swing with Miller compensation capacitor equals to 1
pF [2]. A resistive common mode sensing network for the high
impedance nodes at the outputs of GM2 is employed using
large resistors (Rcm1,2 ). Those resistors are implemented as
complementary sub-threshold transistors for maintaining the
large output swing. A common mode feedback (CMFB) OTA
then equates the DC common mode voltage of GM2 to VDD /2.
In this design, fch equals to 5 kHz which exceeds the 1/f noise
corner frequency of GM1 . Cin and Cf b are equal to 10 pF and
100 fF, respectively. Metal-Oxide-Metal (MOM) capacitors are
employed in implementing all capacitors to benefit from their
high capacitance density.
The proposed active circuit generating a negative capac-
itance is realized, as shown in Fig. 2(c), through a positive
feedback loop formed of cross coupled transistors (M1 ,M2 )
and a capacitor (C1 ). To avoid saturation due to possible
current mismatches with high impedance nodes at the drains of
M1,2 , a CMFB OTA with parallel input transistors adjusts these
nodes to VDD /2 where no AC swing is required at such high
impedance nodes. The total differential impedance (Zneg1,2 )
at the drains of M1 & M2 is approximated to
2 1
Zneg1,2 = −( + )
Gm1,2 sC1
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where (Gm1,2 ) is the transconductance of M1 & M2 . As
depicted by (3), the negative capacitance term (−1/sC1 ) nulls
the total positive capacitance at nodes X and Y as discussed
earlier. While the negative resistive term (−2/Gm1,2 ) is tuned
to cancel the positive output resistance of M3,4 and M5,6 . The
boosted input impedance (Zin,b ) is given by
1
Zin,b = (3)
2Cb1,2 C1
2fch (Cin1,2 − Cb1,2 −2C1
)
Equation (4) points out that the input impedance can be signif-
icantly boosted by enforcing Cin1,2 =(2Cb1,2 C1 /Cb1,2 − 2C1 ).
In this implementation, C1 and Cb are chosen to be 1 pF and
2.5 pF, respectively, for Cin equals to 10 pF. The required
capacitance value of C1 to equate the total positive capacitance
value is significantly relaxed in the presence of Cb1,2 . Thus,
minimum area overhead of 35% for the input impedance
boosting technique is required.
It is important to prove that the proposed input impedance
boosting technique does not add noise to the total input referred
noise. Because of the noise current (i2n ) of M1,2 , dominant
noise contributors, circulates only in the loop formed between
M1,2 and their low resistance (1/Gm1,2 ). Therefore, i2n can not
navigate to nodes X and Y as it will be always blocked by
high input impedance. Realizing the DC servo loop, the clock
signal frequency of the duty cycled resistor is 25 kHz with
duty cycle equals to 1/20000 [6]. The on chip resistor value
equals to 2.5 MΩ. While the integrating capacitor (Ci1,2 ) and
Chp1,2 are 5 pF and 200 fF, respectively.
IV. S IMULATION R ESULTS
The CCFIA is simulated using UMC 65 nm CMOS tech-
nology. The CCFIA consumes 25 µA from supply voltage
(VDD ) equals to 1.2 V. Fig. 5 shows the input impedance
across frequency with and without applying the boosting
technique. The input impedance is boosted to 6 GΩ, while
the conventional input impedance equals to 11 MΩ achieving
more than 540x boosting factor at DC. As shown in Fig. 6, the
histogram from Monte Carlo simulation of 100 runs reveals the
± 3σ standard deviation for the boosted input impedance at DC
to be 1.1 GΩ with minimum boosted input impedance equals
to 5.5 GΩ across mismatch variations. The input referred √noise
power spectral density (PSD) of the CCFIA is 35 nV / Hz
as shown in Fig. 7. The noise of the input transistors of GM1
dominates around 60% of the total input referred noise, while
the proposed negative capacitance circuit noise contribution is
less than 0.5%.
The mid-band gain of the CCFIA equals to 40 dB as shown
in Fig. 7. The high pass 3-dB corner frequency is 0.7 Hz
which is sufficient for sharp rejection to the electrode DC
offset. The low pass 3-dB bandwidth is 450 Hz governed
by the inherent low pass characteristics of the CCFIA itself.
Fig. 8 shows the histogram from Monte Carlo simulation of
100 runs for the output referred ripple. The maximum ± 3σ
output referred ripple is 100 µV. This corresponds to 1 µV
maximum input referred ripple. It is noticeable that the RRL
(2) significantly suppressed the chopping ripples. The transient
step response of the CCFIA is shown in Fig. 9 for an input step
 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE

Fig. 5: Input impedance versus frequency Fig. 9: Transient step response of the CCFIA

Table 1: Performance summary and comparison with state-of-the-art IAs

[2] [3] [4] [5] [6] This
√ work
Inp. Noise PSD (nV / Hz) 60 21 130 80 100 35
Input Impedance (GΩ) 0.03 <0.02 >0.7 >2 0.3 6
Current (µA) 1.8 143 3.5 11 1.6 25
Gain (dB) 40 40 60 40 26 40
Technology (nm) 65 700 180 180 40 65
Input Ripple (µV) 3 0.39 — 0.2 — 1
Feedback Architecture Cap. Cur. Cap. Cap. Cap. Cap.

Fig. 6: Histogram for DC input impedance
this paper. The proposed technique achieves much larger
input impedance without noise degradation or area overhead.
Moreover, the RRL significantly suppress the chopping ripples.
While the DC servo loop filters out the electrode DC offset.
Simulated using UMC 65 nm CMOS technology, the proposed
technique achieves a boosted input impedance much higher
than 2 GΩ with 1 µV maximum input referred ripple and
can tolerate up to 20 mV as electrode√DC offset voltage. The
input referred noise PSD is 35 nV / Hz with total current
consumption equals to 25 µA.

ACKNOWLEDGMENT
Fig. 7: Input noise PSD and gain versus frequency The authors would like to thank the National Telecommu-
nication Regulatory Authority (NTRA) in Egypt for supporting
this work.

Fig. 8: Histogram for output referred ripples
of amplitude 5 mV and capacitive load equals to 10 pF with
20 mV tolerable electrode DC offset intentionally added at the
input of the CCFIA. Table 1 summarizes the obtained results
and compares them with the existing state-of-the-art IAs. The
proposed input impedance boosting technique achieves the
highest input impedance.
V. C ONCLUSION
Using a negative capacitance circuit, an effective input
impedance boosting technique for CCFIAs is proposed in
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