ISSCC 2019 / SESSION 28 / TECHNIQUES FOR LOW-POWER & HIGH-PERFORMANCE WIRELESS / 28.
28.8 A 21dBm-OP1dB 20.3%-Efficiency -131.8dBm/Hz-Noise
X-Band Cartesian-Error-Feedback Transmitter with Fully
Integrated Power Amplifier in 65nm CMOS
Jinbo Li1, Zhiwei Xu2, Qun J. Gu1
1
University of California, Davis, CA
2
Zhejiang University, Hangzhou, China
The increase of carrier frequency enables the utilization of the abundant high-
frequency resource to meet the ceaseless demand for high data-rates. With
respect to the transmitter, the design challenges include linear and high-efficiency
PAs at high frequencies, low out-of-band (OOB) noise for frequency division
duplex (FDD) applications, etc. Moreover, the integration of PAs on the CMOS die
with other transmitter blocks greatly reduces the form factor and cuts down the
cost. Among various linearization techniques, the Cartesian feedback architecture
excels in its robustness against the process, voltage and temperature (PVT)
variations as well as aging effects, but suffers from the noise-linearity trade-off
caused by the feedback path [1-3]. To mitigate this issue, a Cartesian error-
feedback architecture is proposed by adopting a reference path to cancel the signal
before the feedback path and only leave the error information in principle. In this
work, an X-band Cartesian error-feedback transmitter with a fully integrated power
amplifier in bulk CMOS is implemented, and delivers maximum power (PSAT) of
21.4dBm and output-referred 1dB compression point (OP1dB) of 21dBm. At PSAT
and OP1dB, the PA efficiency reaches 33.3% and 30.3%, with total system
efficiency of 22.3% and 20.3%, respectively. Compared with the open-loop
condition, the closed-loop transmitter demonstrates up to 13.6dB suppression
of ACLR using WCDMA uplink (UL) signals, and improves EVM by over 6dB for
4Ms/s 64-QAM signals and over 3dB up to 16Ms/s signals. The out-of-band noise
at 100MHz is -133/-131.8dBm/Hz for the lower and upper sidebands respectively.
Figure 28.8.1 illustrates the noise-linearity trade-off in the conventional Cartesian
feedback architecture and the mitigation of the trade-off in the proposed Cartesian
error-feedback architecture (the gain annotations are in ‘dB’ scale for this figure).
The trade-off lies in the contradictory preference of the attenuator gain α for noise
and linearity performances. The nonlinearities generated by the feedback path,
ΔFB, are positively proportional to its input POUT+α. Thus, α needs to be small to
lower ΔFB. Nevertheless, this increases the noise floor referred to the system
output. To address this noise-linearity trade-off, the error-feedback architecture
utilizes a reference path to cancel the signal before the feedback path while only
leaving the error information in principle, thus greatly suppressing the
nonlinearities generated by the feedback path. In this way, larger α can be used
to mitigate noise performance degradation.
Similar to the conventional feedback architecture, the output signal is attenuated
by α before feeding back. Moreover, the reference path supports additional signal
attention of η. Following the procedure in Fig. 28.8.2, the new ratio between the
feedback path input and system output for the error-feedback architecture is
derived. The additional term η is determined by the loop gain Hαβ and the
mismatch between the reference path output and feedback path input, represented
as Δ. Hαβ exists in the denominator of the equation of η and suppresses the
mismatch Δ. With Hαβ of 15dB, η of -20dB is conveniently achieved with the
allowed amplitude mismatch range of -60% to >100% and phase mismatch range
of -60° to 60°. The amplitude and phase mismatch tolerance ranges become
larger with a larger Hαβ. This phenomenon saves design efforts and costs
significantly as accurate amplitude and phase matching at RF frequencies is
challenging.
The X-band PA employs a push-pull cascode structure as the output stage to
allow large output voltage swings. The bias condition not only affects the static
PA’s DC current (IDC) but also has dependence upon the input power (PIN), and
thus affects the efficiency. At low bias voltages, IDC increases with PIN. During high
biases, the instantaneous output current barely changes in the first half cycle, as
limited by the current delivering capability of the active device. By contrast, the
output current keeps decreasing when PIN increases. Therefore, the overall IDC
decreases when PIN increases at high gate-voltage biases. This leads to similar
PAE values at peak output powers despite different bias voltages. For the target
output power of 21 to 22dBm, the optimal bias voltage of 600mV provides the
highest PAE of 33%.
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The reference path provides a signal to cancel the signal sampled from the PA
output without introducing excess nonlinearities into the system. The reference
path incorporates a feedback-based gm stage and a harmonic-trapping (HT)
capacitor-based LO switching stage, as depicted in Fig. 28.8.4. With sufficiently
large loop gain, the effective gm is purely determined by the resistor values, i.e.,
1/(R1 or 2 || R3/2). For the LO switching stage, its linearity is highly affected by the
2fLO (fLO is the LO signal frequency) components at the common-source node of
the switching pair, VS. The 2fLO components of VS are downconverted by the –fLO
component of the switching pair and impact the output linearity performance. The
HT capacitors provide a low-impedance path for the 2fLO components of VS and
thus suppress their contributions. The odd harmonics are unaffected as VS is
close to a virtual short node. The simulation verifies the concept with 3.3dB
improvement in OIP3 and negligible effects on the noise performance of the
reference path. Both linearity and noise performances comply with the system
specifications.
Measurement results include using continuous-wave (CW), 2-tone, WCDMA UL
and 64-QAM 4Ms/s signals, as depicted in Fig. 28.8.5, for both the open- and
closed-loop conditions. In the CW measurement, the transmitter delivers 21.4dBm
PSAT with 22.3% total system efficiency and 33.3% PA efficiency, and 21dBm
OP1dB with 20.3% system efficiency and 30.3% PA efficiency. 2-tone
measurement shows that OIP3 reaches 38dBm for the closed-loop condition and
demonstrates around 13.5dB suppression of the 3rd-order modulation distortions
(IMD3) at medium output powers. For WCDMA UL signals, the closed-loop
transmitter achieves >13dB suppression on ACLR compared with the open-loop
condition. EVM is improved from -28.5dB to -34.5dB for 4Ms/s 64-QAM signal
and shows more than 3dB improvements up to 16Ms/s. The measured wideband
noise spectrum shows -133/-131.8dBm/Hz for lower and upper sidebands,
respectively.
Compared with prior Cartesian feedback transmitters listed in Fig. 28.8.6, this
work operates at the highest frequency, i.e., 10GHz, integrates all the functional
blocks on the same die and delivers the highest output power of 21.4dBm. None
of the prior works mentioned their noise performances due to the aforementioned
noise-linearity trade-off, and this work achieves the output noise of -133/-
131.8dBm/Hz for lower and upper sidebands, with the realization of a low-noise
Cartesian feedback transmitter. This PA-included transmitter demonstrates
comparable PA and system efficiency with other standalone X-band PA works,
and exhibits smallest efficiency degradation between PSAT and OP1dB. With the
figure of merit (FOM) defined as 10OIP3/10/PDC, this design achieves the highest FOM
of 10.3. Fig. 28.8.7 depicts the power breakdown chart and the die micrograph.
The chip is fabricated in 65nm CMOS with dimensions of 2.37mm×1.8mm.
Acknowledgement:
The authors would like to thank ONR and Dr. Deborah Van Vechten for financial
support.
References:
[1] S. Ock et al., "A Cartesian Feedback-feedforward Transmitter IC in 130nm
CMOS," IEEE CICC, pp. 1-4, 2015.
[2] H. Ishihara et al., "A 10MHz Signal Bandwidth Cartesian-loop Transmitter
Capable of Off-Chip PA Linearization," ISSCC, pp. 66-67, Feb. 2010.
[3] J. Li et al., "A Fully-Integrated Cartesian Feedback Loop Transmitter in 65nm
CMOS," IEEE IMS, pp. 103-106, 2017.
[4] H. Wang et al., "A CMOS Broadband Power Amplifier With a Transformer-
Based High-Order Output Matching Network," IEEE JSSC, vol. 45, no. 12, pp.
2709-2722, Dec. 2010.
[5] F. Bohn et al., "Fully Integrated CMOS X-Band Power Amplifier Quad with
Current Reuse and Dynamic Digital Feedback (DDF) Capabilities," IEEE RFIC, pp.
208-211, 2017.
[6] J. H. Tsai et al., "An X-Band Half-Watt CMOS Power Amplifier Using
Interweaved Parallel Combining Transformer," IEEE MWCL, vol. 27, no. 5, pp.
491-493, May 2017.
978-1-5386-8531-0/19/$31.00 ©2019 IEEE
 ISSCC 2019 / February 20, 2019 / 4:45 PM

Figure 28.8.1: Noise-linearity trade-off in conventional Cartesian feedback Figure 28.8.2: Mitigation of the matching requirement between the reference
architecture, and mitigation of the trade-off in the new Cartesian error-feedback path and the main path due to the feedback-loop effect. The gain annotations
architecture. The symbols-G, α, β, η and γ-are in dB scale in this figure. in this figure are linear by default.

Figure 28.8.3: X-band PA design with efficiency optimization. PA’s DC current

(IDC) changes with input power and thus affects efficiency. The contradictory Figure 28.8.4: Implementation of the reference path. The gm stage is based on
effects of the bias and drain effects lead to similar PAE at peak output powers a feedback loop, and the LO switching stage utilizes harmonic-trapping (HT)
despite different bias voltages. capacitors.

28
Figure 28.8.5: Measured results for continuous-wave (CW) signal, 2-tone
signal, WCDMA uplink (UL) signal, 64-QAM 4Ms/s modulated signal and
wideband noise performance. Figure 28.8.6: Performance summary and comparison with SOAs.

DIGEST OF TECHNICAL PAPERS • 453

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 ISSCC 2019 PAPER CONTINUATIONS

Figure 28.8.7: Power breakdown chart and die micrograph of the Cartesian
error-feedback transmitter in a 65nm CMOS process.

• 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE

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