IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 67, NO.
5, MAY 2019 1883
A CMOS Highly Linear Doherty Power
Amplifier With Multigated Transistors
Doohwan Jung , Student Member, IEEE, Huan Zhao, Member, IEEE, and
Hua Wang , Senior Member, IEEE
Abstract— This paper presents a highly linear and power
back-off efficiency-enhanced Doherty power amplifier (PA) fully
integrated into CMOS. The proposed Doherty PA employs
a transformer-based quadrature signal generator, multigated
transistors (MGTRs) in the main PA, Class-C mode auxiliary
PA, and synthesized transformer-based Doherty parallel output
network with the second-harmonic control circuits. An on-chip
8-port transformer-based quadrature signal generator is designed
within a single transformer footprint (340 µm × 340 µm) and
provides 0°/−90° differential signals to the main/auxiliary PAs.
The MGTR in the main PA is implemented using four transistors
with different sizes and biases to generate and extend a near-
zero gm3 operation region. Moreover, an on-chip transformer-
based Doherty parallel output network with the second-harmonic
control circuits shows higher passive efficiency compared with
a conventional Doherty parallel output network and provides
low second-harmonic loads to the main/auxiliary PAs. Both the
proposed MGTR in the main PA and the second-harmonic
control circuits in the main/auxiliary PAs suppress the third-
order intermodulation distortion of the Doherty PA. This results
in a substantial linearity improvement of the Doherty PA, which
can support high-order modulation signals and reduce or even
eliminate the need for digital predistortion (DPD). As a proof-
of-concept design, a 5.8 GHz Doherty PA is implemented in a
standard 55 nm bulk CMOS process. The proposed Doherty PA
exhibits 27.2 dBm saturated output power with 24.5% power-
added efficiency (PAE) at 5.8 GHz. The measured error vector
magnitude with 40/80 MHz of 64-QAM/256-QAM is 2.5%/1.8%
with 20.7/17 dBm average output power, 9.5%/5.3% average
PAE, and −33.2/−36.3 dBc adjacent channel leakage ratio
without any DPD.
Index Terms— CMOS, Doherty power amplifiers (PAs), linear-
ity, multigated transistors (MGTRs), second-harmonic control,
third-order intermodulation distortion (IMD3), transformer.
I. I NTRODUCTION
T HE demand for high data rates and spectrum effi-
cient modulations with high peak-to-average power
ratios (PAPRs) has drastically increased recently in modern
wireless communication systems. This poses stringent linearity
Manuscript received May 3, 2018; revised September 14, 2018 and
November 16, 2018; accepted January 22, 2019. Date of publication March 12,
2019; date of current version May 6, 2019. This paper is an expanded version
from the IEEE MTT-S International Microwave Symposium (IMS2018),
Philadelphia, PA, USA, June 10–15, 2018. (Corresponding author:
Doohwan Jung.)
D. Jung and H. Wang are with the School of Electrical and Computer
Engineering, Georgia Institute of Technology, Atlanta, GA 30308 USA
(e-mail: djung44@gatech.edu; hua.wang@ece.gatech.edu).
H. Zhao is with the Kangxi Communication Technologies (Shanghai) Co.,
Ltd., Shanghai 201203, China.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2019.2899596
0018-9480 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
and efficiency requirements on RF power amplifiers (PAs),
particularly on their amplitude-to-amplitude (AM–AM)
linearity, phase-to-amplitude (AM–PM) linearity, and power
back-off (PBO) efficiency [1]–[5].
Several digital RF PAs (DPAs) and linear RF PAs (LPAs)
with linearity improvement techniques are reported to sup-
port high-speed and high-order modulation signals [6]–[14].
For example, current-mode DPAs desensitize output phase
response by using a feedforward capacitor [6]. However,
DPAs inherently suffer from sampling images that often vio-
late the output power spectral emission mask. On the other
hand, analog LPAs adopt different linearization techniques
[e.g., input capacitance cancellation, multigated transistors
(MGTRs), adaptive biasing, and harmonic trapping] to main-
tain high linearity for high-order modulation signals without
excessive PBO from P1 dB [8]–[14].
To enhance the PA PBO efficiency, several techniques
have been studied. Outphasing PAs achieve PBO efficiency
enhancement by combining two nonlinear PAs using
load modulation [15]–[17]. However, outphasing PAs
need extensive baseband computations to generate outphasing
signals, resulting in high baseband complexity and low system
efficiency at high modulation rates. Envelope-tracking (ET)
PAs modulate the PA supply voltage real time based on the
modulation envelopes [18], [19]. Although ET PAs can achieve
high efficiency in deep PBO in principle, practical supply
modulator designs often exhibit severe tradeoff among power
capability, efficiency, and modulation speed. Conventional
Doherty PAs use Class-AB/Class-C mode biasing for their
main/auxiliary PAs and achieve linearity extension in the
high-power region, PBO efficiency enhancement, and high-
speed modulation [20]–[32]. However, conventional Doherty
PAs often cannot support advanced modulation signals due to
the third-order intermodulation distortion (IMD3) in the mid-
output power region. Additional AM–AM and/or AM–PM
DPD loop-back circuits are often required with coherent
detectors to correct the large-signal amplitude and phase
distortion, along with a large memory depth [33]–[35],
resulting in increasing DPD complexity [35]. Therefore, there
is an increasing need for Doherty PAs that have intrinsically
high linearity and high PBO efficiency enhancement which
can substantially reduce or even eliminate the need for DPD
loop-back overhead.
To address these challenges, we present an RF Doherty
PA architecture that employs hybrid MGTR/harmonic-
trapping linearization and ultracompact low-loss transformer
1884 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 67, NO. 5, MAY 2019
Fig. 1. Proposed highly linear Doherty PA architecture.
Doherty output network [36]. As a proof-of-concept design,
the Doherty PA is implemented in CMOS and achieves
a state-of-the-art performance combination of linearity,
efficiency, and output power. In particular, the MGTR
topology is implemented in the main PA that improves the PA
linearity beyond 6 dB PBO and directly benefits high PAPR
complex modulations. Meanwhile, the transformer-based
Doherty parallel output network with the second-harmonic
trapping further improves the linearity and PA PBO efficiency.
This paper is organized as follows. In Section II, we will
introduce the proposed Doherty PA with MGTR technique
and ultracompact transformer-based Doherty parallel output
network with the second-harmonic control circuits. Section III
presents the MGTR design in the main PA and linearization of
the proposed Doherty PA. Section IV characterizes the demon-
strated transformer-based Doherty parallel output network with
the second-harmonic controls and an 8-port quadrature signal
generator. Section V presents the comprehensive measurement
results of the proof-of-concept 5.8 GHz highly linear CMOS
Doherty PA, including its continuous-wave (CW) and modu-
lation measurements without any additional predistortion.
II. H IGHLY L INEAR D OHERTY PA W ITH MGTR
T ECHNIQUE AND S ECOND -H ARMONIC
C ONTROL C IRCUITS
The proposed 5.8 GHz highly linear Doherty PA architec-
ture is shown in Fig. 1. The main PA is composed of four
transistors in parallel with different sizes and different biasing
conditions. The sizes of the main PA transistors M1–M4 are
1600, 640, 600, and 400 μm, respectively. Since M1 is biased
in the Class-AB mode and M2–M4 are biased in different
Class-C modes, an input VGS region with near-zero gm3 is
achieved, and the IMD3 in the mid-power region is suppressed
before the auxiliary PA turns on. The auxiliary PA is biased
in the Class-C mode. Both the main and auxiliary PAs are
cascode structures that utilize transistors (M5, M10, M13,
and M14), which are 5 V high-voltage devices (extended-drain
nMOS transistors) for enhanced reliability [37], [38]. The
input 90° signal splitter [39] is designed in a single transformer
footprint and provides two equal-power output signals with a
90° phase difference, very low loss (0.4 dB), compact size
(340 μm × 340 μm), and high isolation at 5.8 GHz. The
Doherty parallel output network, comprised of two trans-
formers and a capacitor π-network with the second-harmonic
control circuits, supports impedance transformation, Doherty
active load modulation, power combining, and differential-to-
single-ended conversion. The second-harmonic control circuits
within the Doherty output network provide low impedance at
the second-harmonic frequency to further suppress IMD3 of
the PA. Leveraging these techniques, our Doherty PA achieves
a state-of-the-art linearity without DPD, efficiency, and output
power, among the reported RF Doherty PAs in CMOS.
III. MGTR D ESIGN AND L INEARIZATION
The IMD3 of the PA plays a critical role in its in-band
linearity (EVM) and out-of-band linearity (ACLR or spectrum
regrowth), when amplifying complex modulated signals, such
as high-order QAMs. For simplicity, the nonlinear output
current of a CMOS device versus its gate–source voltage can
be expressed by a Taylor series [40] as follows:
i ds(VGS + v gs ) = i ds (VGS ) + gm1 (VGS )v gs + gm2 (VGS )v gs2
 v gs
1
+ (v gs − x)2 gm3 (x + VGS )d x (1)
2 0
where gmn represents the nth-degree Taylor series expansion
coefficient. The last or residual term, containing gm3 , is the
dominant contributor to IMD3 generation. For a one-tone
sinusoidal input signal, Acos(ωt), IMD3 is highly related to
the input signal magnitude, A. Approximating the transcon-
ductance profile, gm1 (VGS ), by a piecewise linear function
as in [40], the resulting gm3 (VGS ) characteristic becomes a
JUNG et al.: CMOS HIGHLY LINEAR DOHERTY PA WITH MGTRs 1885

Fig. 3. Simulated IMD3 of the conventional Doherty PA and the proposed

Doherty PA.
Fig. 2. Simulated the large-signal gm3 of (a) conventional Doherty PA and
(b) proposed MGTR Doherty PA.

set of impulses, K i δ(VGS − Vi ), where K i and Vi are their

magnitude and voltage position, respectively. When the input
signal traverses the gm3 impulse, it generates the third-order
products (i ds,3) of i ds , which are expressed as [11], [40]

1 Acosωt
i ds,3 = (Acos(ωt) − x)2
2 0
 N 

× K i δ(x + VGS − Vi ) d x. (2)
i=1
Conventional Doherty PAs [20]–[32] are generally biased
Fig. 4. Simulated input capacitance of a single transistor.
in the Class-AB/Class-C mode for the main/auxiliary PAs,
which often achieves IMD3 cancellation between the main and
auxiliary PAs in the high-power region [20], [21]. However,
complex modulations often exhibit their highest envelope
probability density function in the mid-power region [20] even
before the auxiliary PA is turned on, where the main PA
dominates the third-harmonic nonlinearity and thus generates
the excessive IMD3 [Fig. 2(a)].
To further improve the linearity beyond 6 dB PBO, we uti-
lize MGTR in the main PA to achieve a near-zero gm3 region
[Fig. 2(b)]. The gate bias voltages of 0.48, 0.24, 0.13, and
0.01 V are applied to M1–M4, respectively. The negative gm3
of M1 is canceled out by the positive gm3 of M2–M4,
achieving a near-zero gm3 throughout a 0.3 V VGS region,
as shown in Fig. 2(b). In this 0.3 V VGS region, the input signal Fig. 5. Simulated input capacitance of the MGTR main PA.
does not traverse any gm3 impulse and drastically suppresses
the resulting IMD3. Fig. 3 shows the complete IMD3 sim- M1 is biased in the Class-AB mode. For small-to-large input
ulation results. Compared with a conventional Doherty PA, swings, the average input capacitance of M1 (Cin_avg_M1 )
the proposed Doherty PA clearly produces less IMD3 for a is reduced. M2–M4 are biased in the Class-C mode. With
wide range of output powers (particularly at the mid-power increasing input amplitude, the average input capacitance
region) and also extends the PA gain compression point. The (Cin_avg_M2+M3+M4 ) increases. As a result, the overall input
Doherty PA with MGTR in the main PA achieves an IMD3 capacitance is the sum of Cin_avg_M1 and Cin_avg_M2+M3+M4 ,
optimal point at 19 dBm output power (7 dB PBO from P1 dB ) leading to a compensated total average input capacitance
with 12 dB lower IMD3 than a conventional Doherty PA. (Cin_avg_total ), as shown in Fig. 5.
In addition to the gm3 cancellation, the MGTR in the main
PA reduces the average input capacitance variance of the IV. D OHERTY PASSIVE N ETWORK D ESIGN
common-source transistors over the input signal, which thus
suppresses the AM–PM distortion of the Doherty PA. The A. Analysis of Doherty Parallel Output Network Design
average input capacitance of a transistor is subjected to the gate The conventional Doherty output network [41] typically
bias condition and input signal magnitude, as shown in Fig. 4. suffers from low passive efficiency and narrow bandwidth [42].
1886 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 67, NO. 5, MAY 2019

Fig. 6. Schematic of (a) conventional Doherty output network and

(b) modified Doherty parallel output network.

Fig. 8. Design procedure for the demonstrated transformer-based Doherty

parallel output network.

impedance (R L ) to optimal load impedance (Ropt ) of the

main PA as Z MO1 = (2Ropt R L )1/2 . L M1 and CM1 are given
as follows:

2Ropt R L
L M1 = (3)
ωo
1
C M1 =  . (4)
Fig. 7. Simulated passive efficiency comparison between the conventional ωo 2Ropt R L
and modified Doherty output networks.
Meanwhile, Z MO2 and Z MO3 are related through Z MO3 =
It typically consists of two λ/4 transmission lines (T-lines) for Z MO2 (2R L /Ropt )1/2 . L M2 , CM2 , L M3 , and CM3 can be
parallel power combining and it transforms R L to the optimal expressed by Z MO2
load (Ropt ) seen by each PA output, i.e., Z C1 and Z C2 at 0 dB Z MO2
PBO [Fig. 6(a)]. However, the two λ/4 T-lines degrade the L M2 = (5)
ωo
network passive efficiency at PA PBO. Furthermore, when the 1
auxiliary PA turns off, the main PA requires a high impedance C M2 = (6)
Z MO2 ωo
transformation ratio of 4:1. 
Various modified Doherty parallel output networks have Z MO2 2R L
L M3 = · (7)
been proposed to address this issue [42]. Fig. 6(b) shows ωo Ropt
an example. The output signal of the main PA travels only 
one λ/4 T-line to the load instead of two series λ/4 T-lines 1 Ropt
C M3 = · . (8)
[Fig. 6(b)]. Moreover, the impedance transformation ratio Z MO2 ωo 2R L
is 2Ropt /R L :1, which is lower than that of the conventional Step 2: The parallel connections of CM1 /CM2 and L M3 /L M3
Doherty output network. As a result, the passive loss are reorganized. Then, the series inductors L M1 /L M2 and shunt
beyond 6 dB PBO is significantly improved. The 3-D inductors L M3 /L M3 on the main/auxiliary paths are absorbed
electromagnetic (EM) simulation results in Fig. 7 verify this into the physical nonideal transformers TM1 /TM2 as their
loss reduction, showing up to 9% improvement beyond 6 dB leakage inductors and magnetic inductors, respectively. The
PBO. The passive efficiency in Fig. 7 is defined by the ratio transformer TM1 with a turn ratio of 1:(n 1 /k1 ) results in
of the power delivered to the 50  load (Pout ) and total power downscaling for L M1 , L M3 , and CM1 by a factor of (n 1 /k1 )2 .
injected into the network (Pin_main + Pin_aux ). To make a fair The values for the transformer model of TM1 and a tuning
passive efficiency comparison, each λ/4 T-line is implemented capacitor (CMM1 ) for the main PA are given as
using a C–L–C low-pass π-network with an unloaded Q 
of 10. However, the modified Doherty output network requires k 2 2Ropt R L
L MM1 = 1 2 (9)
excessive chip area to implement the three λ/4 T-lines. n 1 ωo

In this paper, we propose a modified Doherty paral- k14 2Ropt R L
lel output network with two transformers and a capacitor L MM3 =  (10)
1 − k12 n 21 ωo
π-network. The design process is explained in the following
2
steps and demonstrated in Fig. 8. The subscript “M” denotes n1 1
CMM1 = ·  (11)
the modified Doherty network in the following analysis. k1 ωo 2Ropt R L
Step 1: The λ/4 T-lines on the main and auxiliary paths are 
k 2 2Ropt R L
converted into C–L–C (TL1 and TL2 ) and L–C–L (TL3 ) π- L PM =  1 (12)
networks. Z MO1, Z MO2 , and Z MO3 are the characteristic 1 − k12 n 21 ωo
impedances of TL1 –TL3 , respectively. Z MO1 on the main where k1 is the magnetic coupling coefficient of the TM1
path is determined by an impedance transformation from load and L PM is the primary inductance of TM1 . Using (9)–(11),
JUNG et al.: CMOS HIGHLY LINEAR DOHERTY PA WITH MGTRs 1887

Z MO2 is given as
k12 Ropt
Z MO2 =  . (13)
1 − k12
CM2 and CM3 are modified as
  
1 − k12 1 − k12 1
C M2 = 2 C M3 = · . (14)
k1 Ropt ωo k1 ωo
2 2Ropt R L
A similar relationship also applies for the auxiliary side
(TM2 ) using an “A”-subscript

2
k2 k2 Ropt
L MA2 =  1 2 · · (15)
1 − k1 n2 ωo

2
k12
k2 
L MA3 =  · · 2Ropt R L (16)
1 − k1 ωo
2 n2

2
1 − k1 2
n2 1
CMA2 = · · (17)
k12 k 2 ω o Ropt
k 2 2
k2 Ropt
L PA =  1 2 ·  · (18)
1 − k1 1 − k2 n
2 ωo Fig. 9. (a) Schematic and (b) simulation results of the common-mode Doherty
2 2
parallel output network.
where k2 is the magnetic coupling coefficient of TM2 and L PA
is the primary inductance of TM2 . From (15) and (16), k2 can
be solved as

k22 2R L
 = . (19)
1 − k22 Ropt
Therefore, k2 is actually determined by the ratio of R L to Ropt .
The transformation ratio of TM1 and TM2 controls the total
device output capacitance (CMM1 and CMA2 ) that the Doherty
output passive network can absorb (11) and (17). The pas-
sive network-loaded quality factor Q load (ωo CMM1 Ropt and
ωo CMA2 Ropt ) for the main and auxiliary PAs should be larger
than the active devices Q load to completely absorb the device
capacitors (Cdev ), requiring low-Q network and fast active
devices for broadband Doherty PA designs [9]. Thus, selecting
the appropriate transformation ratio for TM1 and TM2 can
provide the desired capacitances for CMM1 and CMA2 .
Besides Doherty load modulation, the PA output network
offers the common-mode second-harmonic trapping, providing
low impedance at 2 f 0 which reduces the second-harmonic
drain voltages of the main/auxiliary PAs and thus suppresses Fig. 10. (a) 3-D EM model of the Doherty output passive network.
its feedback to the PA gates and remixing with the fundamental (b) Simulated active load modulation. (c) Simulated passive efficiency of the
tones for IMD3 generation [8], [48]. C2ndm and C2nda are demonstrated transformer-based Doherty parallel output network.
added at the center taps of TM1 and TM2 [Fig. 9(a)],
which then resonate with the isolation inductance (L ISO ) in
series at the center tap of each transformer as well as the for the TM2 design, as shown in (19), to ensure sufficient
series common-mode inductances L Cm = L PM − km L PM impedance transformation for high PA output power. However,
and L Ca = L PA − ka L PA . The achieved common-mode the closely wound coils lead to strong capacitive coupling,
second-harmonic load impedance of the main/auxiliary PAs which contributes to the imbalance between the differential
is 2.5/3.7  at 11.6 GHz [Fig. 9(b)], ensuring sufficient output terminals of the auxiliary PA. To mitigate this load
second-harmonic trapping. imbalance, the center tap of TM2 is shifted to the right by
The 3-D EM model of the Doherty output passive 16.5 μm [Fig. 10(a)]. In Fig. 10(b), the real parts of the
network and the simulated active load modulation for load impedance for both PAs show the desired Doherty load
the main/auxiliary PAs and passive efficiency are shown modulation, while the imaginary parts are largely tuned out
in Fig. 10. The output network also provides the differential- over the output power. A passive efficiency of more than
to-single-ended conversion. A large k2 value is required 63.2% is achieved over the entire PBO region [Fig. 10(c)].
1888 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 67, NO. 5, MAY 2019

Fig. 11. 3-D EM model of the input passive network and simulated output
phase difference of the Doherty input passive network.
Fig. 13. Measurement setup.

Fig. 12. (a) Chip photograph. (b) Chip assembly with chip capacitors.

B. Doherty Input Passive Network Design

A two-way Doherty PA requires two input signals with a
90° phase difference to drive the main and auxiliary PAs [43].
RC–CR networks suffer from high loss [44], while 90° coupled
lines occupy the large area at low RF frequencies. We choose
to utilize a fully differential 8-port folded-transformer-based
90° signal splitting network as our Doherty input passive
design [39] (Fig. 11). The 8-port transformer-based quadra-
ture signal generator achieves equal output amplitude and
90° phase difference output signals at the through port (P2,
−90°) and the coupled port (P3, 0°) by using inductive and
capacitive couplings when the input port (P1, 0°) is excited.
In addition, the quadrature signal generator achieves a compact
one inductor footprint with magnetic coupling enhancement of
the differential mode operation by folding the two single-ended
transformer-based quadrature hybrid. The detailed operation of
the quadrature network is explained in [39]. Fig. 11 shows
the 3-D EM model of the input passive network with the
fully differential quadrature signal generator that achieves a
compact size, low loss of S12 and S13 (0.6 dB), and high
isolation. The output main/auxiliary path phase mismatch is
only 0.6° at 5.8 GHz. The input matching is below −10 dB
at the desired frequency.
Fig. 14. (a) Measured gain and PAE, (b) AM–PM distortion, and (c) Psat
V. E XPERIMENTAL R ESULTS and PAE profiles over frequency.
As a proof-of-concept design at 5.8 GHz, our proposed
highly linear Doherty PA is fully implemented in a standard The chip is mounted on an FR4 PCB to facilitate testing, and
55-nm bulk CMOS process with the extended-drain nMOS off-chip bypass chip capacitors are added to reduce the bond-
device option that supports 5.5 V. The total chip size is 2 mm× wire inductances of the supply/biasing nodes [Fig. 12(b)]. The
3 mm [Fig. 12(a)]. The chip comprises the PA cores, drivers, PA RF input/output is probed for all the tests.
and input/output Doherty passive networks. The supply voltage The experimental setup for CW and modulation
for the PA cores and drivers is 5.5 and 1.2 V, respectively. measurements is shown in Fig. 13. The CW input signal is
JUNG et al.: CMOS HIGHLY LINEAR DOHERTY PA WITH MGTRs 1889

Fig. 15. Demodulated (a) 20 MSym/s 64-QAM and (b) 40 MSym/s 64-QAM. (c) EVM and ACLR of the 64-QAM over Pave . Demodulated (d) 40 MSym/s
256-QAM and (e) 80 MSym/s 256-QAM. (f) EVM and ACLR of the 256-QAM over Pave .

TABLE I
P ERFORMANCE C OMPARISON OF R ECENTLY R EPORTED PA S

generated by a vector signal generator (E8267D). An off-chip
balun (Krytar 4010180) converts the generated signal into a
differential signal that feeds the PA differential input. The
PA output power is monitored by a power meter (N1913A)
to test the PA gain/power response and AM–AM distortion.
The phase difference between the input and output signals
of the PA is measured by an oscilloscope (MSOS840A) to
characterize the PA AM–PM distortion. For modulation tests,
an arbitrary waveform generator AWG70002A generates
complex modulated signals (64-QAM and 256-QAM). The
output signal from the PA is then demodulated by the
MSOS840A. An arbitrary function generator (AFG3252)
triggers AWG70002A and MSOS840A.
The PA is first characterized using CW signals. The
saturated output power (Psat ), power-added efficiency (PAE),
gain, AM–PM distortion, and Psat 1 dB bandwidth are
shown in Fig. 14. The measured Psat , peak PAE, and
power gain are +27.2 dBm, 24.5% PAE, and 23.3 dB at
5.8 GHz, respectively. The maximum relative PBO efficiency
enhancement is 11.7% at 24.8 dBm compared to Class-B.
The maximum AM–PM distortion is 3° at 5.8 GHz. Both the
gain and the AM–PM distortion are measured without any
1890 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 67, NO. 5, MAY 2019
nonlinearity compensation. The Psat 1 dB bandwidth of the
PA is 740 MHz (12.76% fractional bandwidth), and the peak
PAE is above 18.5% over this bandwidth.
Next, the PA is characterized by high-order complex
modulated signals. We utilize single-carrier 64-QAM (PAPR =
6.2 dB) with 20 and 40 MSym/s and single-carrier 256-QAM
(PAPR = 6.3 dB) with 20, 40, and 80 MSym/s for the mod-
ulation tests. Fig. 15 shows the demodulated EVM, ACLR,
average output power (Pave ), and average PAE (PAEave ) with
single-carrier 64-QAM and 256-QAM signals at 5.8 GHz. For
20 and 40 MSym/s 64-QAM signals at 5.8 GHz, the measured
Pave values are 20.7 and 20.6 dBm with 9.3% and 9.4%
PAEave . The measured EVM values are 2.48% and 2.3%,
while the ACLR values are −34.5/−34 and −34.4/−33.2 dBc,
respectively [Fig. 15(a) and (b)]. Fig. 15(c) summarizes the
measured EVM and ACLR versus Pave for the single-carrier
64-QAM. For 20 and 40 MSym/s 64-QAM signals, the PA
achieves similar EVM without additional PBO or DPD. For 40
and 80 MSym/s 256-QAM signals at 5.8 GHz, the measured
Pave values are 19.18 and 17 dBm with 7.4% and 5.2% PAEave .
The measured EVM values are 1.75% and 1.8%, while the
ACLR values are −35.6/−33.8 and −36.6/−36.3 dBc, respec-
tively [Fig. 15(d) and (e)]. Fig. 15(f) shows the summary of the
EVM and ACLR for the 256-QAM. The PA for 80 MSym/s
256-QAM modulation signal requires 3.2 dB additional PBO
to achieve the similar EVM of 20 MSym/s 256-QAM.
VI. C ONCLUSION
We propose a highly linear Doherty PA that employs hybrid
MGTR/harmonic-trapping linearization and a low-loss trans-
former Doherty output network. The MGTR is implemented in
the main PA to extend the near-zero gm3 region and minimize
the power-dependent input capacitance variation. The second-
harmonic control circuits implemented in the Doherty parallel
output network provide low impedance at the second-
harmonic, resulting in substantial IMD3 suppression. As a
proof-of-concept design, we implemented a 5.8 GHz Doherty
PA in a 55-nm CMOS process with extended-drain nMOS
devices. Our Doherty PA prototype achieves 3° AM–PM
and can support 80 MSym/s 256-QAM modulated signal
with 1.8% EVM without DPD while exhibiting enhanced
PBO efficiency (Table I). The Doherty PA demonstrates the
state-of-the-art linearity without DPD, efficiency, and output
power, among the reported RF Doherty PAs in CMOS.
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Doohwan Jung (S’16) was born in Seoul, South
Korea, in 1985. He received the B.S. degree in
electrical engineering from Yonsei University, Seoul,
in 2011, and the M.S. degree from the University
of Michigan, Ann Arbor, MI, USA, in 2013. He is
currently pursuing the Ph.D. degree in electrical
engineering at the Georgia Institute of Technology,
Atlanta, GA, USA.
From 2013 to 2015, he was with Samsung Elec-
tronics, Suwon, South Korea, where he designed
phase-locked loops.
Huan Zhao (S’04–M’09) received the B.Sc. degree
in electronic engineering from Shanghai Jiao Tong
University, Shanghai, China, in 2004, and the M.Sc.
degree in electrical engineering from Lehigh Uni-
versity, Bethlehem, PA, USA, in 2006.
In 2014, he co-founded the Kangxi Commu-
nication Technologies, Co. Ltd., Shanghai, where
he is currently the Chief Technical Officer. His
current research interests include high-performance
RF front-end circuitry in silicon and compound
semiconductors.
Hua Wang (M’05–SM’15) received the M.S. and
Ph.D. degrees in electrical engineering from the
California Institute of Technology, Pasadena, CA,
USA, in 2007 and 2009, respectively.
He was with the Intel Corporation, Mountain View,
CA, USA, and Skyworks Solutions, Woburn, MA,
USA. In 2012, he joined the School of Electrical and
Computer Engineering, Georgia Institute of Technol-
ogy, Atlanta, GA, USA, as an Associate Professor.
He holds the Demetrius T. Paris Junior Profes-
sorship of the School of Electrical and Computer
Engineering, Georgia Institute of Technology. His current research interests
include innovating mixed-signal, RF, and mm-wave integrated circuits and
hybrid systems for wireless communication, radar, imaging, and bioelectronics
applications.
Dr. Wang is a Technical Program Committee member of the IEEE Interna-
tional Solid-State Circuits Conference, the IEEE Radio Frequency Integrated
Circuits Symposium (RFIC), the IEEE Custom Integrated Circuits Conference
(CICC), and the IEEE Biopolar/BiCMOS Circuits and Technology Meeting.
He is also a Steering Committee member of the IEEE RFIC and the
IEEE CICC. He serves as the Chair for Atlanta’s IEEE CAS/SSCS Joint
Chapter, which received the IEEE SSCS Outstanding Chapter Award in 2014.
He was the recipient of the DURIP Award in 2014, the Georgia Institute
of Technology ECE Outstanding Junior Faculty Member Award in 2015,
the Lockheed Dean’s Excellence in Teaching Award in 2015, the National
Science Foundation CAREER Award in 2015, the Georgia Insititute of
Technology Sigma Xi Young Faculty Award in 2016, and the IEEE MTT-S
Outstanding Young Engineer Award in 2017. His research group, the Georgia
Institute of Technology Electronics and Micro-Systems Lab, has received
multiple Best Paper Awards, including the IEEE RFIC Best Student Paper
Award in 2014 (First Place) and 2016 (Second Place), the IEEE CICC Best
Student Paper Award in 2015, the 2016 IEEE Microwave Magazine Best
Paper Award, and the 2016 IEEE SENSORS Best Live Demo Award (Second
Place), and multiple Best Paper Award finalist at IEEE conferences. He is
an Associate Editor of IEEE M ICROWAVE AND W IRELESS C OMPONENTS
L ETTERS .