1094
5, MAY 2015
Design of A Transformer-Based Reconfigurable
Digital Polar Doherty Power Amplifier
Fully Integrated in Bulk CMOS
Song Hu, Student Member, IEEE, Shouhei Kousai, Member, IEEE, Jong Seok Park, Student Member, IEEE,
Outmane Lemtiri Chlieh, Student Member, IEEE, and Hua Wang, Senior Member, IEEE
Abstract—This paper presents a digital polar Doherty power
amplifier (PA) fully integrated in a 65 nm bulk CMOS process. It
achieves +27.3 dBm peak output power and 32.5% peak PA drain
efficiency at 3.82 GHz and 3.60 GHz, respectively. The proposed
digital Doherty PA architecture optimizes the cooperation of the
main and auxiliary amplifiers and achieves superior back-off
efficiency enhancement (a maximum 47.9% improvement versus
the corresponding Class-B operation). This digital intensive ar-
chitecture also allows in-field PA reconfigurability which both
provides robust PA operation against antenna mismatches and al-
lows flexible trade-off optimization on PA efficiency and linearity.
Transformer-based passives are employed as the Doherty input
and output networks. The input 90 signal splitter is realized
by a 6-port folded differential transformer structure. The active
Doherty load modulation and power combining at the PA output
are achieved by two transformers in a parallel configuration.
These transformer-based passives ensure an ultra-compact PA
design (2.1 mm ) and broad bandwidth (24.9% for 1 dB P
bandwidth). Measurement with 1 MSym/s QPSK signal shows
3.5% rms EVM with +23.5 dBm average output power and 26.8%
PA drain efficiency. Measurement with 16-QAM signal exhibits
the PA's flexibility on optimizing efficiency and linearity.
Index Terms—Antenna mismatch, CMOS integrated circuits,
digital, Doherty power amplifier, efficiency, linearity, polar modu-
lation, reconfigurable.
I. INTRODUCTION
T O MEET the perennial demand of a higher data rate with
limited spectrum resource, spectrum efficient modulation
schemes, such as high-order Quadrature Amplitude Modulation
(QAM), are widely employed in modern wireless standards.
These modulation schemes often result in large peak-to-average
power ratios (PAPRs) for the transmitted signals. Consequently,
the power amplifier (PA), often as the most power hungry
block in the wireless transceiver, will frequently operate at a
large power back-off (PBO), leading to efficiency degradation
and a shortened battery life of mobile devices [1]. In addition,
Manuscript received August 26, 2014; revised November 28, 2014; accepted
March 11, 2015. Date of publication April 20, 2015; date of current version
April 30, 2015. This paper was approved by Guest Editor Ranjit Gharpurey.
S. Hu, J. S. Park, O. L. Chlieh, and H. Wang are with the School of Electrical
and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30308
USA (e-mail: husong@gatech.edu, hua.wang@ece.gatech.edu).
S. Kousai is with the Center for Semiconductor R&D, Toshiba Corporation,
Saiwai-ku, Kawasaki 212-8520, Japan (e-mail: shouhei.kousai@toshiba.co.jp).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2015.2415494
0018-9200 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO.
to amplify signals with high fidelity, stringent AM-AM and
AM-PM linearity requirements have become critical PA design
aspects [1].
Several PA techniques have been presented to enhance both
PA PBO efficiency and linearity. Dynamically adapting the PA
biasing current to the envelope signal [2]–[5] can enhance the
AM-AM linearity but may not address the AM-PM linearity.
Envelope Elimination and Restoration (EER) PA [6]–[10], a
polar PA scheme, poses a stringent trade-off on the supply mod-
ulator for its efficiency, bandwidth, and dynamic range [11],
[12], often compromising the performance in practice. In Enve-
lope Tracking (ET) PA [2], [13], [14], although the supply mod-
ulator requirements are relaxed, the peak efficiency is reduced
due to the use of linear PAs as opposed to switching PAs in the
EER systems, and the complexity for predistortion rises [15].
Direct Digital Amplitude Modulation (DDAM) is another polar
PA scheme [16]–[20]. However, single-branch DDAM PAs nor-
mally achieve Class-B PBO efficiency performance only.
On the other hand, PA designs incorporating multiple PAs
have been reported. A low-power PA path can be added to
bypass the main PA and to provide high efficiency at large
PBO [21]. However, this often requires low-loss and highly
linear switches which can withstand a large voltage swing,
adding the design complexity [21], [22]. The outphasing PA
[23]–[26] requires judicious design of the outphasing output
combiner network. The generation of outphasing signals also
requires additional computation power in the digital baseband.
The Doherty PA configuration [27] can achieve enhanced PBO
efficiency and potentially large modulation bandwidth without
costly computation of the input signals. Doherty PAs have
been widely employed in base station applications [28], and it
has recently gained increasing attention for CMOS integration
[29]–[39]. However, several key challenges exist for Doherty
PAs, including non-ideal cooperation between the main and
auxiliary PA paths, large and lossy passive networks, and
limited RF bandwidth. These challenges often lead to compro-
mised performance for the conventional analog Doherty PAs
in practice.
We present a digital polar Doherty PA with transformer-based
input and output passive networks in this paper [38]. The
main and auxiliary PAs are implemented as two digitally
controlled RF power Digital-to-Analog Converters (DACs)
with switching PAs comprising the unit cells. This architecture
enables reconfiguration of the two PA paths to achieve superior
 HU et al.: DESIGN OF A TRANSFORMER-BASED RECONFIGURABLE DIGITAL POLAR DOHERTY PA FULLY INTEGRATED IN BULK CMOS
Fig. 1. Classic Doherty PA configuration. The main and auxiliary amplifiers
are also called carrier and peaking amplifiers respectively in some literature [1].
Fig. 2. Classic Doherty PA operating principle. The quantities of ( ),
( ), and ( ) are the normalized RF current, RF output voltage,
and the effective load impedance for the main (auxiliary) amplifier. The quantity
is the normalized total efficiency for the Doherty PA.
PA PBO efficiency enhancement, robust Doherty operation
against load variations, and flexible efficiency and linearity
optimization. Ultra-compact form-factor and broadband oper-
ation are ensured by the transformer-based input and output
networks. Section II reviews the Doherty PA operation and
presents the proposed digital polar Doherty PA architecture.
The passive network designs are shown in Section III. The
measurement results are demonstrated in Section IV.
II. DIGITAL POLAR DOHERTY PA ARCHITECTURE
A. Doherty Principle Review
Fig. 1 shows the conceptual diagram for a classic 2-way
Doherty PA. A impedance inverter combines the main and
the auxiliary PA outputs. To balance the phase between the
two paths for constructive output power combining, one more
line is needed at the auxiliary PA input. Fig. 2 summarizes
the operation of the 2-way Doherty PA [1], [39]. We assume a
symmetric Doherty configuration with the main and auxiliary
PAs as two identical linear PAs with zero knee voltage. The
lines are assumed to be lossless. The output parasitic
capacitors of the PAs are assumed to be resonated out and all
output harmonics are terminated as “shorted”.
If the optimum load for each amplifier is at the peak
output power, the final load driven by the 2-way Doherty PA
should be to satisfy the classic Doherty PA operation,
while the characteristic impedance of the output line should
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1095
Fig. 3. (a) Conventional analog Doherty PA. (b) Proposed digital polar Doherty
PA architecture.
be [1], [39], [40]. In addition, to ensure Doherty operation
[1], [39], the normalized RF current from the auxiliary PA (de-
noted as ) should track the current from the main PA (denoted
as ) as
high power
(1)
low power.
The output RF voltages (normalized to ) and the effective
load impedance (normalized to ) of the two PAs as well as
the total PA drain efficiency (DE) are plotted in Fig. 2 [1], [39].
In the low power region ( ), only the main PA
is on, and its load impedance is due to the output
impedance inverter. When the main PA outputs half of its max-
imum RF current , its output RF voltage swing
reaches , and the PA achieves the first efficiency peak. In
the high power region ( ), both PAs are on, and the
active load modulation effect leads to a decreasing load at the
main PA output when the total output power increases. It can be
shown that (1) ensures a constant RF voltage swing of at
the main PA output in this high power region ( ),
leading to enhanced PBO efficiency [1], [39]. At the peak output
power, both PAs output maximum RF current ( ) and
achieve maximum output RF voltage swings of ; this leads
to the second efficiency peak. In a symmetric 2-way Doherty
PA, the efficiency between 0 dB and 6 dB PBO can be sub-
stantially enhanced [1], [39].
The desired Doherty PA operation highly relies on the coop-
eration between the two PA paths, in particular the turning-on
point of the auxiliary PA and the gain relationship of the two
PAs. However, it is challenging to satisfy these in analog
Doherty PAs. Conventionally, to mimic Doherty operation,
the auxiliary PA is often biased with a smaller conduction
angle compared with the main PA (Fig. 3(a)). Additional
analog techniques, including uneven input power splitting [41],
asymmetrical main and auxiliary amplifiers [42], and dynamic
biasing [32], [37], [43] have been reported to enhance the
analog Doherty PA performance. However, most techniques
rely on dedicated tuning and lack the flexibility for in-field
adjustment. Achieving desired cooperation between the two
 1096
Fig. 4. Circuit schematic of a digital polar Doherty PA.
amplifier paths remains elusive in practice. We thereby pro-
pose a digital polar architecture to address these challenges in
Doherty PAs.
B. Digital Polar Doherty PA Architecture
Our proposed digital polar Doherty PA is conceptually shown
in Fig. 3(b). Unlike analog Doherty PAs (Fig. 3(a)), both main
and auxiliary PAs are implemented as digitally controlled RF
power DACs. As a result, the auxiliary PA turning-on point and
the two PAs' gain relationship can be precisely controlled using
the digital settings. This leads to a fundamentally improved Do-
herty operation and hence enhanced PBO efficiency compared
with analog Doherty PAs.
Moreover, the polar operation is embedded in the proposed
architecture, which allows the use of switch-mode PAs for high
peak efficiency (Fig. 3(b)). The phase modulated (PM) RF input
is first split into two signals with 90 phase difference. These
two RF signals are then separately amplified by the main and
auxiliary RF power DACs. The desired amplitude modulation
(AM) is first digitized and then mapped to the main and auxiliary
RF power DAC control codes.
Therefore, the proposed digital polar Doherty PA archi-
tecture can potentially achieve both high peak efficiency and
enhanced PBO efficiency. Furthermore, it is demonstrated in
Section IV that the proposed architecture enables reconfig-
urable Doherty active load modulation, which can compensate
the antenna mismatches and achieve robust Doherty operation
resilient to load variations. In addition, measurement results
show that such flexibility enabled by the digital control also
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 5, MAY 2015
provides a unique degree of freedom to optimize the PA effi-
ciency with its linearity.
C. PA Core and Driver Design
The main and auxiliary RF power DACs are each imple-
mented as 5 bit binary-weighted power cells for the proof of
concept. All the DAC bits share the same unit power cell for
minimum mismatches. Five bit DACs, which have moderate
implementation and measurement overhead, are chosen for
QPSK and 16-QAM modulation schemes. Our digital Doherty
PA architecture can accommodate RF DACs with larger num-
bers of bits and binary/thermometer coding methods.
We adopt the differential inverse Class-D (Class- ) PA
as the unit power cell for the two RF power DACs (Fig. 4),
which is compatible with transformer output networks for
efficient and broadband power combining [20], [44], [45].
With a parallel LC resonant load, the Class- PA dif-
ferential output voltage is sinusoidal and satisfies the zero
voltage switching (ZVS) condition. The Class- PA core
is a pseudo-differential cascode amplifier (Fig. 4) with thick
oxide cascoded devices for enhanced power handling. An
optimum device size is determined by the trade-off between the
switching PA on-resistance and its output capacitance. Small
on-resistance is desired for high PA efficiency, but requires
large devices and high driving power. Section III shows that
small device output capacitance is preferred to improve the
passive efficiency of the proposed Doherty output network.
In addition, large device output capacitors provide leakage
paths for the even order harmonics, which deviates the current
waveform from the desired Class- operation, increases
 HU et al.: DESIGN OF A TRANSFORMER-BASED RECONFIGURABLE DIGITAL POLAR DOHERTY PA FULLY INTEGRATED IN BULK CMOS
Fig. 5. (a) Six-port folded-transformer-based differential quadrature gener-
ation structure. (b) EM simulation results showing the wideband differential
quadrature generation.
the voltage/current waveform overlaps, and thus degrades
efficiency [20], [45].
The PA cores are driven by four stage digital drivers. Both
the PA core and the last two stage drivers are 5 bit binary
weighted (Fig. 4). If a sub-PA is off, its last two stage drivers
are also turned off to minimize their impact on the PBO effi-
ciency. Cross-coupled inverters are placed in the driver chain
to balance the differential signals and suppress common-mode
oscillation [19].
III. PASSIVE NETWORK DESIGNS IN THE PROPOSED FULLY
INTEGRATED DOHERTY PA
A. Doherty Input Passive Network Design
The Doherty input passive network generates two outputs
from the RF input with 90 apart and feeds the two PA paths.
To perform such quadrature generation, the RC-CR network and
its extensions, the polyphase filters, are conventionally used but
pose significant RF loss [30], [40]. Couplers based on coupled
slab [29] or spiral [46]–[48] inductors can be used instead. How-
ever, a large footprint is needed in differential configurations
[29], [47], [48], and the required low coupling ( ) low power range. Although switch controlled capacitors [34] or
raises the loss and narrows the bandwidth [49].
We adopt a 6-port folded-transformer-based differential
quadrature generation structure as the input network [38], [50]
(Fig. 5). It folds two transformers with constructive magnetic
coupling to achieve a 6-port fully differential network within
only one inductor footprint for significant area reduction
(Fig. 5(a)). Unlike conventional transformer-based couplers,
our design favors a larger coupling coefficient, leading to less
loss and wider bandwidth [50]. Its 3D EM simulations show
0.7 dB loss at the center frequency and a maximum 8.8 phase
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1097
Fig. 6. Proposed parallel-combining-transformer-based Doherty output pas-
sive network.
error over 25% bandwidth for the differential quadrature out-
puts (Fig. 5(b)), ensuring the broadband Doherty PA operation.
B. Doherty Output Passive Network Design
In conventional Doherty PAs, the output impedance
inverter is often implemented as a - - low-pass -net-
work [28]. The series inductor can be either a slab [29],
[31], [32] or a spiral [30] inductor, which often requires a
large area particularly in differential configurations. The
series-combining-transformer (SCT) network in [51] has been
employed in Doherty PA designs [33], [52]. However, the effi-
ciency of the SCT network intrinsically suffers from the non-zero
output impedance of the auxiliary PA when it is turned off in the
LC tuning networks [35], [36] can be added at the auxiliary PA
output to address this issue, these techniques require additional
complexity and chip area and may also degrade the reliability
and passive efficiency. In addition, a variable balun transformer
has been reported in a CMOS Doherty PA [37]. It also requires
switch controlled capacitors at the PA output, and only discon-
tinuous load modulation can be realized.
In this paper, we propose a parallel-combining-trans-
former-based (PCT-based) Doherty output passive network
(Fig. 6) [38]. Note that parallel power combining naturally
 1098 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 5, MAY 2015

Fig. 7. Design methodology for the proposed PCT-based Doherty output network.

fits the classic Doherty PA operation, which combines the meet the required impedance for the desired Doherty operation.
currents from the two PA paths (Fig. 3). The design process The details on design are presented in the Appendix.
is explained as follows. As the starting point (Fig. 6(a)), the The transformer absorbs the series inductor in the
two PAs are connected through a - - -network as the impedance inverter (Fig. 7), and its design process is explained
impedance inverter and their output parasitic capacitors here. The 's leakage inductor and the two form
( and ) are tuned out with shunt inductors ( the - - impedance inverter. Its magnetizing inductor
and ). The components can be reorganized as in Fig. 6(b). is resonated out by a shunt capacitor at the operating fre-
Next, series inductor in the -network and the main PA quency . This is then followed by an ideal 1: ( ) trans-
shunt inductor are absorbed into a 2:2 transformer [53] former based on the transformer modeling [49]. Assume is
(Fig. 6(c)). The coupling coefficient of is designed to the impedance presented to the main PA; is the impedance
allow its leakage and magnetizing inductors to absorb looking into the impedance inverter from its right side; is
and , respectively. Meanwhile, the load is replaced the impedance seen by the impedance inverter from its left side
by the 50 load and a 1:2 transformer for impedance (Fig. 7). First, this - - impedance inverter together with
down-scaling (Fig. 6(c)). also absorbs the auxiliary PA the transformer should transform to
tuning inductor . at 0 dB PBO and to
This design thus achieves a fully differential Doherty output at dB PBO for the desired Doherty operation. Therefore,
network by two transformers (Fig. 6(d)). It provides Do- the characteristic impedance of this impedance inverter, ,
herty active load modulation, power combining, impedance should satisfy
down-scaling, and differential to single-ended conversion. The
transformer isolates the dc of the two amplifiers. The (2)
and center taps supply the main and auxiliary PAs,
respectively. At the same time, the impedance inverter requires that
A systematic design and optimization methodology for the
PCT-based Doherty output network is presented as follows. The (3)
main and auxiliary PAs are assumed to be identical. Given the
desired output power and supply voltage, the PA core and the and can be solved as
optimum load impedance can be first-order determined by (4)
the large-signal load-pull simulation. The device output capaci-
tance can thus be estimated, which generally presents a and
smaller value in a more advanced process. The optimum PA
load at the frequency can be calculated by (5)
.
In Fig. 7, ( ), ( ), ( ), and ( ) are in Fig. 7 is used to tune out the magnetizing inductor of
the turn ratio, coupling coefficient, leakage inductance and mag- at , therefore
netizing inductance of the transformer ( ). and
the tuning capacitor comprise the impedance down-scaling (6)
network. Assume the impedance looking into this network from
the primary side of is (Fig. 7). The antenna load Note that (on the right side of ) and should be trans-
should be transformed to by and to formed to the secondary side of to absorb the secondary
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 HU et al.: DESIGN OF A TRANSFORMER-BASED RECONFIGURABLE DIGITAL POLAR DOHERTY PA FULLY INTEGRATED IN BULK CMOS 1099

parasitic capacitor of , , and the main PA's output

parasitic capacitor, , which become and (Fig. 7)
with the values as

(7)

and

(8)
Fig. 8. Implementation of the proposed Doherty output passive network.
At the main PA output, one may add an extra to complete
the capacitance absorption as

(9)

Substituting (7) and (8) into (9), one can obtain

(10)

This is named as the capacitance budget equation at the main

PA output. Similarly, at the auxiliary PA output, we can have
the other capacitance budget equation as

(11)

where and are the parasitic capacitors of

and at their primary sides, respectively. is the
extra tuning capacitor at the auxiliary PA output if needed.
Transformer efficiency is derived in [54] as

(12)

where is the load impedance for the transformer, which

Fig. 9. Effective load impedance for the main and auxiliary PAs based on the
can be either the antenna impedance for or the actively EM-simulated Doherty output passive network. Device output parasitic capac-
modulated impedance in parallel with for ; is the itors and constant tuning capacitors are included. The two PA RF currents are
coupling coefficient; and are the quality factors for the assumed to follow (1), which can be achieved in practice by the DAC digital
codes.
primary and secondary coils with as the primary/secondary
turn ratio. From (12), a large coupling coefficient improves
the transformer efficiency. A large is also desired for wide
bandwidth operation [49].
For given and , a larger ( ) leads
to a larger based on (5). Meanwhile, the right side of
(10) decreases when increases. It manifests several design
insights. First, to provide a large capacitance budget at the main
PA output, the turn ratio of should be small. Hence,
is designed as a 2:2 transformer ( ). Secondly, to absorb
a large parasitic capacitance by the device and the transformer
, the extra tuning capacitor should be avoided.
Thirdly, (10) suggests that a better passive performance can be
Fig. 10. Simulation results on the passive efficiency with the EM-simulated
achieved in a more advanced process. This is because a small Doherty output passive network.
relaxes the required capacitance budget and allows a
higher coupling coefficient , which improves the transformer
passive efficiency. from to , depending
In addition, (12) reveals another important design aspect that on the power level (Fig. 2). This means the passive efficiency
the transformer passive efficiency relies on the load impedance. of and thus the overall passive efficiency will change with
In the desired Doherty operation, due to the active load modu- respect to the output power. The SCT network also presents a
lation, the impedance loading of the transformer can vary similar characteristic [52], [55]. Note that this is different from
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 1100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 5, MAY 2015

Fig. 11. (a) Chip microphotograph. (b) Chip assembly.

single-branch transformer-based PAs, where the passive effi-

ciency remains the same for different output power levels due
to the constant load impedance.
The 3D EM structure of the output network and the simu-
lated effective load impedance for the main and auxiliary PAs
are shown in Figs. 8 and 9, respectively. The two PA loads both
present decreasing real parts in the high power region, demon-
strating the true Doherty active load pulling behavior (Fig. 2).
Moreover, the imaginary parts in our PCT network are tuned out
over the whole power range without any switch controlled ca-
pacitor. The efficiency of this network versus the output power
is plotted in Fig. 10. The power dependent passive efficiency is
due to two reasons. First, the main PA output experiences more
Fig. 12. Measured PA output power and efficiencies.
loss than the auxiliary PA output; therefore the overall passive
efficiency increases at a higher output power when the auxil-
iary PA contributes more power via a passive path with a higher
efficiency. Secondly, as previously discussed, efficiency
inherently varies when the output power backs off and its ef-
fective load impedance varies. Simulation shows 70.4% peak
passive efficiency at 0 dB PBO.

IV. EXPERIMENTAL RESULTS

The PA is implemented in a standard 65 nm bulk CMOS
process with 1.41 1.48 mm area (Fig. 11(a)). The supply by-
pass chip capacitors are placed close to the chip in a staircase
fashion to reduce the wire-bond inductance and resistance and
improve the PA stability and efficiency (Fig. 11(b)). The sup-
plies for the PA cores and the digital drivers are 3 V and 1.2 V,
respectively.

A. Continuous Wave Measurement

The PA is first characterized using continuous wave signals
with a 50 standard load. The peak output power and effi-
ciency are shown in Fig. 12. The PA achieves its peak power
of dBm at 3.82 GHz with 16.8 dB power gain. The peak
PA DE and PAE are 32.5% and 28.6% at 3.60 GHz, respec-
tively. The dB bandwidth of the PA is 3.10–3.98 GHz. This
24.9% wide bandwidth is mainly due to the broadband input
and output passive networks. At 3.82 GHz, the suppression of
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Fig. 13. Measured PA drain efficiency with the 50 standard load.
the 2nd and 3rd harmonics are 38.1 dBc and 54.7 dBc at the
peak output power.
The main/auxiliary PA code combinations are then swept
with the 50 load, and Fig. 13 shows the PA DE versus the
PBO level at 3.82 GHz. Different points represent different AM
control codes. Code means that there are and unit
 HU et al.: DESIGN OF A TRANSFORMER-BASED RECONFIGURABLE DIGITAL POLAR DOHERTY PA FULLY INTEGRATED IN BULK CMOS
Fig. 14. Measured PA drain efficiency with the load at
. used for all the power levels.
power cells turned on in the main and auxiliary PAs, respec-
tively. For a given PBO level, the optimum code can be chosen
to achieve the best efficiency, which is called the Efficiency
Optimum Code (EOC). Note that this is a unique reconfig-
urability advantage of the digital Doherty PA compared with
the analog counterparts, since the latter cannot arbitrarily set
the gains of the two PAs. The maximum absolute and relative
efficiency improvement compared with a Class-B PA is 7.0%
at 5.4 dB PBO (from 16.2% DE to 23.2% DE) and 47.9% at
8.1 dB PBO (from 11.9% DE to 17.6% DE), respectively.
To demonstrate the robust PBO efficiency enhancement
against antenna mismatches, the PA is measured with loads at
the 2:1 VSWR circle. Fig. 14 illustrates an example result with
at 3.60 GHz. The PBO efficiency enhancement
by the Doherty operation is maintained even when the PA
is subjected to load variations. The maximum absolute and
relative efficiency improvement compared with a Class-B PA is
6.2% at 4.3 dB PBO (from 13.1% DE to 19.3% DE) and 50%
at 6.3 dB PBO (from 10.4% DE to 15.6% DE), respectively.
This is also due to the gain programming flexibility of the two
PAs by using the digital control [39]. The codes for optimum
efficiency at 6 dB, 5 dB and 4 dB PBO are depicted in
Figs. 13 and 14.
B. Modulated Signal Measurement
The PA is then characterized with modulated signals. An RF
vector signal generator synthesizes the PM RF input signal, and
the AM signal is realized by the 10 bit control signals from
an FPGA board. The AM control codes determine the output
power, so the appropriate codes can be set dynamically to syn-
thesize the modulated envelope. The full power range is always
utilized, and no AM or PM predistortion is applied in the fol-
lowing modulation tests.
Using the EOCs obtained in the static measurement, the PA
achieves 3.5% rms EVM (Fig. 15) with 23.5 dBm average
output power and 26.8% PA DE at 3.82 GHz for the QPSK
signal (1 MSym/s, 3.7 dB PAPR) with a 10 oversampling
ratio. Compared with a Class-B PA, there is 37.4% relative DE
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1101
Fig. 15. Modulation test with 1 MSym/s QPSK at dBm average output
and power and 26.8% PA drain efficiency. Efficiency optimum codes (EOCs) are
improvement by the Doherty operation. Suppression of the sam-
pling aliases is consistent with a zero-order hold system. The
sampling rate is limited by the test setup.
In the tests with the 16-QAM signal (500 kSym/s, 10 MHz
sampling rate, 5.4 dB PAPR), if using the EOCs, the PA achieves
5.6% rms EVM (Fig. 16(a)) with 21.8 dBm average output
power and 22.1% PA DE at 3.82 GHz. This is 37.8% better than
the Class-B operation.
However, when using the EOCs for the 16-QAM signal,
we observe undesired rotation of the inner four constellation
points (Fig. 16(a)). This is due to the AM-PM distortion which
dominates the EVM degradation. At each power level, the
code with the highest efficiency (EOC) may not guarantee
the minimum phase distortion (Fig. 17(a)). For a given output
power, we can also select the control code with the least phase
distortion measured in the static test (Fig. 17(a)). It is defined
as the Linearity Optimum Code (LOC). Using the LOCs for
the whole power range, AM-PM distortion effects are signif-
icantly reduced in the measured constellation and the EVM is
improved (Fig. 16(b)). The PA achieves 4.4% rms EVM with
22.2 dBm average output power and 20.2% PA DE. Note
that the code selection strategy, i.e., choosing the EOCs or
LOCs, offers a new degree of freedom to trade off between
the PA linearity and efficiency (Fig. 17). This again manifests
the reconfigurability advantage of our digital Doherty PA over
the conventional analog counterparts. The achieved average
DE by LOCs is 20.3% better than the Class-B operation. In
addition, the LOCs improve not only the in-band linearity,
evaluated by EVM, but also the out-of-band (OOB) linearity,
which is justified by Adjacent Channel Leakage Ratio (ACLR)
(Fig. 18). This is due to the better matched symbol trajectory
by the reduced phase distortion.
Moreover, leveraging the digital control, one can adopt a
hybrid code setting using the EOCs and LOCs for different
power levels. Table I lists the 16-QAM measurement results for
five cases. The power levels using the LOCs are in the second
column. The rest power levels adopt EOCs. The measured
spectrum for the case No. 4 is shown in Fig. 18. The flexible
 1102 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 5, MAY 2015

Fig. 16. Modulation tests with 500 kSym/s 16-QAM when applying (a) efficiency optimum codes, and (b) linearity optimum codes for all the power levels. The
undesired constellation rotation due to the AM-PM distortion when using the EOCs (in a) is corrected by the LOCs (in b).

Fig. 17. (a) Measured large signal phase response referred to the value at the peak power and (b) relative PA drain efficiency improvement over Class-B operation
for the linearity optimum codes (LOCs) and the efficiency optimum codes (EOCs).

TABLE I
MEASUREMENT RESULTS WITH DIFFERENT CONTROL CODE
OPTIMIZATION METHODS

different applications with different constellations and spec-

Fig. 18. OOB linearity comparision when applying different code selection
strategies to different power levels. See Table I for the configurations in different
cases.
and reconfigurable digital control offers a unique degree of
freedom to optimize linearity together with efficiency. For
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ifications on in-band/OOB linearity, our digital Doherty PA
can be reconfigured to optimize the efficiency. Additional
digital predistortions can further improve the PA linearity, but
our PA's built-in reconfigurability naturally augments such
predistortions and potentially reduces their complexities.
Table II summaries the measured PA performance. There is
no degradation observed over tests with more than 30 hours.
Comparisons with other CMOS Doherty PAs and CMOS PAs
using other back-off efficiency enhancement techniques are
shown in Tables II and III, respectively.
 HU et al.: DESIGN OF A TRANSFORMER-BASED RECONFIGURABLE DIGITAL POLAR DOHERTY PA FULLY INTEGRATED IN BULK CMOS 1103

TABLE II
PERFORMANCE SUMMARY AND COMPARISON WITH OTHER CMOS DOHERTY PAS

TABLE III
MODULATION PERFORMANCE COMPARISON WITH CMOS PAS USING OTHER BACK-OFF EFFICIENCY ENHANCEMENT TECHNIQUES

V. CONCLUSIONS this impedance down-scaling network from the primary side of

A dBm digital polar Doherty PA fully integrated in is . is designed to null the imaginary part of at
65nm bulk CMOS is presented. Digitally intensive architecture and its capacitance can be calculated as
results in superior, robust, and flexible Doherty operation. It is
suitable for system-on-chip applications, where the digital con- (13)
trol can be readily derived from the digital baseband. Broadband
and ultra-compact transformer-based passive structures are also Then, in Fig. 7 will be a purely real impedance and
presented for fully-integrated Doherty PAs.

APPENDIX (14)
IMPEDANCE DOWN-SCALING TRANSFORMER DESIGN
To achieve the desired Doherty operation, the antenna load By equating with , one can solve the primary induc-
should be transformed to . In Fig. 7, this is real- tance of as
ized by a transformer with coupling coefficient and a
tuning capacitor . This appendix discusses the design of this
impedance transformation network, which can also serve as a (15)
general guideline to scale between two real loads by a non-ideal
transformer. Note and
Assume the magnetizing and leakage inductance of are always true for in (13) and (14).
are and and the impedance looking into The latter result can also be easily observed in the Smith chart
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 1104
Fig. 19. Explanation on the Smith chart for the effects of the non-ideal mag-
netic coupling in the impedance down-scaling transformer.
interpretation (Fig. 19). Therefore, the non-ideal coupling be-
tween the two coils in the impedance downscaling transformer
not only degrades the efficiency and bandwidth [49], but also
limits the smallest real impedance which can be presented to
the PA. This matches common design intuitions.
Besides, an impedance down-scaling transformer is more
sensitive to the loss of the coil where the down-scaled
impedance is presented. This can also be identified by checking
the factors in front of and in the denominator of
(12). It can be shown that in a transformer with moderate or
low loss and a loaded quality factor, the loss of the coil
with fewer turns dominates. This also aligns with common
design practices.
Therefore, the topology and geometry for the impedance
down-scaling transformer need to be properly designed con-
sidering the trade-off among the coupling coefficient, quality
factors, and parasitic capacitance. In this digital Doherty PA de-
sign, the impedance down-scaling transformer is implemented
as a 1:2 transformer with two parallel primary coils sandwiched
with the 2-turn secondary coil (Fig. 8) [20], [56]. This topology
enhances both the quality factor of the primary coil and the
coupling coefficient between the coils.
ACKNOWLEDGMENT
The authors would like to acknowledge Toshiba Corporation
for the foundry service and Georgia Electronic Design Center
(GEDC) for the measurement equipment support.
REFERENCES
[1] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd
ed. Boston, MA, USA: Artech House, 2006.
[2] A. A. M. Saleh and D. C. Cox, “Improving the power-added efficiency
of FET amplifiers operating with varying-envelope signals,” IEEE
Trans. Microw. Theory Techn., vol. 31, no. 1, pp. 51–56, Jan. 1983.
[3] Y. S. Noh and C. S. Park, “An intelligent power amplifier MMIC using
a new adaptive bias control circuit for W-CDMA applications,” IEEE
J. Solid-State Circuits, vol. 39, no. 6, pp. 967–970, Jun. 2004.
[4] P. C. Wang et al., “A 2.4 GHz fully integrated transmitter front end
witth dBm on-chip CMOS power amplifier,” in Proc. IEEE RF
Integrated Circuits Symp., 2007, pp. 263–266.
[5] A. Afsahi, A. Behzad, V. Magoon, and L. E. Larson, “Linearized dual-
band power amplifiers with integrated baluns in 65 nm CMOS for a 2
2 802.11n MIMO WLAN SoC,” IEEE J. Solid-State Circuits, vol.
45, no. 5, pp. 955–966, May 2010.
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on July 11,2023 at 06:10:24 UTC from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 5, MAY 2015
[6] L. R. Kahn, “Single-sideband transmission by envelope elimination
and restoration,” Proc. IRE, vol. 40, no. 7, pp. 803–806, Jul. 1952.
[7] D. K. Su and W. J. McFarland, “An IC for linearizing RF power ampli-
fiers using envelope elimination and restoration,” IEEE J. Solid-State
Circuits, vol. 33, no. 12, pp. 2252–2258, Dec. 1998.
[8] P. Reynaert and M. S. J. Steyaert, “A 1.75 GHz polar modulated CMOS
RF power amplifier for GSM-EDGE,” IEEE J. Solid-State Circuits,
vol. 40, no. 12, pp. 2598–2608, Dec. 2005.
[9] J. S. Walling, S. S. Taylor, and D. J. Allstot, “A Class-G supply modu-
lator and Class-E PA in 130 nm CMOS,” IEEE J. Solid-State Circuits,
vol. 44, no. 9, pp. 2339–2347, Sep. 2009.
[10] K. Oishi et al., “A 1.95 GHz fully integrated envelope elimination and
restoration CMOS power amplifier using timing alignment technique
for WCDMA and LTE,” IEEE J. Solid-State Circuits, vol. 49, no. 12,
pp. 2915–2924, Dec. 2014.
[11] M. Hassan, P. M. Asbeck, and L. E. Larson, “A CMOS dual-switching
power-supply modulator with 8% efficiency improvement for 20 MHz
LTE envelope tracking RF power amplifiers,” in IEEE Int. Solid-State
Circuits Conf. (ISSCC) Dig. Tech. Papers, 2013, pp. 366–367.
[12] P. Arno, M. Thomas, V. Molata, and T. Jerabek, “Envelope modulator
for multimode transmitters with AC-coupled multilevel regulators,” in
IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2014,
pp. 296–297.
[13] R. Wu, Y. T. Liu, J. Lopez, C. Schecht, Y. Li, and D. Y. C. Lie, “High-
efficiency silicon-based envelope-tracking power amplifier design with
envelope shaping for broadband wireless applications,” IEEE J. Solid-
State Circuits, vol. 48, no. 9, pp. 2030–2040, Sep. 2013.
[14] D. Kang, B. Park, D. Kim, J. Kim, Y. Cho, and B. Kim, “Envelope-
tracking CMOS power amplifier module for LTE applications,” IEEE
Trans. Microw. Theory Techn., vol. 61, no. 10, pp. 3763–3773, Oct.
2013.
[15] A. Zhu, P. J. Draxler, C. Hsia, T. J. Brazil, D. F. Kimball, and P. M.
Asbeck, “Digital predistortion for envelope-tracking power amplifiers
using decomposed piecewise Volterra series,” IEEE Trans. Microw.
Theory Techn., vol. 56, no. 10, pp. 2237–2247, Oct. 2008.
[16] R. B. Staszewski et al., “All-digital PLL and transmitter for mobile
phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482,
Dec. 2005.
[17] A. Kavousian, D. K. Su, M. Hekmat, A. Shirvani, and B. Wooley,
“A digitally modulated polar CMOS power amplifier with a 20 MHz
channel bandwidth,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp.
2251–2258, Oct. 2008.
[18] C. D. Presti, F. Carrara, A. Scuderi, P. M. Asbeck, and G. Palmisano,
“A 25 dBm digitally modulated CMOS power amplifier for WCDMA/
EDGE/OFDM with adaptive digital predistortion and efficient power
control,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 1883–1896,
Jul. 2009.
[19] S. Kousai and A. Hajimiri, “An octave-range, watt-level, fully-inte-
grated CMOS switching power mixer array for linearization and back-
off-efficiency improvement,” IEEE J. Solid-State Circuits, vol. 44, no.
12, pp. 3376–3392, Dec. 2009.
[20] D. Chowdhury, L. Ye, E. Alon, and A. M. Niknejad, “An efficient
mixed-signal 2.4 GHz polar power amplifier in 65 nm CMOS tech-
nology,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1796–1809,
Aug. 2011.
[21] B. Koo, T. Joo, Y. Na, and S. Hong, “A fully integrated dual-mode
CMOS power amplifier for WCDMA applications,” in IEEE Int. Solid-
State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012, pp. 82–84.
[22] Y. Yoon, H. Kim, Y. Park, M. Ahn, C. H. Lee, and J. Laskar, “A high-
power and highly linear CMOS switched capacitor,” IEEE Microw.
Wireless Compon. Lett., vol. 20, no. 11, pp. 619–621, Nov. 2010.
[23] H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23,
no. 11, pp. 1370–1392, Nov. 1935.
[24] H. Xu, Y. Palaskas, A. Ravi, M. Sajadieh, M. A. El-Tanani, and K.
Soumyanath, “A flip-chip-packaged 25.3 dBm Class-D outphasing
power amplifier in 32 nm CMOS for WLAN application,” IEEE J.
Solid-State Circuits, vol. 46, no. 7, pp. 1596–1605, May 2011.
[25] S. Moloudi and A. A. Abidi, “The outphasing RF power amplifier: A
comprehensive analysis and a Class-B CMOS realization,” IEEE J.
Solid-State Circuits, vol. 48, no. 6, pp. 1357–1369, Jun. 2013.
[26] L. Ding, J. Hur, R. Hezar, and B. Haroun, “A 25 dBm outphasing power
amplifier with novel non-isolated combining network,” in Proc. IEEE
RF Integrated Circuits Symp., 2014, pp. 231–234.
[27] W. H. Doherty, “A new high efficiency power amplifiers for modulated
waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–1182, Sep. 1936.
 HU et al.: DESIGN OF A TRANSFORMER-BASED RECONFIGURABLE DIGITAL POLAR DOHERTY PA FULLY INTEGRATED IN BULK CMOS
[28] A. Grebennikov and S. Bulja, “High-efficiency Doherty power ampli-
fiers: Historical aspect and modern trends,” Proc. IEEE, vol. 100, no.
12, pp. 3190–3219, Dec. 2012.
[29] M. Elmala, J. Paramesh, and R. Bishop, “A 90 nm CMOS Doherty
power amplifier with minimum AM-PM distortion,” IEEE J. Solid-
State Circuits, vol. 41, no. 6, pp. 1323–1332, Jun. 2006.
[30] N. Wongkomet, L. Tee, and P. R. Gray, “A dBm CMOS RF
Doherty power amplifier for wireless communications,” IEEE J. Solid-
State Circuits, vol. 41, no. 12, pp. 2852–2859, Dec. 2006.
[31] K. Onizuka, S. Saigusa, and S. Otaka, “A dBm CMOS Do-
herty power amplifier with reliability enhancement technique,” in IEEE
Symp. VLSI Circuits, 2012, pp. 78–79.
[32] K. Onizuka, K. Ikeuchi, S. Saigusa, and S. Otaka, “A 2.4 GHz CMOS
Doherty power amplifier with dynamic biasing scheme,” in Proc. IEEE
Asian Solid-State Circuits Conf., 2012, pp. 93–96.
[33] E. Kaymaksut and P. Reynaert, “Transformer-based uneven Doherty
power amplifier in 90 nm CMOS for WLAN Applications,” IEEE J.
Solid-State Circuits, vol. 47, no. 7, pp. 1659–1671, Jul. 2012.
[34] W. M. Gaber, P. Wambacq, J. Craninckx, and M. Ingels, “A CMOS
IQ digital Doherty transmitter using modulated tuning capacitors,” in
Proc. IEEE European Solid State Circuits Conf. (ESSCIRC), 2012, pp.
341–344.
[35] E. Kaymaksut, D. Zhao, and P. Reynaert, “E-band transformer-based
Doherty power amplifier in 40 nm CMOS,” in Proc. IEEE RF Inte-
grated Circuits Symp., 2014, pp. 167–170.
[36] C. Zhao, B. Park, and B. Kim, “Complementary metal-oxide semi-
conductor Doherty power amplifier based on voltage combining
method,” IET Microw. Antennas Propag., vol. 8, no. 3, pp. 131–136,
Feb. 2014.
[37] N. Ryu, S. Jang, K. C. Lee, and Y. Jeong, “CMOS Doherty ampli-
fier with variable balun transformer and adaptive bias control for wire-
less LAN application,” IEEE J. Solid-State Circuits, vol. 49, no. 6, pp.
1356–1365, Jun. 2014.
[38] S. Hu, S. Kousai, J. S. Park, O. L. Chlieh, and H. Wang, “A dBm
transformer-based digital Doherty polar power amplifier fully inte-
grated in Bulk CMOS,” in Proc. IEEE RF Integrated Circuits Symp.,
2014, pp. 235–238.
[39] S. Hu, S. Kousai, and H. Wang, “Antenna impedance variation com-
pensation by exploiting a digital Doherty power amplifier architec-
ture,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 2, pp. 580–597,
Feb. 2015.
[40] B. Razavi, RF Microelectronics, 2nd ed. Englewood Cliffs, NJ, USA:
Prentice Hall, 2011.
[41] J. Kim, J. Cha, I. Kim, and B. Kim, “Optimum operation of asymmet-
rical cells-based linear Doherty power amplifiers – Uneven power drive
and power matching,” IEEE Trans. Microw. Theory Techn., vol. 53, no.
5, pp. 1802–1809, May 2005.
[42] J. Kim, B. Fehri, S. Boumaiza, and J. Wood, “Power efficiency and
linearity enhancement using optimized asymmetrical Doherty power
amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 2, pp.
425–434, Feb. 2011.
[43] J. Nam and B. Kim, “The Doherty power amplifier with on-chip dy-
namic bias control circuit for handset application,” IEEE Trans. Mi-
crow. Theory Techn., vol. 55, no. 4, pp. 633–642, Apr. 2007.
[44] H. Kobayashi, J. M. Hinrichs, and P. M. Asbeck, “Current-mode
Class-D power amplifiers for high-efficiency RF applications,” IEEE
Trans. Microw. Theory Techn., vol. 49, no. 12, pp. 2480–2485, Dec.
2001.
[45] D. Chowdhury, S. V. Thyagarajan, L. Ye, E. Alon, and A. M. Niknejad,
“A fully-integrated efficient CMOS inverse Class-D power amplifier
for digital polar transmitters,” IEEE J. Solid-State Circuits, vol. 47, no.
5, pp. 1113–1122, May 2012.
[46] R. C. Frye, S. Kapur, and R. C. Melville, “A 2 GHz quadrature hybrid
implemented in CMOS technology,” IEEE J. Solid-State Circuits, vol.
38, no. 3, pp. 550–555, Mar. 2003.
[47] F. Golcuk, T. Kanar, and G. M. Rebeiz, “A 90–100 GHz 4 4 SiGe
BiCMOS polarimetric transmit/receive phased array with simultaneous
receive-beams capabilities,” IEEE Trans. Microw. Theory Techn., vol.
61, no. 8, pp. 3099–3114, Aug. 2013.
[48] Q. Shi, K. Vaesen, B. Parvais, G. Mangraviti, and P. Wambacq, “A
54–69.3 GHz dual-band VCO with differential hybrid coupler for
quadrature generation,” in Proc. IEEE Asian Solid-State Circuits
Conf., 2013, pp. 325–328.
[49] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE
J. Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on July 11,2023 at 06:10:24 UTC from IEEE Xplore. Restrictions apply.
1105
[50] J. S. Park, S. Kousai, and H. Wang, “A fully differential ultra-compact
broadband transformer based quadrature generation scheme,” in Proc.
IEEE Custom Integrated Circuits Conf. (CICC), 2013.
[51] P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, “A
5.8 GHz 1 V linear power amplifier using a novel on-chip transformer
power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Cir-
cuits, vol. 43, no. 5, pp. 1054–1063, May 2008.
[52] E. Kaymaksut, B. Francois, and P. Reynaert, “Analysis and optimiza-
tion of transformer-based power combining for back-off efficiency en-
hancement,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 60, no. 4,
pp. 825–835, Apr. 2013.
[53] H. Wang, C. Sideris, and A. Hajimiri, “A CMOS broadband power
amplifier with a transformer-based high-order output matching net-
work,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2709–2722,
Dec. 2010.
[54] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Distributed active
transformer – A new power-combining and impedance-transformation
technique,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 1, pp.
316–331, Jan. 2002.
[55] G. Liu, P. Haldi, T. K. Liu, and A. M. Niknejad, “Fully integrated
CMOS power amplifier with efficiency enhancement at power back-
off,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 600–609, Mar.
2008.
[56] Y. Wang, H. Wang, C. Hull, and S. Ravid, “A transformer-based broad-
band front-end combo in standard CMOS,” IEEE J. Solid-State Cir-
cuits, vol. 47, no. 8, pp. 1810–1819, Aug. 2012.
Song Hu (S'13) was born in September, 1988. He
received the B.Eng. degree in information engi-
neering (with honors) from Southeast University,
Nanjing, China, in 2009, and the M.Sc. degree in
microelectronics from Fudan University, Shanghai,
China, in 2012. His master thesis was focused on
the high-linearity RF front-end for cellular receivers.
He is currently working toward the Ph.D. degree
in electrical engineering at the Georgia Institute of
Technology, Atlanta, GA, USA.
His current research interests include integrated
biosensors and digital-assisted reconfigurable RF integrated circuits and
systems.
Mr. Hu was the recipient of the Best Student Paper Award (1st Place) at
the 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium and
the Best Student Paper Award at the 2011 IEEE Radio Frequency Integration
Technology (RFIT) Symposium. He received the IEEE Microwave Theory and
Techniques Society Graduate Fellowship in 2015 and the Analog Devices Inc.
Outstanding Student Designer Award in 2014. He was also the recipient of the
Southeast University President Scholarship in 2006, the National Scholarship
in 2007, the first prize in the National Undergraduate Electronic Design Contest
in 2008, the Microsoft Young Fellowship Award from Microsoft Research Asia
in 2008, the Marvell Scholarship in 2011, the Shanghai Outstanding Graduate
Student Award in 2012, and the Shanghai Excellent Master Thesis Award in
2013.
Shouhei Kousai (M'08) received the B.S. and M.S.
degrees in electronic engineering from the University
of Tokyo, Tokyo, Japan, in 1996 and 1998, respec-
tively, and the Ph.D. degree in physical electronics
from Tokyo Institute of Technology in 2011.
In 1998, he joined Toshiba Corporation, Kana-
gawa, Japan. Since then, he has been engaged in
the design of analog and RF circuits for wireless
communications. From 2007 to 2009, he was a
visiting scholar at the California Institute of Tech-
nology, Pasadena, CA, USA, where he was engaged
in research on linear power amplifiers.
Dr. Kousai was a member of the technical program committee (TPC) of the
IEEE International Solid-State Circuits Conference (ISSCC). He was also a
member of the TPC of the Asian Solid-State Circuits Conference (A-SSCC)
and International Electron Devices Meeting (IEDM).
 1106
Jong Seok Park (S'13) received the B.S. degree in
electrical and electronic engineering, with highest
honors, from Yonsei University, Seoul, South Korea,
in 2012. He is now pursuing the Ph.D. degree in
electrical and computer engineering at the Georgia
Institute of Technology, Atlanta, GA, USA.
His current research interests include novel EM
structure, RF and mm-wave circuits, and sensors for
biomedical applications.
Mr. Park was the recipient of a study abroad schol-
arship from KFAS in 2012. He was also the recipient
of the Analog Device Inc. Outstanding Student Designer Award in 2014 and a
co-recipient of the RFIC Best Student Paper Award (1st Place) in 2014.
Outmane Lemtiri Chlieh (S'12) received the
Engineering Diploma, equivalent to a Master's
degree, in electronics and signal processing with
a major in integrated circuit design from INP-EN-
SEEIHT, Toulouse, France, in November 2011. He
received a second Master degree in micro and nano
systems from INP (Institut National Polytechnique
de Toulouse) during the same year. He has been a
graduate student in the Georgia Institute of Tech-
nology, Atlanta, GA, USA, since January 2011 and
is currently working towards the Ph.D. degree within
MiRCTECH, an RF research group led by Prof. John Papapolymerou.
His research is mainly focused on developing novel cooling and tuning tech-
niques for high power devices on organic substrates. A part of his work consists
of characterizing III/V based-power amplifiers using load pull measurements.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 5, MAY 2015
Hua Wang (M'05–SM'15) received the B.S. degree
from Tsinghua University, Beijing, China, in 2003,
and the M.S. and Ph.D. degrees in electrical engi-
neering from the California Institute of Technology,
Pasadena, CA, USA, in 2007 and 2009, respectively.
He was with Guidant Corporation during the
summer of 2004, working on accelerometer-based
posture monitoring systems for implantable biomed-
ical devices. In 2010, he joined Intel Corporation,
where he worked on the next generation energy-effi-
cient mm-wave communication link and broadband
CMOS Front-End-Module for Wi-Fi systems. In 2011, he joined Skyworks
Solutions. His work at Skyworks included the development of SAW-less
integrated filter solutions for low-cost cellular-standard Front-End-Module. In
spring 2012, he joined the School of Electrical and Computer Engineering at
Georgia Institute of Technology as an assistant professor. He currently holds
the Demetrius T. Paris Junior Professorship of the School of Electrical and
Computer Engineering. He is generally interested in innovating mixed-signal,
RF, and mm-Wave integrated circuits and systems for communication, radar,
and bioelectronics applications.
Dr. Wang received National Science Foundation (NSF) CAREER Award in
2015, Roger P. Webb ECE Outstanding Junior Faculty Member Award in 2015,
and Lockheed Martin Dean’s Excellence in Teaching Award in 2015. He was the
award recipient of the 46th IEEE DAC/ISSCC Student Design Contest Winner
in 2009 based on his work of “An Ultrasensitive CMOS Magnetic Biosensor
Array for Point-Of-Care (POC) Microarray Application.” He was also a co-re-
cipient of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Best Student Paper Award (1st Place) as the students’ Ph.D. advisor in 2014.
Dr. Wang is an Associate Editor of the IEEE Microwave and Wireless
Components Letters (MWCL). He is currently a Technical Program Committee
(TPC) Member for IEEE Radio Frequency Integrated Circuits Symposium
(RFIC), IEEE Custom Integrated Circuits Conference (CICC), and IEEE
Biopolar/BiCMOS Circuits and Technology Meeting (BCTM). He is a member
of Sigma Xi, the IEEE Solid-State Circuits Society (SSCS), the IEEE Mi-
crowave Theory and Techniques Society (MTT-S), the IEEE Circuits and
Systems Society (CAS), and the IEEE Engineering in Medicine & Biology
Society (EMBS). He serves as the Chair of the Atlanta’s IEEE CAS/SSCS joint
chapter, which won the IEEE SSCS Outstanding Chapter Award in 2014.