GeMiC 2015 • March 16–18, 2015, Nürnberg, Germany

High Speed Static Frequency Divider Design with

111.6 GHz Self-Oscillation Frequency (SOF) in
0.13 µm SiGe BiCMOS Technology
U. Ali, M. Bober, A. Thiede A. Awny, G. Fischer
University of Paderborn, Warburger Str.100, 33098 IHP, Im Technologiepark 25, 15236
Paderborn, Germany Frankfurt(Oder), Germany
umair.ali@uni-paderborn.de awny@ihp-microelectronics.de

Abstract—A speed optimization scheme for static frequency
dividers based on master-slave flip-flops is presented. As a proof
of the concept, the design of a divide by two static frequency
divider in 0.13 µm SiGe BiCMOS technology (with ft > 300 GHz
and fmax > 450 GHz) is reported. The circuit exhibits the highest
self-oscillation frequency (SOF) of 111.6 GHz among the existing
SiGe technology based static frequency dividers. With single-
ended sine wave clock input, divider is operational from 6 to
128.7 GHz (limited by measurement equipment). At dual power
supply with Vcc = 3 V and Vee = -1.9 V, the circuit consumes 40 mA
per latch.
(Q3, Q4) differential pairs and collector nodes (X, Y) are
shown. The differential pairs are followed by two emitter
followers (EF’s) which provide enhanced decoupling
capability from the next stage and a slight peaking at higher
frequencies. The speed enhancement techniques are
investigated using this basic latch schematic and finally an
optimized circuit is fabricated to validate the findings.

Keywords — HBT, latch, SiGe, static frequency dividers

I. INTRODUCTION
The speed potential of SiGe technologies for millimeter-
wave applications is evaluated and compared by the
performance of static frequency dividers designed in these
technologies. The figures of merit like fT and fmax characterize
the transistor performance, but basic circuits like ring
oscillator and static frequency divider give good indication of
the achievable performance in the wide range of circuit
applications [1]. In particular, static dividers have traditionally
been used as a benchmark for the comparison of high speed
technologies. The highest operating frequency reported by
SiGe bipolar static dividers is 133 GHz [1]. A divider based on
InP DHBTs with fT > 530 GHz and fmax > 600 GHz using
inductive peaking operates even up to 200 GHz [2].
In this paper, a design flow of high speed static frequency
divider using 0.13 µm SiGe BiCMOS technology is discussed.
The effect of speed enhancement techniques such as double
emitter-followers [1], split-load [3], and asymmetric latch [4]
are investigated to optimize the circuit from the speed
perspective. The designed frequency divider is to be later
integrated into clock synthesizer circuitry for 160 Gbits/s 4:1
multiplexer (MUX).
II. CIRCUIT DESIGN
The proposed static frequency divider is based on a D-flip-
flop (consisting of two latches) connected with negative
feedback [1], [3], [6]. The schematic for one of the two latches
is shown in Fig. 1 where the sensing (Q1, Q2) and the latching
Fig. 1. Schematic of a latch with two Emitter followers
If no input clock signal is applied, a differential static
divider (with divider ratio two) can also be viewed as a ring
oscillator which oscillates at self-oscillation frequency (SOF)
and a signal at frequency ‘SOF/2’ appears at the output. The
efficacy of a particular speed enhancement technique is
compared on the basis of achieved SOF.
In schematic level simulations, an increase of 20% in SOF
was observed by adding second emitter follower in the latch
schematic. Similar kind of behavior has been reported in [1].
The voltage swing optimization at nodes ‘X’ and ‘Y’ has been
used in [5]. The simulation results show that a voltage swing
between 190 and 210 mV achieves the highest SOF. The speed
of the D-latch can be further increased by reducing the R1*Cout
time constant at nodes ‘X’ and ‘Y’. The capacitance at ‘X’ is
the parallel combination of collector-to--substrate capacitances
of Q1, Q3 and base-to-collector capacitance of Q8. The sizes
of the latch differential pair (Q3, Q4) and Q6 are scaled down

ISBN 978-3-9812668-6-3 241 © IMATech e.V. • Ratingen, Germany

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on April 09,2023 at 12:06:16 UTC from IEEE Xplore. Restrictions apply.
 GeMiC 2015 • March 16–18, 2015, Nürnberg, Germany

The circuit is laid-out symmetrically to minimize the effect

of common-mode noise. The physical length of interconnects
between the divider core and buffer has negative impact on
SOF (because of parasitic capacitances) so these are kept as
small as possible. The simulation results show that the SOF is
a strong function of capacitances at nodes ‘X’ and ‘Y’. Hence,
the metal connections at nodes ‘X’ and ‘Y’ are laid-out with
metal layers which offer less capacitance e.g. Metal 4 and
Metal 5. The chip photograph of the frequency divider is
shown in Fig. 3. The total area of the divider including bond
pads is 765×765 μm2.

Fig. 2. Size ratio of the sensing and latching branch vs SOF/2

by reducing their number of emitter fingers. The reduced

number of fingers lowers the collector-to-substrate capacitance
for the corresponding latching differential pair. The size of the
sensing differential pair and Q5 are kept constant. The size
ratio of 2-to-1 between the sensing and latching branch is
found to be optimum from both SOF and bandwidth point of
view. Fig. 2 shows the relation between size ratio and ‘SOF/2’.
Another method of reducing the time constant at collector
nodes of the latching pair is to split the load resistance R1 for
the sensing and latching pairs [3]. When the split-load
technique was applied on asymmetric latches, it was found less
useful because of the overall reduced bandwidth. Table I Fig. 3. Chip photograph of the static frequency divider
summarizes the speed enhancement techniques and their
effects on the performance of the circuit.
IV. MEASUREMENT RESULTS
Following the static frequency divider circuit, a 50 Ω output The measurements of the static dividers were done on wafer.
buffer was designed to provide 400 mVpp of swing at the Single-ended GSG and PGSGSGP (G: ground, S: signal, P:
output pads. power) probes were used for RF and DC connections
respectively. The choice of probes depends on the frequency
TABLE I. SUMMARY OF THE SPEED ENHANCEMENT TECHNIQUES
band of operation. Table II shows the summary of input and
Technique Used % inc. % inc. SOF output equipment (including probes) used at different
in SOF in BW (GHz) frequency bands to measure input sensitivity curve of the
divider.
1 EF No - - 75
TABLE II. SUMMARY OF MEASUREMENT SCHEME FOR DIFFERENT
2 EFs Yes 20 % 17 % 90 FREQUENCY BANDS (0-129 GHZ)

fIN Input source setup fOUT Output side

Voltage Swing
Yes 1% 1% 91.2 (GHz) (GHz) setup
optimization
0-50 Agilent 83650 + coax. 0-25 GSG probe +
cable + GSG probe coaxial cable +
Asym. sense and 50-75 Agilent 83650 + MW 25- spectrum
Yes 22 % 15% 111.6
latch branch ampl. + 4x multiplier 37.5 analyzer
module (HP83557A) + (MS2668C)
Split load tech. No 21% 10% 110 V- band GSG probe
75-110 Agilent 83650L +MW 37.5-
ampl. + 6x multiplier 40
III. TECHNOLOGY AND LAYOUT STRATEGY module (HP83558A) + 50-55 V_band probe +
The circuit is fabricated in IHP SG13G2 BiCMOS HBT W-band GSG probe V_band mixer +
technology. It is a self-aligned single poly-silicon technology *110- Agilent 83650 + MW 55- spectrum
129 ampl. + 6x multiplier 64.5 analyzer
with 0.13 µm min. lithographic emitter width and seven (MS2668C)
aluminum metallization layers (Metal 1 – Metal 5, Top module (HP83558A) +
W band GSG probe
metal 1, and Top metal 2). The technology has fT and fmax of *input power sensitivity curve is not calibrated
300 GHz and 500 GHz, respectively [7].

ISBN 978-3-9812668-6-3 242 © IMATech e.V. • Ratingen, Germany

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on April 09,2023 at 12:06:16 UTC from IEEE Xplore. Restrictions apply.
 GeMiC 2015 • March 16–18, 2015, Nürnberg, Germany

TABLE III. COMPARISON TO PREVIOUSLY PUBLISHED STATIC FREQUENCY DIVIDERS

[6] [3] [5] [8] [2] [1] This Work

Technology SiGe SiGe SiGe SiGe InP SiGe SiGe
Divide ratio 2 2 2 2 2 4 2
No Split-load Inductive Asymmetric Inductive No Asymmetric
Speed enhancement Peaking Latch Peaking Latch
Emitter follower stages 2 2 1 1 1 2 2
Power consumption / latch 112 mW 242 mW 122 mW 115 mW 228 mW 210 mW 196 mW
Maximum operating frequency 100 GHz 96 GHz 100 GHz 113 GHz 200 GHz 133 GHz >128.7 GHz
(GHz)
SOF (GHz) 70.34 GHz 70 GHz 77 GHz 80 GHz 172 GHz 98 GHz 111.6 GHz

Fig. 4 shows the measured input sensitivity curve of the

static frequency divider. At dual supply voltages of Vcc = 3 V
and Vee = -1.9 V, the circuit operates from 6 to 128.7 GHz.
The low-frequency response is limited by the slew-rate of the
sinusoidal input signal. The power consumption of a single
latch is 196 mW.
A comparison with the recently published static frequency
dividers is given in Table III. The measured maximum
frequency of operation for the proposed divider is comparable
to the fastest reported divider [1] in SiGe technology.
However, the SOF of the designed circuit is 111.6 GHz which
is higher than 98 GHz reported in [1]. In this paper, SOF has
been used to more fairly compare the performance of static
dividers because it depends solely on the circuit parameters.
On the other hand, the maximum operating frequency of the
divider was restricted by the test setup and the power available
from the signal source.
Fig. 4. Input power sensitivity curve of divider
ACKNOWLEDGMENT
The authors thank IHP for fabrication support. This work
was sponsored by DFG under project TH829/9-1.
REFERENCES
[1] H. Knapp, T. Meister, W. Liebl, D. Claeys, T. Popp, K. Aufinger, H.
Schafer, J. Bock, S. Boguth, and R. Lachner, “Static frequency dividers
up to 133 GHz in SiGe:C bipolar technology,” in Proc. BCTM’10,
Austin TX, 2010, pp. 29-32.
[2] M. D’Amore, C. Monier, S. Lin, B. Oyama, D. Scott, E.Kaneshiro, A.
Gutierrez-Aitken, and A. Oki, “A 0.25 μm InP DHBT 200 GHz+ static
frequency divider,” in Proc. CSICS’09, Greensboro, NC, 2009.
[3] A. Rylyakov and T. Zwick “96 GHz static frequency divider in SiGe,”
IEEE J. Solid-State Circuits, vol. 39, pp. 1712–1715, Oct. 2004.
[4] S. Trotta, H. Knapp, T. Meister, K. Aufinger, J. Böck, W. Simbürger,
A. Scholtz, “110-GHz static frequency divider in SiGe bipolar
technology,” in Proc. CSICS 2005 Digest, pp. 291-294.
[5] E. Laskin, S. Nicolson, P. Chevalier, A. Chantre, B. Sautreuil, and S.
Voinigescu, “Low-power, low-phase noise SiGe HBT static frequency
divider topologies up to 100 GHz,” in Proc. BCTM’06, Maastricht, The
Netherlands, 2006, pp. 235–238.
[6] A. Awny, L. Moeller, J. Junio, C. Scheytt, and A. Thiede, “Design and
measurement techniques for an 80 Gb/s 1-tap decision feedback
equalizer,” IEEE J. Solid-State Circuits, vol. 49, pp. 452–470, Feb.
2014.
[7] B. Heinemann, R. Barth, D. Bolze, J. Drews, G. G. Fischer, A. Fox, O.
Fursenko, T. Grabolla, U. Haak, D. Knoll, R. Kurps, M. Lisker, S.
Marschmeyer, H. Rücker, D. Schmidt, J. Schmidt, M. A. Schubert, B.
Tillack, C. Wipf, D. Wolansky, and Y. Yamamoto, “SiGe HBT
technology with fT/fmax of 300 GHz/500 GHz and 2.0 ps CML gate
delay,” IEEE Intl. Electron Device Meeting (IEDM), San Francisco, CA,
2010, pp. 688–691.
[8] S. Trotta, H. Li, V. P. Trivedi, and J. John, “A tunable flip flop-based
frequency divider up to 113 GHz and a fully differential 77 GHz push-
push VCO in SiGe BiCMOS technology,” in Proc. Radio Frequency IC
Symp. (RFIC’09), Boston, MA, 2009, pp. 47–50.

V. CONCLUSIONS
The design and characterization of a divide ratio two static
frequency divider working up to 128.7 GHz in a 0.13 µm SiGe
BiCMOS technology is reported. To the author’s knowledge,
the presented static frequency divider has the highest self-
oscillation frequency (SOF) among the published static
frequency dividers in SiGe technology.

ISBN 978-3-9812668-6-3 243 © IMATech e.V. • Ratingen, Germany

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY ROORKEE. Downloaded on April 09,2023 at 12:06:16 UTC from IEEE Xplore. Restrictions apply.