Analog Integrated Circuits and Signal Processing (2021) 107:227–238

https://doi.org/10.1007/s10470-021-01809-y (0123456789().,-volV)
(0123456789().,-volV)

MIXED SIGNAL LETTER

A DTMOS-based power efficient recycling folded cascode operational

transconductance amplifier
Amitkumar S. Khade1 • Sandeep Musale1 • Ravikant Suryawanshi1 • Vibha Vyas2

Received: 28 July 2020 / Revised: 3 January 2021 / Accepted: 7 February 2021 / Published online: 26 February 2021
Ó The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature 2021

Abstract
The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in
which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed
using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class
AB operation, an adaptive biasing technique comprising a flip voltage follower is used which boosts the dynamic current
and gain-bandwidth product of OTA. Conventional current mirrors are replaced with source degenerated non-linear current
mirrors to achieve a better slew rate. The conventional and proposed RFC structures are designed and simulated in a
standard 180 nm CMOS process at 1 V supply voltage. The proposed RFC OTA demonstrates a significant enhancement in
the performance parameter as 11 dB improvement in the gain as well as 290% more GBW and achieves a slew rate that is
nine times better compared to the conventional RFC.

Keywords Superclass AB stage  Dynamic threshold MOSFET (DTMOS)  FVF adaptive biasing  Slew rate enhancement 
Recycling folded cascode amplifier

1 Introduction enhancing the performance of such amplifiers, especially

The life span of battery-operated portable devices can be
significantly prolonged with the use of power-efficient
analog circuits. Worldwide, there is a growing demand for
such analog circuits. An OTA is a primary element in many
analog circuits ranging from simple filters to complex
programmable analog circuits [1–3]. A single-stage
amplifier offers better power efficiency and is well suited
for low voltage, low power applications. However,
& Amitkumar S. Khade
amitkumar.khade@cumminscollege.in
Sandeep Musale
sandeep.musale@cumminscollege.in
Ravikant Suryawanshi
ravikant.suryawanshi@cumminscollege.in
Vibha Vyas
vsv.extc@coep.ac.in
1
Electronics and Telecommunication Department, Cummins
College of Engineering for Women, Pune 411005, India
2
Electronics and Telecommunication Department, College of
Engineering Pune, Pune 411005, India
gain and speed at reasonably low supply voltage, turns out
to be a daunting task in sub-micron CMOS technology. The
cascoding technique significantly improves the output
resistance of amplifiers resulting in high DC gain. Never-
theless, the cascoding method reduces the output voltage
swing. The current folding technique alleviates this draw-
back and provides a large DC gain with marginally good
output voltage swing. However, the requirement of addi-
tional current sources at the folding nodes of an amplifier
drastically increases power consumption. The techniques
used to improve the performance of the folded cascode
(FC) amplifier include a multipath scheme [4], a current
starving technique [5], positive feedback technique [6] and
current recycling concept [7]. Nowadays, a current recy-
cling folded cascode (RFC) OTA has gained complete
attention since it demonstrates a significant enhancement
over the conventional FC counterpart structure without
increasing the area and power budget.
Applications such as low-dropout regulators (LDO),
data converters, switch capacitor circuits, anti-aliasing fil-
ters need an OTA with a large gain-bandwidth product
(GBW), DC gain and slew rate [8, 9]. Like conventional

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228 Analog Integrated Circuits and Signal Processing (2021) 107:227–238

FC OTAs, the maximum output current in RFC structures

is limited by their biasing current [10]. An improvement in
RFC amplifier can be achieved by using a considerable
value of biasing current, which leads to large power con-
sumption. To overcome this drawback and achieve better
power efficiency, class AB operation is adopted in RFC
amplifiers. Performance enhancement of an RFC OTA
using a class AB operation is reported in [11, 12]. To
achieve class AB operation, the constant DC biasing cur-
rent of OTA is implemented using an adaptive biased cir-
cuit comprising a flip voltage follower (FVF). Additionally,
local common-mode feedback (LCMF) techniques utilizing
a couple of matched resistors are opted to improve the Fig. 1 Conventional RFC OTA
transconductance of an OTA circuit.
The functioning of the reported superclass AB RFC
structure entirely depends on the resistance value of two
matched resistors that are highly sensitive to temperature
and process variation. Further, the requirement of a large
value resistor to obtain marginally useful transconductance
increases power consumption and the die area of an OTA
circuit. Implementation of such a large value resistor in a
low-cost CMOS process is not a viable option. To address
this problem, this study proposes a superclass AB RFC
structure using source degenerated current mirrors. Addi-
tionally, to extend the current efficiency of the proposed
OTA, Dynamic Threshold MOSFET (DTMOS) is utilized
to implement the input stage of the proposed OTA.
This study proposes a class AB RFC structure consisting Fig. 2 Super class AB RFC OTA
of a non-linear current mirror and a DTMOS differential
pair to enhance the current efficiency of a conventional Despite these advantages, the conventional RFC shows
RFC OTA. The remaining paper is segmented in the fol- poor current efficiency since the maximum output current
lowing manner: Sect. 2 discusses LCMF based superclass is restricted by its biasing current.
AB RFC structure. Sects. 3 and 4 introduce DTMOS AB-RFC OTA addresses this drawback by adopting
operation and structure proposed respectively. The per- Class AB operation where the biasing current of the con-
formance parameters of the presented OTA are discussed ventional RFC is replaced by an adaptive biasing tech-
in Sect. 5. To support theoretical discussion, simulation nique. FVF is used to implement an adaptive biasing
outcome is provided in Sect. 6. The paper ends with con- technique. This technique significantly boosts the dynamic
clusion of the study. current of AB-RFC OTA not limited by its biasing current.
In AB-RFC OTA, maximum output current generated is
proportional to Vid4 instead of Vid in a conventional RFC.
2 LCMF based superclass AB RFC structure Moreover, LCMF further increases dynamic current with-
out scaling the static current. As shown in Fig. 2, LCMF
The conventional RFC and the recently reported superclass technique feeds the drain voltage of transistors M3C and
AB RFC (AB-RFC) OTA proposed in [7] and [11, 12] are M4C back to the common gate terminal of transistors M3B
shown in Figs. 1 and 2, respectively. As shown in the and M4B utilizing two resistors that match of equal value
figures, both the topologies used PMOS at the input stage R1 = R2 = R. The active current mirrors M3A-M3B and
to achieve better noise performance. Additionally, the M4A-M4B behave as conventional current mirrors in the
folding node current sources of a conventional FC OTA are absence of an input signal. An immense value of the input
replaced by active current mirrors with a gain factor of K signal leads to a voltage drop across R1 and/or R2 which
and are reconnected to the input stage transistors. To gets added to the gate terminal of transistors M3A and/or
achieve area and power efficiency, a value of factor K is M4A, yielding a large output current. This improves the
adjusted to 3, for which the conventional RFC shows 100% slew rate of an OTA without affecting the quiescent
transconductance improvement over its FC counterpart.

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Analog Integrated Circuits and Signal Processing (2021) 107:227–238
current. In addition to the dynamic performance, the LCMF
technique also enhances the small-signal performance by
providing a small signal current gain.
If symbols Gm1 and Gm2 represent transconductance of a
conventional RFC and AB-RFC OTA shown in Figs. 1
and 2, then the transconductance for both the OTAs is
expressed as:
Gm1 ¼ ð1 þ K Þgm1a ð1Þ
Gm2 ¼ 2ð1 þ gm3a RÞgm1a ð2Þ
Here, the symbols gm1a and gm3a indicate transconduc-
tance of transistors M1A and M3A, respectively. For
h i
R [ K  1=2gm3a AB-RFC OTA provides larger
transconductance compared to RFC OTA. The static and
dynamic performances of the AB-RFC OTA are mainly
decided by LCMF matching resistors, which are sensitive
to process and temperature variations. Additionally, opti-
mization of R to decide LCMF current gain is a challenging
job in a low-cost submicron CMOS process.
To resolve dependency of AB-RFC OTA on the resis-
tance value, an alternative approach to implement AB-RFC
OTA is proposed in this paper. It represents a superclass
AB RFC OTA using a source degenerated current mirror
instead of the LCMF technique without compromising its
performance. To extend current efficiency and achieve
low-voltage compatibility, DTMOS based input stage is
adopted.
3 Proposed new superclass AB RFC OTA
3.1 Dynamic threshold MOSFET operation
In modern CMOS technology, to keep pace with the
aggressive downscaling and to maintain reliability of MOS
transistors necessarily reduces the supply voltage of the
transistors [10]. In the sub-micron CMOS process, reduc-
tion in the supply voltage is mainly restricted by the
threshold voltage of the MOS transistor [10]. Moreover, the
reduced supply voltage also reduces the input / output
voltage swing of analog circuits. Acceptance of a body
driven MOS transistor (BD-MOST) benefits a low voltage
operation with an equitable voltage swing by adjusting
threshold voltage. High-performance amplifier structures
using BD-MOST are reported in [10, 13–15]. Nevertheless,
BD-MOST provides lower transconductance, low cut-off
frequency, higher mismatch and more extensive area. The
shortcomings of BD-MOST mentioned above have a direct
effect on the functioning of OTA such as a reduced
intrinsic gain and increased input-referred noise as bulk
transconductance is 4 to 5 times lesser in comparison to
gate transconductance. To overcome these weaknesses of
229
BD-MOST and enhance the overall transconductance, a
dynamic threshold MOST is adopted in [16–19].
A MOSFET using a dynamic body bias technique, i.e.,
DTMOS transistor as well as an equivalent small-signal
model are shown in Figs. 3(a) and (b) below:
As shown in the figure, both the gate and body terminals
are bound together and utilized as input terminals. In this
configuration, the threshold voltage of the MOS transistor
appears to be a function of its input signal. Any variation in
the input signal reflects a similar variation in the body
signal and induces a body effect which dynamically
changes the threshold voltage of the transistors. In the
DTMOS transistor, the contribution of both the gate and
the body transconductance enhances the effective
transconductance of the MOS transistor, which is expres-
sed as follows:
Gmeff ¼ gm þ gmb ffi ð1 þ gÞgm ð3Þ
where, gm and gmb symbolize the gate and body transcon-
ductance respectively and parameter g ffi 0:2  0:4. From
(3), DTMOST provides 20% to 40% transconductance
enhancement compared to the traditional gate transcon-
ductance. Additionally, DTMOST offers more reduction in
the threshold voltage, subthreshold swing and superior
control over short channel effects compared to the gate
driven MOST. The potential advantages of the DTMOS
transistor strongly build the foundation for its acceptance to
implement an input stage of the proposed OTA.
3.2 Proposed new superclass AB RFC OTA (NRFC
OTA)
The presented new superclass AB RFC OTA termed as
NRFC OTA is shown in Fig. 4.
For the input stage transistors M1A,B and M2A,B, the
body and gate terminals are tied together to achieve a low
voltage operation and high current efficiency since in
DTMOS, the current is modulated by gate and body
transconductance. In DTMOS transistor, though the
source-body junction diode gets forward biased to some
extent, a significant diode current conduction can be con-
trolled by limiting the gate voltage to one diode voltage. To
further enhance the current efficiency of the proposed
OTA, the active current mirrors of the conventional RFC
OTA are replaced with source degenerated non-linear
current mirrors. Like AB-RFC, FVF based adaptive biasing
is used in NRFC OTA. A biasing voltage, VBIAS, of
degeneration transistors M3c and M4c are adjusted to boost
the dynamic current in the active load of the input stage.
Under quiescent conditions, transistors M3B–M4B are
biased in the saturation region and degeneration transistors
M3C–M4C in the ohmic region.
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230 Analog Integrated Circuits and Signal Processing (2021) 107:227–238

Fig. 3 a DTMOS transistor

b Small-signal model of
DTMOS transistor

(a) DTMOS transistor

(b) Small-signal model of DTMOS transistor

Fig. 4 The proposed new class superclass AB RFC OTA (NRFC OTA)

Under a quiescent condition, every transistor at the input selecting a small value of IB. A large value of the input
stage conducts an equal quiescent current (static current) of signal boosts the dynamic current of OTA not limited by
the value of IB/2 since VSG1a = VSG1b = VSG2a = VSG2b. IB. The usage of FVF circuit and DTMOS transistor makes
Further reduction in static current can be achieved by OTA suitable for low voltage operation.

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Analog Integrated Circuits and Signal Processing (2021) 107:227–238 231

(
4 Small signal performance of NIRFC OTA 2kTc gm3a þ gm9
v2oNRFC ¼ 
ðgm1a þ gmb1a Þðgm1a þ gmb1a Þð1 þ K Þ2
For the proposed NRFC OTA, small-signal analysis is  2
presented in this section. 1 þ 2K 2 gm3b K
þ þ g
ð1 þ K Þ2 ðgm1a þ gmb1a Þ 1 þ K
A. Small signal transconductance, gain and GBW
ð10Þ
If symbol Gm represents transconductance of NRFC
In (10), the overall OTA transconductance improvement
OTA, then the transconductance is given as:
leads to lower input-referred noise for the proposed NRFC
Gm ¼ 2ð1 þ K Þð1 þ gÞgm1a ð4Þ OTA. A higher value of factor K further reduces input
Factor 2 in (4) is because of additional transconductance noise as the dc gain increases, but it degrades the phase
supplied by the adaptive biasing circuit. For factor K = 3, margin.
the transconductance of the RFC and the NRFC is given as: C. Stability analysis
GmRFC ¼ 4gm1a ð5Þ
The stability of OTA is primarily decided by its phase
GmNRFC ¼ 8ð1 þ gÞgm1a ð6Þ margin value, which is a function of the number of poles
DTMOS transistor drives more drain current due to and zeros introduced in its transfer function. Figure 5
reduced threshold voltage and hence exhibits a consider- shows the pole-zero location for NRFC OTA.
able value of gm1a compared to the conventional RFC Like RFC OTA, NRFC OTA has a dominant pole
OTA. Also, an adjustment of VBIAS to obtain a quiescent P1 ¼ 1=Rout CL at the output node. Moreover, two non-
condition in the NRFC may show higher transconductance. dominant poles at the current recycling mirror and folding
The output impedance of the NRFC OTA can be nodes are given in (11) and (12) as:
expressed as: 1 gm3b;4b
Rout ¼ gm6 ro6 ðro2a jjro4a Þjj gm8 ro8 ðro10 Þ ð7Þ P2 ¼  ¼ ð11Þ
RP CP ð1 þ K ÞCgs3a;4a
An improved transconductance leads to enhanced gain gm5;6
P3 ¼ ð12Þ
since the small-signal gain is the product of transconduc- Cgs5;6
tance along with output resistance.
and one zero associated with the current recycling
GBW expression for RFC and NRFC is as given below:
mirror is expressed in (13) as:
ðK þ 1Þgm1a
GBWRFC ¼ ð8Þ Z1 ¼ ½1 þ KP2 ð13Þ
2pCL
2ðK þ 1Þð1 þ gÞgm1a where gmi and Cgsi are transconductances and gate-
GBWNRFC ¼ ð9Þ source capacitances of the corresponding transistors as
2pCL
indicated in NRFC OTA. This pole-zero pair P2  Z1
An improved transconductance leads to the enhanced which is at the recycling current mirror node is related to
GBW for NRFC OTA. Further, enhancement in GBW can NMOS transistors, and therefore located at a relatively high
be achieved by either selecting a small value of the load frequency. The position of the two non-dominant poles P2
capacitor CL or an immense amount of the factor K. and P3 is interchangeable depending on limitations
However, these choices degrade the phase margin and
affect the stability of OTA.
B. Noise
It is one of the main parameters in the design of low
power OTA circuits. For a MOS transistor, it is possible to
show the thermal noise current as:
i2o ¼ 4kTcgm
where k is a representation of the Boltzmann constant, T is
a representation of absolute temperature and the transcon-
ductance of transistors is represented by gm. The factor c
varies from 1/2 to 2/3 from weak inversion to strong
inversion. For the presented NRFC OTA, the input-referred
thermal noise can be expressed as shown in Eq. 10:
Fig. 5 Pole-zero location for NRFC-OTA

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232 Analog Integrated Circuits and Signal Processing (2021) 107:227–238

imposed by the design. For the NRFC OTA to achieve as VGS3A = VGS3B ? VDS3C, leading to a substantial cur-
stability, the condition P2 [ 3GBW must be satisfied. rent in M3A which is available at the output through M5
Here, it is possible to express a phase margin as: and M7-M10 respectively. The current through M3A is:
  "sffiffiffiffiffiffiffiffi #
GBW b3A 2I3B 2ID3c 1
PM ¼ 1800  tan1 I3A ¼ þ  ð18Þ
f p2 2 b3B k3c b3c ðVbias  VTH Þ2 k3c
 
ðg þ gmb1a Þ Cgs3a
PM ¼ 1800  tan1 2 m1a ð K þ 1Þ 2 where k3c 6¼ 0 and Vbias [ VTH . Since, Iout ¼ I3A  I4A .
gm3b CL
From (16) and (17), an approximate theoretical slew rate
ð14Þ (SR) for the proposed NRFC can be expressed as:
From (11) and (14), it can be noted that the large value " #2
of factor K significantly increases the value of capacitor b4A b2B 2
SRþ ¼ V ð19Þ
Cgs3,4a and shifts the non-dominant pole P2 in a low-fre- 2CL k4A b4A ðVbias  VTH Þ2 id
quency region. This results in a significant decrease in the " #2
phase margin. b3A b1b 2
SR ¼ V ð20Þ
2CL k3A b3A ðVbias  VTH Þ2 id

5 Large signal analysis From (19) and (20), for a large value of Vid, SR is
proportional to Vid4 . However, a practical value of SR is
To describe the large signal operation, the drain current of lower than its theoretical limit since degenerated transistors
MOSFET biased in the strong inversion and ohmic region M3C and M4C will not enter in deep saturation. Moreover,
is expressed as: compared to the conventional RFC, the proposed NRFC
OTA shows a larger SR without increasing static power.
ID ¼ bðVGS  VTH Þ:VDS ð15Þ
where, bi ¼ lp Cox ðW=LÞi and VDSi is a transconductance
parameter and a drain to the source voltage of the respec- 6 Simulation results
tive transistor. With an assumption that voltage VDS is
small, the quadratic term has been neglected in (13). Fur- This section demonstrates the experimental environment
ther, for a transistor biased in strong inversion and satu- along with a summary of results for the conventional RFC
ration, the drain current is as: and the proposed NRFC OTA structures.
b
ID ¼ ðVGS  VTH Þ2 ð1 þ kVDS Þ ð16Þ 6.1 Simulation environment
2
where k represents the channel length modulation param- The conventional RFC and the presented NRFC OTA are
eter. Assuming all the input stage transistors and driving simulated utilizing the standard 0.18um CMOS process. A
transistors M1C, M2C of FVF are matched, for a large Vid, biasing current of 10uA and supply voltage of value 1 V is
currents in the input stage transistors are given by: used to validate the performance of both the OTA struc-
sffiffiffiffiffiffiffi !2 tures. To achieve a fair tradeoff between the speed and the
b1b Ib consumption of power, each one of the transistors is biased
IM1B ¼ þ Vid ; Vid \0
2 b1b in the moderate inversion region. A unity gain configura-
sffiffiffiffiffiffiffi !2 tion test setup is made use of to test the open-loop behavior
b Ib of OTAs. The MOS sizing ratio used during the simulation
IM2B ¼ 2b þ Vid ; Vid [ 0 ð17Þ is given in Table 1.
2 b2b
The achieved AC responses of the RFC and the pro-
For a large value of input signal (Vid [ 0), input stage posed NRFC are presented in Fig. 6. The proposed NIRFC
transistors M1A and M1B shut off, and the entire current OTA provides GBW of 3.07 MHz and a gain of 79.37 dB
flows through M2B. For a fixed value of VGS3c, a large drain whereas the RFC structure offers GBW of 0.78 MHz and a
current (ID3C) forces the degeneration transistor M3C into a gain of 67.91 dB. The enhancement in the gain and GBW
saturation region causing a very large VDS3C. This action supports the theoretical discussion of transconductance
increases the gate voltage of transistor M3A notably, given improvement in NRFC OTA. However, a phase margin

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Analog Integrated Circuits and Signal Processing (2021) 107:227–238 233

Table 1 Transistors Aspect

Transistor W/L (um) Transistor W/L (um) Transistor W/L (um) Transistor W/L (um)
Ratio for NRFC OTA
M1a, M1b 190 / 0.6 M3b, M4b 60 / 0.6 M1d, M2d 60 / 0.6 M9, M10 200 / 0.6
M2a, M2b 190 / 0.6 M3a, M4a 180 / 0.6 M5, M6 120 / 0.6
M3c, M4c 60 / 0.6 M1c, M2c 190 / 0.6 M7, M8 200 / 0.6

Fig. 6 AC responses of RFC and proposed NIRFC OTA structures

degradation is observed for the proposed NRFC OTA. RFC
OTA shows 13.37° advancement in the phase margin
compared to the proposed NRFC OTA.
To test a large signal response, a square wave of
650 mV, 5 MHz is applied at the input terminal of both the
OTAs and the obtained response is shown in Fig. 7. Due to
class AB operation, the proposed NRFC OTA offers a
much better transient response compared to RFC OTA. The
average slew rates measured for NRFC and RFC structures
are 3.625 V/us and 0.40 V/us, respectively. The proposed
OTA offers a slew rate approximately nine times larger
than RFC OTA. The noticed 1% settling time for RFC and
NRFC OTA is 1.58us and 172.6 ns respectively.
The typical mode response of the RFC and the presented
NRFC structures are depicted in Fig. 8. RFC OTA offers a
reasonably good common-mode response compared to
NRFC OTA and shows advancement of 6.35 dB. The
lower impedance introduced by FVF is the primary reason
for the common-mode gain degradation in the proposed
NRFC structure. Thanks to the differential mode gain,

Fig. 7 Large signal response of

RFC and the proposed NRFC
structure

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234
Fig. 8 Common mode response of RFC and the proposed NRFC OTA
Fig. 9 Noise performance of RFC and the proposed NRFC OTA
which helps to achieve better CMRR in the NRFC and
shows an improvement of 5.1 dB compared to RFC OTA.
The simulated input-referred noise spectral density for
RFC and the proposed NRFC OTA is presented in Fig. 9.
For the bandwidth of 1 Hz–10 MHz, the equivalent input-
referred noise of the RFC and the NRFC OTA is 28.72 and
10.99 nV/sqrt (Hz) respectively at 100KHz. An improve-
ment in effective transconductance brings down the input-
referred noise to a great extent in the NRFC OTA. Further,
the use of DTMOS transistor for employing an input stage
certainly enhances the input common-mode range (ICMR)
of the proposed OTA significantly, as shown in Fig. 10.
The performance parameters obtained for RFC and the
proposed NRFC OTA are summarized in Table 2. The
proposed NRFC provides a noticeable improvement in the
slew rate, GBW and the gain in comparison to RFC OTA
with a slight degradation in the phase margin. The effect of
the variation of the process as well as the temperature on
the performance parameters of the NRFC OTA is sum-
marized in Tables 3 and 4, respectively.
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Analog Integrated Circuits and Signal Processing (2021) 107:227–238
FoM1 specifies small signal current efficiency whereas
FoM2 specifies large signal current efficiency. The pro-
posed modification greatly enhances the small signal and
large signal current efficacies.
For the verification of the robustness of the suggested
NRFC OTA against the process and the mismatch, Monte
Carlo simulation for GBW and slew rate is conducted for
1000 run, and it is depicted in Fig. 11.
To demonstrate how capable the proposed OTA is,
Table 5 shows a comparison of the NRFC OTA with OTA
topologies that have been published recently.
7 Conclusions
This study presents a superclass AB RFC OTA imple-
mented utilizing a source degenerated non-linear current
mirror and a DTMOS based input stage. The proposed
OTA structure offers a significant enhancement in the
small as well as large signal current efficiency.
Analog Integrated Circuits and Signal Processing (2021) 107:227–238 235

Fig. 10 ICMR response of RFC and the proposed NRFC OTA

Table 2 Key Parameter Simulation Summary of RFC and NRFC Table 4 Impact of temperature variation on NRFC OTA parameters
OTA
Parameter T = - 40° T = 27° T = 0° T = 40° T = 90°
Parameter RFC NRFC
Gain (dB) 62.72 79.37 74 81.15 84.41
Supply voltage (V) 1 1 GBW (MHz) 3.86 3.07 3.77 3.61 3.33
Load capacitor (pF) 50 50 PM (Deg) 70.54 71.76 71.74 71.66 69.90
Gain (dB) 67.91 79.37 SR ? (V/us) 0.84 4.94 2.65 5.89 –
GBW (MHz) 0.79 3.078 SR- (V/us) 1.2 2.31 2.00 2.21 0.684
CMRR (dB) 136.67 141.77 CMRR (dB) 137.63 141.77 143.94 140.68 137.03
Positive SR (V/us) 0.393 4.94 PSRR (dB) 82.72 98.67 94.32 100.15 89.29
Negative SR (V/us) 0.416 2.31
PSRR ? (dB) 86.29 98.67
PSRR—(dB) 73.9 80.88
Offset voltage (mV) 58.67 22.41 Additionally, the proposed structure shows excellent
Phase margin (Degree) 85.13 71.76 improvement in performance parameters like an 11 dB
Equivalent input noise (nV/sqrt(Hz) @100KHz 29.79 10.99 enhancement in gain, 3.5 times larger GBW and nine times
1% Settling time (s) 1.58u 172.65n better slew rate compared to RFC OTA. However, the
ICMR (mV) 620 950 performance enhancement is obtained with approximately
THD @ 300mVpp, 500 kHz (dB) - 24.31 - 41.78 28% extra power in comparison to the conventional RFC
Estimated area (um2) 1440 1740 OTA due to the more dynamic current provided by the
Power (uW) (VDD x IDD) 20.85 26.4 adaptive biasing circuit.
FoM1 (MHz pF/mA) 3950 15,390
FoM2 [(V/us pF) / mA] 2000 18,125
FoM1 = [GBW x Load capacitor] / biasing current
FoM2 = [Avg. SR x Load Capacitor] / Biasing Current

Table 3 Impact of process variation on NRFC OTA parameters

Parameter FF FS SF SS

Gain (dB) 86.21 61.47 62.10 54.60

GBW (MHz) 3.85 3.54 2.85 2.60
PM (Deg) 71.37 62.13 72.57 66.58
SR ? (V/us) 4.93 4.14 – 4.80
SR- (V/us) 8.92 9.30 – 0.328
CMRR (dB) 130.63 113.91 109.67 114.59
PSRR (dB) 104.75 81.96 81.34 68.07

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236 Analog Integrated Circuits and Signal Processing (2021) 107:227–238

Fig. 11 a Monte Carlo analysis

of GBW b Monte Carlo analysis
of positive SR c Monte Carlo
analysis of negative SR

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Analog Integrated Circuits and Signal Processing (2021) 107:227–238 237

Table 5 Comparison of the proposed NRFC OTA with recently published OTA structures
Parameter [4] [8] [10] [11]a [12] This work

Supply (V) 1 1 0.6 1.0 1.8 1

Technology (um) 0.18 0.18 0.18 0.5 0.18 0.18
CL (pF) 15 30 20 70 50 50
DC gain (dB) 66.9 80.3 75.39 76.8 85.2 79.37
GBW (MHz) 6.4 10.2 0.0742 3.4 1.91 3.07
PM (Deg) 76.2 80.4 78.86 75.1 78.6 71.76
SR ? (V/us) 1.86 1.73 0.057 13.2 5.3 4.94
SR- (V/us) – 1.82 0.056 25.3 5.5 2.31
1% ST (ns) 67 136 7870 120 348 172.65
CMRR (dB) – – 136.49 112 132.2 141.77
PSRR (dB) – – 78.23 92 85 89.77
Input noise 560 @ 1 Hz 22 @ 10 MHz 209.36 @ 40KHz 23 @ 1 MHz 27.2 @ 100KHz 10.99 @ 100KHZ
(nV/sqrt(Hz)
FoM1 1920 7650 4950 23,800 477,500 15,350
FoM2 558 1330 379 134,700 13,500 18,125
a
Fabrication result

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123
238
Publisher’s Note Springer Nature remains neutral with regard to
jurisdictional claims in published maps and institutional affiliations.
Amitkumar S. Khade received
his Ph.D. degree and Master of
Engineering from Savitribai
Phule Pune University and Sant
Gadge Baba Amaravati Univer-
sity, Amaravati, India in 2020
and 2007 respectively. Cur-
rently, he is working as Assis-
tant Professor at Cummins
College of Engineering for
Women, Pune, which is an
autonomous institute affiliated
to Savitribai Phule Pune
University, Pune. His area of
interest is design of low power
analog integrated circuits like Gm-C filter, analog to digital converter,
low dropout regulator etc.
Sandeep Musale received his
Ph.D. degree and Master of
Engineering and B.E. from
Savitribai Phule Pune Univer-
sity in 2015 and 2008 respec-
tively. Currently, he is working
as Professor at Cummins Col-
lege of Engineering for Women,
Pune, which is an autonomous
institute affiliated to Savitribai
Phule Pune University, Pune.
His main research work was in
the field of Digital Image pro-
cessing - texture analysis. His
area of interest is Signal Pro-
cessing, Microelectronics and Low power analog integrated circuits.
123
Analog Integrated Circuits and Signal Processing (2021) 107:227–238
Ravikant Suryawanshi com-
pleted his Master of Technology
in Digital Systems from College
of Engineering Pune (COEP) in
2012 and his bachelors from
Savitribai Phule Pune Univer-
sity in 2009. Currently, he is
working as Assistant Professor
at Cummins College of Engi-
neering for Women, Pune which
is an autonomous institute affil-
iated to Savitribai Phule Pune
University, Pune. His area of
interest is low power, high
speed CMOS circuit Design.
Vibha Vyas received the PhD
degree and ME Degree from
College of Engineering, Pune
(COEP), under University of
Pune in 2010 and 2002 respec-
tively. Her main work was
research in the field of geomet-
ric transform invariant texture
analysis. At present she is serv-
ing as Associate Professor at
Electronics and Telecommuni-
cation Engineering Department
of College of Engineering Pune
(COEP), which is an autono-
mous institute of Government of
Maharashtra, India. Her areas of interests are pattern recognition,
texture analysis, signal processing, coding schemes, VLSI - embed-
ded systems and antenna. She is guiding many PhD and M.Tech
students in the said domain.