electronics

Article
Power Efficient Fully Differential Bulk Driven OTA
for Portable Biomedical Application
Saleha Bano * ID
, Ghous Bakhsh Narejo and Syed Muhammad Usman Ali Shah
Electronic Engineering Department, NED University of Engineering and Technology, Karachi 75270, Pakistan;
narejo@neduet.edu.pk (G.B.N.); uashah68@neduet.edu.pk (S.M.U.A.S.)
* Correspondence: saleha@neduet.edu.pk; Tel.: +92-333-375-7328

Received: 19 February 2018; Accepted: 16 March 2018; Published: 20 March 2018

Abstract: This paper presents a power efficient, bulk driven, source degenerated fully differential
operational transconductance amplifier (OTA), operating in the subthreshold region. The input part
of the OTA consists of a bulk driven source degenerated differential pair and cross coupled transistors
to improve the linearity of OTA. It consists of a bulk driven pair to reduce the supply voltage and to
improve the linearity. The proposed fully differential OTA has utilized self-cascode current mirror
loads which increases the output impedance and hence the overall intrinsic gain. A subthreshold
region is adopted to reduce the power consumption of the circuit. For a 200 mVpp sinusoidal input at
100 Hz, a total harmonic distortion (THD) of −58.56 dB is achieved. The gain, gain bandwidth (GBW),
phase margin (PM) and gain margin (GM) values obtained were 48.4 dB, 3.1 KHz, 80◦ and 19.01 dB,
respectively. The common mode rejection ratio (CMRR), power supply rejection ratio (PSRR) and
slew rate +/− values were 146.3 dB, 83 dB and 99.56/100 V/ms, respectively. The circuit is capable of
operating under a supply voltage of 0.8 V with a power consumption of 59.04 nW, which proves that
the circuit is suitable for portable biomedical devices. The proposed circuit is simulated in CADENCE
environment virtuoso using LFoundry 150 nm Complementary metal oxide semiconductor (CMOS)
process technology.

Keywords: power efficient; source degenerated; fully differential; portable devices; bulk driven; self
cascode; total harmonic distortion

1. Introduction
With the increasing demand for portable battery operated biomedical devices, there is a growing
need for the development of new design techniques for low voltage (LV), low power (LP), integrated
circuits (IC) [1]. The biomedical field is rapidly changing and moving towards portability; thus, low
power consumption is highly desirable for devices which monitor patients throughout the day [2].
Biomedical devices should be portable and durable due to the constraints of avoiding frequent
replacement of batteries and having power efficient circuits as well as low supply voltages so that these
devices can be used for a prolonged period of time [3]. Keeping the size and weight of the devices
as small as possible without affecting the quality is extremely important; therefore, it is desirable to
use as few batteries as possible, which demands low voltage operations [4]. Low voltage operation
is also demanded because there is a continued down-scaling of processes. As the channel length of
the metal oxide semiconductor (MOS) transistor is scaled down, the gate-oxide thickness becomes
only several nanometers thick, and the supply voltage has to be reduced in order to ensure device
function and reliability. Nowadays, the allowable supply voltage has gone below 1 V [5]. Not only
this, there is an increasing density of components on the chip, and a silicon chip can only have a
limited amount of power per unit area. Since the increasing density of components allows for more
electronic functions per unit area, the power per electronic function has to be lowered in order to

Electronics 2018, 7, 41; doi:10.3390/electronics7030041 www.mdpi.com/journal/electronics

Electronics 2018, 7, 41 2 of 19

prevent overheating of the chip; thus LV LP designs are necessary [6]. Different design techniques have
been proposed in the literature to reduce the supply voltage as well as the power consumption [7–9],
but the reduction in the threshold voltage (Vth ) has not been reduced by the same amount. With a
low supply voltage, the threshold voltage is the main limitation in designing of low voltage analog
integrated circuits [10]. This issue has been resolved by using the low threshold voltage MOS-like
flipped voltage flower [11], the floating gate [12], the pseudo differential approach [13], the bulk driven
MOS [14], the sub-threshold operation [15], etc. Out of these methods, sub-threshold operation is
the best choice for low voltage, low power and low frequency biomedical applications. Bulk driven
technique is also one promising approach for low voltage operations as it is compatible with the CMOS
process and does not require any change in the conventional MOS transistor [16]; this not only allows
for a large signal swing, but also a reduced open loop gain and unity gain bandwidth (UGBW) [17].
It is suitable for low voltage operations as it removes the threshold voltage from the signal path, but
its bulk source transconductance (gmb ) is 3–5 times smaller than the gate source transconductance
(gm ) [18], and it increases the input referred noise. A low GBW does not matter for biomedical low
frequency signals, but its intrinsic gain is reduced [7].
The operational transconductance amplifier (OTA) is one of the most important building blocks
used in various applications, such as data converters, oscillators, continuous time filters and analog
to digital converters [19]. One drawback of OTA is its limited linear range which has to be
increased to reduce the distortion at the output [20]. Bio signals, such as the electrocardiogram
(ECG), electroencephalogram (EECG) and electromyogram (EMG) are low power, low voltage signals.
Different bio signals have different amplitudes and frequencies ranging from 1 uV to 500 mV with
low frequencies up to a few KHz. Various design techniques have been reported in recent years to
achieve transconductance in the order of a few nA/V and to enhance the linear range, such as input
attenuation [21], source degeneration [22], cross coupled differential pairs [23] and the adaptive biasing
technique [24]. Bulk driven MOS transistors were used in [25] to control the cancellation factor, and the
transconductance was linearly adjusted by bulk voltage. A feed-forward technique was used in [26] to
cancel out the third order nonlinear component of OTA, but its improved performance was achieved at
the expense of high noise and increased power. Source degeneration, nonlinear term cancellation and
current division technique was used in [27] to improve the linear range up to +/− 0.4 V under a supply
voltage of 1 V. The linearity of OTA is an important issue because the overall system performance
is determined by the linearity of OTA. This issue becomes challenging when low voltage and low
power are the major concerns [28]. The use of complex architecture to enhance the linear range has
drawbacks since it increases noise, mismatches and the chip area, which degrades the performance
of the circuit. OTA, operated in the subthreshold region, is associated with low voltage, low power
circuits, as it favors LV design due to its reduced VDS of about 78 mV, rather than the 200 mV that
is required for strong inversion saturation MOS [17]. In the subthreshold region, OTA has a narrow
linear range, because in this region, the MOS transistor depends exponentially on the voltage. Source
degeneration is the one of the simplest methods used to linearize the OTA; it uses passive resistors to
enhance the linearity, but these passive resistors can occupy a large area so can be replaced with an
MOS, operated in the triode region. This reduces the distortion component and the transconductance
value as well [29].
The objective of this research is to design a power efficient, low voltage circuit, suitable for
biomedical application, to avoid frequent battery replacement in portable devices and to allow
operation of the device for a prolonged period of time. This work further focuses on improving
the linearity of the circuit to reduce the distortion at the output and achieve a high performance OTA
circuit. In this paper, a fully differential, bulk driven, source degenerated, differential pair, operating
in the weak inversion region is proposed. The bulk driven method is used to reduce the threshold
voltage which, in turn, reduces the supply voltage. Weak inversion is adopted to reduce the power
consumption of the circuit. The source degeneration method is used to reduce the transconductance
required for a low frequency circuit and to enhance the linear range, but a trade-off exists for linearity
Electronics 2018, 7, 41 3 of 19

Electronics 2018, 7, x FOR PEER REVIEW 3 of 18

and gain: as the linearity increases, the gain reduces. To overcome the reduction in gain due to source
enhance the output impedance and thereby, the gain in OTA, without any excess power dissipation.
degeneration, a self-cascode MOS are used. Self-cascode current mirror loads are used to enhance
Section 2 describes the materials and methods used, showing a block diagram, schematic and
the output impedance and thereby, the gain in OTA, without any excess power dissipation. Section 2
working of OTA in its subsections; Section 3 presents some derived equations; Section 4 shows the
describes the materials and methods used, showing a block diagram, schematic and working of
simulated results; and Section 5 concludes the paper with some comparisons with the results already
OTA in its subsections; Section 3 presents some derived equations; Section 4 shows the simulated
available in the literature.
results; and Section 5 concludes the paper with some comparisons with the results already available in
the literature.
2. Materials and Methods
2. Materials
Differentand Methods
methods were used in this research to achieve LV LP circuits with enhanced linear
ranges.
Different methods were used in this research to achieve LV LP circuits with enhanced linear ranges.

2.1. Linearization
2.1. Linearization Methods
Methods

2.1.1. Source Degeneration

Degeneration with
with Cross
Cross Coupled
Coupled Differential
Differential Pair
Pair
To improve
To improve the linearity of of the
the amplifier
amplifier and
andtotoachieve
achievedesirable
desirableperformance
performanceofofthe thecircuit, a
circuit,
acombination
combinationofofdifferent
differentlinearization
linearization techniques
techniques were
wereused.
used. Figure
Figure1 shows
1 showsthethe
circuit diagram
circuit diagram of
thethe
of conventional
conventional source
sourcedegeneration
degenerationtransistor
transistorwith
withcross
crosscoupled
coupled differential
differential pairs. Using this this
method, the transconductance
transconductance isisreduced
reducedby byaafactor
factorofof1 1+ +
NN and
andthethe
third harmonic
third harmonic is reduced
is reduced by
keeping
by different
keeping aspect
different ratios
aspect in the
ratios in input differential
the input pairspairs
differential to cancel out the
to cancel outodd
theharmonics.
odd harmonics.Even
harmonics
Even are automatically
harmonics suppressed
are automatically suppressedduedue
to the differential
to the differentialnature
natureofofthe
thecircuit.
circuit. The
The source
degeneration factor is N = = gm R. . Reduction in the transconductance
transconductance of the OTA is given by the the
following equation:
following equation:
gm
Gm = (1)
= 1 + gm R (1)
+

Figure 1. Cross coupled differential pair with source degeneration.

Figure 1. Cross coupled differential pair with source degeneration.

2.1.2. Bulk Driven Transistors

2.1.2. Bulk Driven Transistors
Figure 2 shows bulk driven differential pairs; in this technique, input signals are applied to the
Figure 2 shows bulk driven differential pairs; in this technique, input signals are applied to the
bulks of the input transistors. Bulk driven transistors are used for operation under low supply
bulks of the input transistors. Bulk driven transistors are used for operation under low supply voltages;
voltages; this reduces or removes the threshold voltage from the signal path. However, it reduces the
this reduces or removes the threshold voltage from the signal path. However, it reduces the gain
gain and gain bandwidth product, which is problematic for high frequency applications. However,
and gain bandwidth product, which is problematic for high frequency applications. However, for
for low frequency circuits, this problem is resolved because a low transconductance and gain
low frequency circuits, this problem is resolved because a low transconductance and gain bandwidth
bandwidth is required [10]. The linearity of an amplifier can be improved by using bulk driven
is required [10]. The linearity of an amplifier can be improved by using bulk driven differential
differential pairs, because this provides inherent signal attenuation and enhances linearity without
extra power dissipation. Trade-off exists with linearity and noise; input referred noise is increased
with an improvement in linearity. The transconductance of the bulk is 3–5 times less compared to
Electronics 2018, 7, 41 4 of 19

pairs, because this provides inherent signal attenuation and enhances linearity without extra power
dissipation. Trade-off exists with linearity and noise; input referred noise is increased with an
improvement in 7,linearity.
Electronics 2018, x FOR PEERThe transconductance of the bulk is 3–5 times less compared to4 ofthe
REVIEW 18 gate
transconductance [9]. Low transconductance is required for low frequency applications; therefore,
the gate transconductance
this reduction in7,transconductance [9]. Low transconductance is required for low frequency applications;
Electronics 2018, x FOR PEER REVIEW is favorable for biomedical circuits which are designed 4 offor
18 low
therefore, this reduction in transconductance is favorable for biomedical circuits
frequency ranges. The main advantage of this technique is the compatibility with the CMOS processes, which are designed
PMOS forislow
the gate frequency
preferred forranges.
transconductance The
bulk driven[9].main
Low advantage
input of this
transconductance
transistors technique is the
is required
because it does notcompatibility
for low with
havefrequency
to change the structure
CMOS
applications;
the of
processes,
therefore, PMOS
this is preferred
reduction in for bulk driven
transconductance input
is transistors
favorable for because
biomedical it does not
circuits have
which to
arechange the
designed
the MOS; it favors standard single well CMOS technology in which PMOS is fabricated with the bulk
structure of the MOS; it favors standard single of
well CMOS technology in which PMOS is the
fabricated
beingfor low frequency
isolated, avoiding ranges. The main
the need advantage
of complex this
and costly technique
twin tub is the
CMOScompatibility with
process [18]. CMOS
with the bulk
processes, PMOSbeing isolated, avoiding
is preferred the need
for bulk driven of complex
input andbecause
transistors costly twin tubnot
it does CMOS
have process [18].
to change the
structure of the MOS; it favors standard single well CMOS technology in which PMOS is fabricated
with the bulk being isolated, avoiding the need of complex and costly twin tub CMOS process [18].

Figure 2. Bulk driven differential pair.

Figure 2. Bulk driven differential pair.
2.2. Proposed OTA
Figure 2. Bulk driven differential pair.
2.2. Proposed OTA
Figure 3 shows the block diagram of a fully differential OTA. The bulk driven input pairs are
2.2.
usedProposed
Figure with OTA
two
3 shows cross
the coupled differential
block diagram of apairs
fullytodifferential
cancel out the OTA.non-linear
The bulk component.
driven input A source pairs are
used degeneration
withFigure
two crossresistor
3 shows is block
coupled
the used to increase
differential
diagram athe
ofpairs linearity.
cancelThe
todifferential
fully small
outOTA. signal
the The currents,
non-linear
bulk ia andpairs
component.
driven input ib, A flowsource
are
through
degeneration
used the
with transistors,
resistor
two is used
cross M1
to and
coupled M2, which
increase are to
cross
the linearity.
differential pairs coupled,
The
cancel small
out the andnon-linear
thecurrents,
signal final currents,
ia andi1iband
component. ,Aflow i2, through
source are
generated, which are copied bytoCM4, CM6the andlinearity.
CM1 to the output
degeneration
the transistors, M1resistor
and is used
M2, which increase
are cross coupled, and The
the finalwhich
small signal provides
currents,
currents, i1 andaia current
iand
2 , are
(iflow
2–i1)
ib,generated,
and CM3,the
through CM5 and CM2M1
transistors, which
and produces
M2, whichtheare
current
cross (i 1–i2) at the other output end. Figure 4 shows
coupled, and the final currents, i1 and i2, are
which are copied by CM4, CM6 and CM1 to the output which provides a current (i2 –i1 ) and CM3,
the detailedwhich
generated, schematic of the bulk
are copied driven,
by CM4, CM6 fully
anddifferential,
CM1 to theself-cascode
output which OTA.
provides a current (i2–i1)
CM5 and CM2 which produces the current (i1 –i2 ) at the other output end. Figure 4 shows the detailed
and CM3, CM5 and CM2 which produces the current (i1–i2) at the other output end. Figure 4 shows
schematic of the bulk driven, fully differential, self-cascode OTA.
the detailed schematic of the bulk driven, fully differential, self-cascode OTA.

Figure 3. Block diagram of the fully differential operational transconductance amplifier (OTA).

The input part of the OTA comprises two bulk driven differential pairs, cross coupled with the
Figure 3. Block diagram of the fully differential operational transconductance amplifier (OTA).
opposite
Figurepair to cancel
3. Block the non-linear
diagram of the fullyterm. The source
differential is degenerated
operational with the help
transconductance of a resistor
amplifier (OTA). to
improve the linearity, which is the simplest, best option for the circuit. Bulk driven MOS
The input part of the OTA comprises two bulk driven differential pairs, cross coupled with are selected
the
opposite pair to cancel the non-linear term. The source is degenerated with the help of a resistor to
improve the linearity, which is the simplest, best option for the circuit. Bulk driven MOS are selected
Electronics 2018, 7, 41 5 of 19

The input part of the OTA comprises two bulk driven differential pairs, cross coupled with the
opposite pair to cancel the non-linear term. The source is degenerated with the help of a resistor to
improve the linearity, which is the simplest, best option for the circuit. Bulk driven MOS are selected
Electronics 2018, 7, x FOR PEER REVIEW 5 of 18
to reduce the supply voltage, as the threshold voltage does not appear in the signal path. Two different
currents, ia andthe
to reduce ib , supply
flow, depending
voltage, as upon the sizesvoltage
the threshold through doesthenottwoappeardifferential
in the pairs,
signal which
path. Twothen get
added at the cross
different coupled
currents, ia andnode and
ib, flow, form currents
depending upon the i1 and
sizesi2through
, at nodes theVda and Vdb, respectively.
two differential pairs, which The
currents
thenfrom the cross
get added at coupled
the crossdifferential
coupled node pair,and
i1 , are
form then copiedi1 by
currents and thei2,diode connected
at nodes Vda and self-cascode
Vdb,
respectively. The currents from the cross coupled differential pair,
load, M7, M8, to the current mirrors, M17, M18 and M11, M12, through current mirrors, M15, M16 i 1 , are then copied by the diode
connected
and M13, M14.self-cascode load, M7,i ,M8,
Similarly, current to the current mirrors, M17, M18 and M11, M12, through
2 from the loads M5 and M6, is mirrored to M9, M10 and M19,
M20 through current mirrors, M23, M24M14.
current mirrors, M15, M16 and M13, and Similarly,
M21, M22. current i2, from node,
The output the loads M5 and M6,
i+, provides is
a current,
mirrored to M9, M10 and M19, M20 through current mirrors, M23, M24 and M21, M22. The output
i1 –i2 and the opposite output end, i-, provides the current, i2 –i1 . The current gains of all the current
node, i+, provides a current, i1–i2 and the opposite output end, i-, provides the current, i2–i1. The
mirrors are set to 1. The OTA circuit input comprises a total of eight branches, out of which two
current gains of all the current mirrors are set to 1. The OTA circuit input comprises a total of eight
branches are from
branches, out ofthe input
which two pairs, twoare
branches branches
from theare from
input thetwo
pairs, twobranches
current are mirrors andtwo
from the thecurrent
remaining
two are fromand
mirrors the the
output branch.
remaining twoThe
areinput
from part shouldbranch.
the output be properly
The input optimized so that
part should be an optimized
properly
gain,optimized
phase andsoGBW that an with a low total
optimized gain, harmonic
phase and GBW distortion
with a(THD)
low total should be achieved.
harmonic distortion The
(THD) output
part consists
should beofachieved.
common source
The outputdrivers, M5, of
part consists M6 and M7,
common sourceM8,drivers,
with their self-cascode
M5, M6 and M7, M8, loads,
with M21,
M22 andtheir M13,
self-cascode
M14. The loads, M21, M22
designed OTAand M13,a M14.
utilizes The designed
self-cascode structure OTA utilizes
instead of aa self-cascode
normal cascode
becausestructure instead structures
self-cascode of a normal cascode
provide highbecause
outputself-cascode
impedancesstructuresand save provide a Vth drop,highcompared
output to
impedances and save a Vth drop, compared to conventional cascodes [30]. All the transistors are
conventional cascodes [30]. All the transistors are operated in the subthreshold region to ensure a
operated in the subthreshold region to ensure a power efficient circuit suitable for low voltage, low
power efficient circuit suitable for low voltage, low frequency, portable biomedical applications.
frequency, portable biomedical applications.

Figure 4. Schematic of the bulk driven fully differential self-cascode OTA.

Figure 4. Schematic of the bulk driven fully differential self-cascode OTA.
Fully differential structures always require a common mode feedback circuit (CMFB) to
stabilize
Fully the common
differential mode output
structures alwaysvoltage,
requirebut this proposed
a common modeOTA is based
feedback on current
circuit (CMFB)mirrors
to stabilize
the common mode output voltage, but this proposed OTA is based on current mirrors whichand
which have an inherent common mode feedback. In general, the single ended output OTA have an
op-amp structures are the common mode signal, generated at the diode connected low-impedance
inherent common mode feedback. In general, the single ended output OTA and op-amp structures
nodes of the current mirroring MOS transistor; these are copied to the final output node in the first
are the common mode signal, generated at the diode connected low-impedance nodes of the current
stage and the output common mode signal becomes well defined and it does not need the CMFB
mirroring MOS transistor; these are copied to the final output node in the first stage and the output
network (N/W). However, in a fully differential structure, the common gates of the output section,
common mode signal becomes
n-MOS or p-MOS, well
are biased bydefined andDC
a constant it does not(V
voltage need the or
bias-n CMFB network
V bias-p, (N/W). However,
respectively). The
in a fully differential
output structure,
nodes’ voltage the common
(DC value) gatesin
is not defined ofthis
thecase,
output
andsection,
it needsn-MOS or p-MOS,
to be stabilized are biased
through a
negative feedback-based CMFG N/W. However, in the case of the proposed OTA circuit, there exists
Electronics 2018, 7, 41 6 of 19

by a constant DC voltage (V bias-n or V bias-p, respectively). The output nodes’ voltage (DC value)
is not defined in this case, and it needs to be stabilized through a negative feedback-based CMFG
N/W. However, in the case of the proposed OTA circuit, there exists two-subsections in the first stage.
This is called a balanced OTA structure, in which both internal nodes are symmetrical low-impedance
nodes, unlike the conventional single ended, output based nodes of the current mirror asymmetric
OTA, where one node is of a high impedance and the other node is a low-impedance node. In the
balanced, bulk driven, cross coupled-based, V/I converter (used in this design), both of the internal
outputs’ (intermediate) nodes are low-impedance mode nodes, where there exists one p-MOS in a
diode connected configuration, and the DC voltage generated there well defines both of the final
differential output nodes’ (conveyed to output nodes for well-matched input section CMOS transistors)
DC bias voltages correspondingly. So, a CMFB circuit is not mandatory for the balance or symmetrical
structure of this circuit.
The dimensions of the transistor are listed in Table 1.

Table 1. Transistor Dimensions.

Transistors W/L (um)

Ma, Mb 1/0.5
M1, M4 10/10
M2, M3 30/10
M5, M7, M9, M15, M18, M23 30/1
M6, M8, M10, M16, M17, M24 1.5/1
M12, M13, M20, M21 8/1
MM11, M14, M19, M22 160/1

3. Performance Equation
This section is sub-divided into two sections: The first section shows the details of self-cascode
composite transistors in the subthreshold region. The second section shows the derivation of the
transconductance of the proposed OTA circuit.

3.1. Subthreshold Equation

The weak inversion current is an exponential function of the input voltage. The drain to source
the current IDS of a transistor in the subthreshold region is given by

W ( VGSnp−·VVTH ) −VDS
ID = Is ( )e T ·(1 − e VT ) (2)
L
where,


VTH = VT0 − n p − 1 VBS (3)

The complete equation is

−VT0 (n p −1)VBS −VDS

W ( VGS
 
) ( )
ID = Is e np·VT ·e np·VT ·(1 − e VT ) (4)
L

where Is represents the characteristic current and np is the slope factor in the weak inversion. VGS , VBS
and VDS are the gate, bulk and the drain voltages, respectively. VT0 is the threshold voltage at VBS = 0
and VT = KTq is the thermal voltage in which K is the Boltzmann’s constant and q is the electric charge.
Is is the characteristic current given by Is = 2nµCox VT 2 . The transistor will be saturated in this region
when VDS ≥ 3 KT q . The gate transconductance in the subthreshold region is given by

ID qID
gm = = (5)
nVT nKT
Electronics 2018, 7, 41 7 of 19

This gm is a function of ID and nKT q , whereas the bulk transconductance is a function of body
effect coefficient, γ, and the Fermi potential, ϕ F , which is given by
γ
gmb = (n − 1) gm = p gm (6)
2 2ϕ F − VBS

The bulk transconductance, gmb , is 2–3 times less than the gate transconductance, g7mof,18and it does
Electronics 2018, 7, x FOR PEER REVIEW
not depend on the aspect ratios of MOSFETs, as it does in strong inversion.
The bulk transconductance, , is 2–3 times less than the gate transconductance, , and it
does MOS
3.2. Composite not depend on the aspect ratios of MOSFETs, as it does in strong inversion.

The composite
3.2. Composite transistors,
MOS NMOS and PMOS, are shown in Figure 5 these are important
configurationsThe
in composite
weak inversion [13].
transistors, These
NMOS andself-cascode
PMOS, are showncomposite
in Figuretransistors
5 these areare able to provide
important
configurations
high output impedance in and
weakainversion
lower V[13].
th These
drop self-cascode
than a composite
normal transistors
cascode; are
therefore, able to
they provide
is preferred for
high output impedance and a lower Vth drop than a normal cascode; therefore, they is preferred for
low voltage applications.
low voltage applications.

Figure 5. (a) NMOS composite transistor (b) PMOS composite transistor.

Figure 5. (a) NMOS composite transistor (b) PMOS composite transistor.
3.2.1. Sizing of Composite Transistors
3.2.1. Sizing ofConsidering
Composite Transistors
Figure 5a, the currents and voltages of the composite transistor can be derived and
written as
Considering Figure 5a, the currents and voltages of the composite transistor can be derived and
= (7)
written as
IDSa= = IDSb
− (8) (7)

= VDa−− VSa
VDSa = (9) (8)
where, and are the drains to source the current flowing through transistors Qa and Qb,
VDSa = VGSa − VGSb (9)
is the drain to source the voltage of transistor Qa, and and are the gates to source
where, IDSavoltages
and Iof transistors Qa and Qb, respectively. The transistor on the rail side is called the rail device
DSb are the drains to source the current flowing through transistors Qa and Qb, VDsa
and the transistor on the other side is called the cascode device [7]. Considering that both of the
is the drain to source the voltage of transistor Qa, and VGSa and VGSb are the gates to source voltages
transistors are in the saturation region of weak inversion and are implemented in the same well,
of transistors Qacausing
thereby and Qb, respectively.
a body The Equations
effect, by solving transistor
(2) on
andthe railexpression
(9), the side is called
of the
canrail device and the
be written
transistor on the other side is called the cascode device [7]. Considering that both of the transistors are
as [17,30]
in the saturation region of weak inversion
(
and
)
are implemented
( ) in the same well, thereby causing a
1− ( )
= (10)
body effect, by solving Equations (2) and (9), the expression(of V)Dsa can be written as [17,30]

(
VGSa −VGSb
)( ( ) (W )
e VT
[1 −/e(−
) VDSa VT )
= ] =  L b (11) (10)
( ) W
L a
( )
= 1 + (W ) (12)
e(VDSa /VT ) =  L b (11)
W
The drain source voltage of transistor Qa is a logarithmic
L a function of the transistor sizes, rather
than the gate to source voltage, as in a conventional transistor. For both the transistors to be in the
(W )
VDSa = VT ln[1 +  L b ] (12)
W
L a
Electronics 2018, 7, 41 8 of 19

The drain source voltage of transistor Qa is a logarithmic function of the transistor sizes, rather
than the gate to source voltage, as in a conventional transistor. For both the transistors to be in the
saturation region of weak inversion, VDSa and VDSb must be ≥ 3 KT q . To maintain this condition, the
sizes of the transistor should be set according to Equation (13).

(W )
Electronics 2018, 7, x FOR PEER REVIEW  L b ≥ e3 − 1 8 of 18
(13)
W
saturation region of weak inversion, L a must be ≥ 3
and . To maintain this condition, the
sizes of the transistor should be set according
W to Equation (13).
( )
(L b ) ≥ 20 − 1 (14)
W ≥ −1 (13)
(L a)
The above condition shows that the size( of transistor
) Qb should be at least greater than 19 times
≥ 20 − 1 (14)
the size of transistor Qa. Therefore a large area
( is )required to maintain the transistors in saturation [30].
The same condition applies to the PMOS composite transistor as well.
The above condition shows that the size of transistor Qb should be at least greater than 19 times
the size of transistor Qa. Therefore a large area is required to maintain the transistors in saturation
3.2.2. Small Signal
[30]. Model
The same of Composite
condition Transistors
applies to the PMOS composite transistor as well.
Figure 6 shows the small signal model of the composite transistor from Figure 3a when both
3.2.2. Small Signal Model of Composite Transistors
transistors are saturated. The output resistance is multiplied by the gain of the common gate amplifier;
Figure 6 shows the small signal model of the composite transistor from Figure 3a when both
thus, it becomes larger
transistors for sameThe
are saturated. value of Vresistance
output GS . The currents andbyvoltages
is multiplied the gain ofof the
the composite
common gatetransistors
are same as for a single
amplifier; thus, ittransistor,
becomes largerandfora same
smallvalue
value GS.V
of Vof The
DS is enough
currents and to saturate
voltages of theboth the transistors,
composite
transistors are same as for a single transistor, and a small value of V
as long as the transistor ratios satisfy Equation (13). The composite transistor has biasingthe
DS is enough to saturate both similar to a
transistors, as long as the transistor ratios satisfy Equation (13). The composite transistor has biasing
single MOS; therefore, it does not increase the power of the circuit and the purpose of the composite
similar to a single MOS; therefore, it does not increase the power of the circuit and the purpose of the
transistor is to increase
composite the output
transistor impedance
is to increase and impedance
the output thus the gain. The the
and thus small signal
gain. equivalent
The small signal equation
is given byequivalent
[15,30]: equation is given by [15,30]:
gm ≈ gm a (15) (15)

And And
go a gob
go ≈ (16)
(16)
ngmb

Figure 6. Small signal model of the composite transistor.

Figure 6. Small signal model of the composite transistor.
3.2.3. Noise of Composite MOS
3.2.3. Noise ofThe
Composite MOS MOS comprises of flicker noise and thermal noise, which can be given
noise of a composite
by the following expression [11]:
The noise of a composite MOS comprises of flicker noise and thermal noise, which can be given
= +( ) (17)
by the following expression [11]:
Total noise can be calculated as a single MOS transistor.
2
go a
Vn2 = Vna 2 + ( ) Vnb 2 ≈ Vn a 2 (17)
3.3. Transconductance of OTA gm a
In regard to the simplified block diagram of the OTA shown in Figure 7, the input transistor
Total noise can be calculated as a single MOS transistor.
pair gate is grounded, and the input signal is applied to the bulks. The grounded gates provide an
inversion layer, and a current (Ib) flows through the input pairs, even if no input signal is applied
Electronics 2018, 7, 41 9 of 19

3.3. Transconductance of OTA

In regard to the simplified block diagram of the OTA shown in Figure 7, the input transistor
pair gate is grounded, and the input signal is applied to the bulks. The grounded gates provide an
inversion layer, and a current (Ib ) flows through the input pairs, even if no input signal is applied and
no current
Electronics flows
2018, through
7, x FOR the degeneration resistor. If a small signal differential voltage is applied
PEER REVIEW 9 of at
18
the bulk of the differential pairs and V1 is greater than V2, then a current (iR ) will flow through the
and
source nodegeneration
current flows through
resistor (Rs).the degeneration
This resistor.
current can be If a as
expressed small signal differential voltage is
applied at the bulk of the differential pairs and V1 is greater than V2, then a current (iR) will flow
through the source degeneration resistor (Rs). This − Vsb can be expressed as
Vsacurrent
iR = (18)
2Rs
−
= (18)
Considering the simplified half circuit and its2small signal model of Figure 8, N represents the
transconductance
Considering the ratio between M2
simplified halfand M4.and
circuit Theits
transconductance of the
small signal model of OTA is 8,
Figure given by [31,32]:the
N represents
transconductance ratio between M2 and M4. The transconductance of the OTA is given by [31,32]:
iout gm − Ngmb
Gm = = −b (19)
= vid
= vgs1 + vs1
(19)
+
(1 (−1 −) N ) gmb
Gm== (20)
(20)
1 +1 + N
(1
(1−− N
) ) (1b +(1 +
gm ) N)
Gm =
= . · (21)
(1
(1++ N
) )1 +1 + gm 1 1 (21)
(1b+(1 +). (N )·( g)
0_RS
)
_
(1 − N ) + b ()1 + N )
(1gm
G=m (1
=− ) . · (22)
(22)
) 1N+) 1 +(1gm
(1 +(1 + + b ().1 + N )· Rs


where, gmb (gm(b1 = gmb2== gmb4 == gmb ) = n p −) 1 =gm = −
where, gm1b is the
= effective
isbulk
thetransconductance
effective bulk
pairs, 1 of
1
of the differential pairs,
transconductance of theg0_RS is the conductance
differential the
is source
the degeneration
conductance of resistance.
the source N shows that
degeneration
_
the size of the transistor M2 is N times M4. The transconductance of the differential
resistance. N shows that the size of the transistor M2 is N times M4. The transconductance pair is decreased
of the
by a factor of (1 + N) and depends on Rs.
differential pair is decreased by a factor of (1 + N) and depends on Rs.

Figure 7. Half circuit of the proposed OTA.

Figure 7. Half circuit of the proposed OTA.
Electronics 2018, 7, 41 10 of 19
Electronics 2018, 7, x FOR PEER REVIEW 10 of 18

Figure 8. Small signal model of the half circuit.

Figure 8. Small signal model of the half circuit.
Further simplifying Equation (22),
Further simplifying Equation (22), ( ) ( )
= . or = . _ (23)
( ) ( )
(1 − N ) 1 (1 − N )
Gm = · (1 −or G
)m = · g0_RS (23)
(1 + N )= Rs . _ .(1 + N ) (24)
(1 + )
Equations (23) and (24) show that (1is− N ) to the conductance,
linear _ . Thus, by increasing
i0 = ·g ·v (24)
(1 + N
Rs, linearity is increased at the cost of decreased ) 0_RS id
transconductance.
Equations (23) and (24) show that Gm is linear to the conductance, g0_RS . Thus, by increasing Rs,
4. Simulation Results
linearity is increased at the cost of decreased transconductance.
The proposed OTA was simulated in CADENCE virtuoso environment using LFoundry 150 nm
CMOS process
4. Simulation parameters. Different simulation graphs were extracted from CADENCE and plotted
Results
on MATLAB software using CSV files. The objectives of the different simulations were to obtain
The proposed
various OTA was
performances simulated
of the OTA withinrespect
CADENCE virtuosotransient
to ac response, environment using
response, LFoundry
corner 150 nm
simulation
CMOS process parameters.
and the DC sweep. Different simulation graphs were extracted from CADENCE and plotted
on MATLAB software using CSV files. The objectives of the different simulations were to obtain
4.1. performances
various AC Response of the OTA with respect to ac response, transient response, corner simulation
and the DC Thesweep.
AC analysis of the proposed OTA was done with a capacitive load of 1 pF and the DC gain
obtained was 48.4 dB with a unity gain bandwidth (GBW) of 3.1 KHz; the phase margin (PM) and
4.1. AC Response
gain margin (GM) were found to be 80° and 19.01 dB, respectively. The gain was improved from 32
dB toAC
The 48 dB by using
analysis of the
thecomposite
proposedMOS. OTAThewasGBWdonecan be improved
with further
a capacitive loadbyofkeeping
1 pF andthe the
current
DC gain
mirrors (CM) ratio high, but here in the proposed OTA, the CM ratio was kept at 1:1, as for low
obtained was 48.4 dB with a unity gain bandwidth (GBW) of 3.1 KHz; the phase margin (PM) and gain
frequency circuits, the GBW is usually low. The gain and phase responses of the proposed OTA are
margin (GM) were found to be 80◦ and 19.01 dB, respectively. The gain was improved from 32 dB to
shown in Figure 9 along with various corner simulations at the four corners (i.e., slow NMOS, slow
48 dBPMOS
by using
(SS);the composite
slow NMOS, fast MOS. The(SF);
PMOS GBW can
fast be improved
NMOS and slowfurther
PMOS by keeping
(FS); the fast
and lastly current
NMOS mirrors
(CM)andratio
fasthigh,
PMOS but hereFigure
(FF)). in the10proposed
shows theOTA,
effect the CM ratio was
of temperature kept on
variation at 1:1, asgain
the ac for low frequency
and phase
circuits, the GBW
response. is usually
The designed low.must
circuit The begain and phase
capable responses
of working of thetolerance,
under device proposedtemperature
OTA are shown and in
Figureprocess
9 alongvariations, and device
with various mismatch
corner effects.at
simulations The
theprocess corners were
four corners simulated
(i.e., slow NMOS,to check
slowthe PMOS
robustness of the circuit.
(SS); slow NMOS, fast PMOS (SF); fast NMOS and slow PMOS (FS); and lastly fast NMOS and fast
PMOS (FF)).Table 2 shows
Figure 10the simulation
shows results
the effect of the ac analysis
of temperature under process
variation on the corners.
ac gain The
andperformance
phase response.
deviations at the four corners regarding the gain, GBW, PM and GM lie in the range of 34–56 dB, 1.3
The designed circuit must be capable of working under device tolerance, temperature and process
K–4.3 K, 76.5°–83.5° and 19–20.5 dB, respectively, whereas the gain, GBW, PM and GM for a TT
variations, and device mismatch effects. The process corners were simulated to check the robustness of
(typical typical) case are 48.4 db, 3.1 KHz, 80° and 19.01 dB, respectively.
the circuit.
Table 2 shows the simulation results of the ac analysis under process corners. The performance
deviations at the four corners regarding the gain, GBW, PM and GM lie in the range of 34–56 dB,
1.3 K–4.3 K, 76.5◦ –83.5◦ and 19–20.5 dB, respectively, whereas the gain, GBW, PM and GM for a TT
(typical typical) case are 48.4 db, 3.1 KHz, 80◦ and 19.01 dB, respectively.
Electronics 2018, 7, 41 11 of 19

Electronics 2018, 7, x FOR PEER REVIEW 11 of 18

Electronics 2018, 7, x FOR PEER REVIEW 11 of 18

Figure 9. Process corner effects on the ac gain and phase response.

Figure 9. Process corner effects on the ac gain and phase response.
Figure 9. Process corner effects on the ac gain and phase response.

Figure 10. Temperature variation effects on the ac gain and phase response.

Figure 10. Temperature variation effects on the ac gain and phase response.
Table
Figure 10. Temperature 2. Effect of
variation corners
effects ononthe
ac response.
ac gain and phase response.
Corner Name Table
Corner
Table
2. 2.Gain (dB)
Effectof
Effect GBWon
ofcorners
corners on(Hz)
ac PM (degree) GM (dB)
acresponse.
response.
Nominal TT 48.40 3.1 K 80° 19.01
Corner Name Corner Gain (dB) GBW (Hz) PM (degree) GM (dB)
C0 SS 55.78 1.3 K 76.5° 20.4
Corner Name Corner
Nominal
C1
TT Gain (dB)
SF
48.40
56.32
GBW
3.1 K (Hz) 80° PM (degree)
1.4 K 78.6°
19.01
20.5
GM (dB)
C0 SS 55.78 1.3 K 76.5° 20.4
◦
Nominal C2
TT FS 48.4034.24 4.2 k3.1 K 83.5° 8019.2 19.01
C1 SF 56.32 1.4 K 78.6° 20.5
◦
C0 C3
SS FF 55.7836.67 4.3 K1.3 K 83.3° 19.3
76.5 20.4
C2 FS 34.24 4.2 k 83.5° 19.2
◦
C1 SF
C3 FF
56.3236.67 4.3 K
1.4 K 83.3°
78.619.3 20.5
C2 To verify that the
FS designed circuit works properly 4.2
34.24 in different
k environmental
83.5 ◦
conditions,19.2
the
C3 of temperature
effect FFvariations, from36.67
−50° to 100 °C, on 4.3
theKabove-mentioned ◦
83.3parameters 19.3
of the ac
To verify that the designed circuit works properly in different environmental conditions, the
response, are shown in Table 3.
effect of temperature variations, from −50° to 100 °C, on the above-mentioned parameters of the ac
Toresponse, are the
verify that shown in Tablecircuit
designed 3. works properly in different environmental conditions, the effect
Table 3. Effect of temperature variation on the ac response.
of temperature variations, from −50◦ to 100 ◦ C, on the above-mentioned parameters of the ac response,
Temperature
Table 3.(°C)
EffectGain (dB) GBW
of temperature (Hz) on
variation PMthe
(degree) GM (dB)
ac response.
are shown in Table 3. −50 55.4 234.7 78.5° 25.2
Temperature (°C) Gain (dB) GBW (Hz) PM (degree) GM (dB)
−25 54.84 866.5 77.8° 22.1
0
3. Effect of temperature
Table−50 55.4
52.48
variation on 77.5°
234.7
1.9 K
the ac response.
78.5° 25.2
20.1
−25 54.84 866.5 77.8° 22.1
25 48.72 2.9 K 79.9° 18.9
◦
Temperature ( C) 0 52.48 1.9 K 77.5° 20.1
50 Gain (dB) 44.38 GBW 3.8(Hz)
K PM (degree)
81.1° 18.7 GM (dB)
25 48.72 2.9 K 79.9° 18.9
75 40 4.4 K 82.1° ◦ 18.9
−50 50 55.4 44.38 234.7
3.8 K 81.1° 78.5 18.7 25.2
100 35.4 4.7 K 83.4° ◦ 18.8
−25 75 54.84 40 866.5
4.4 K 82.1° 77.8 18.9 22.1
0 100 52.48 35.4 1.9
4.7KK 83.4° 77.5◦ 18.8 20.1
25 48.72 2.9 K 79.9◦ 18.9
50 44.38 3.8 K 81.1◦ 18.7
75 40 4.4 K 82.1◦ 18.9
100 35.4 4.7 K 83.4◦ 18.8
Electronics 2018, 7, 41 12 of 19

4.2. Common Mode Rejection Ratio (CMRR)

Electronics 2018, 7, x FOR PEER REVIEW 12 of 18
The common mode rejection ratio (CMRR) is the ability of a differential amplifier to
Electronics 2018, 7, x FOR PEER REVIEW
reject the
12 of 18
common mode
4.2. Common signal
Mode(i.e., signals
Rejection Ratiocommon
(CMRR) to both inputs). CMRR can be calculated as
4.2. Common Mode Rejection
The common Ratio (CMRR)
mode rejection ratio (CMRR) is the ability of a differential amplifier to reject the
AD
common mode signal (i.e., signals
The common mode rejection ratio common
CMRR to=
both
(CMRR) inputs).
20log
is the CMRR
ability
10 of a can be calculated
differential as to reject the
amplifier (25)
ACM
common mode signal (i.e., signals common to both inputs). CMRR can be calculated as
= 20 (25)
where, A D is the differential gain and ACM is the input common mode gain.
= 20 (25)
Figure 11 shows
where, is thethat the CMRR
differential gain is 146.3 dB,
and which
is the inputiscommon
high atmode
low frequencies
gain. and starts to decrease
Figure 11decreases
as differential shows thatandthe common
CMRR is 146.3 dB, which is high atVarious
low frequencies and starts to
where, gain is the differential gain and mode gain
is the input increases.
common mode gain. common mode noises can
decrease as differential gain decreases and common mode gain increases. Various common mode
be rejectedFigure
by having
11 showsgoodthat
noise
the immunity,
CMRR is 146.3anddB,thiswhich
can be is achieved
high at low byfrequencies
having a higher CMRR:
and starts to the
noises can be rejected by having good noise immunity, and this can be achieved by having a higher
higherdecrease
the as differential
CMRR, the lower gain
the decreases
effect of andcommon
the common modemode gain increases. Various common mode
signal.
CMRR: the higher the CMRR, the lower the effect of the common mode signal.
noises can be rejected by having good noise immunity, and this can be achieved by having a higher
CMRR: the higher the CMRR, the lower the effect of the common mode signal.

Figure 11. The common mode rejection ratio (CMRR).

Figure 11. The common mode rejection ratio (CMRR).
4.3. Power Supply RejectionFigure
Ratio 11.
(PSRR)
The common mode rejection ratio (CMRR).
4.3. Power Supply Rejection
The power supplyRatio (PSRR)
rejection ratio (PSRR) is the ability of a device to maintain its output voltage
4.3. Power Supply Rejection Ratio (PSRR)
Theaspower
the DC supply
power supply voltage
rejection (VDC)
ratio varies.
(PSRR) It can
is the be expressed
ability as to maintain its output voltage as
of a device
The power supply rejection ratio (PSRR)
the DC power supply voltage (VDC) varies. It can is the ability of a device to maintain its output voltage
= 20be expressed as (26)
+
as the DC power supply voltage (VDC) varies. It can be expressed as
AD
where, PSRR
is the differential mode gain and =
A+20log
is the10ratio of differential voltage to the change in (26)
= 20 A+ (26)
power supply. A+ can be expressed as +
A D is theisdifferential
where,where, mode
the differential mode gain andA+
gainand A+ is the ratio
is the ratioofofdifferential
differential voltage
voltage tochange
to the the change
in in
powerpower
supply. A+ can be expressed asas += (27)
supply. A+ can be expressed
A
Figure 12 shows that a PSRR of 83 dBA = Dat low frequencies. Higher PSRR values are
is+obtained (27)
+= VDD (27)
required to reduce the effect of ripples generated due to the variation in power supply.
Figure 12 shows that a PSRR of 83 dB is obtained at low frequencies. Higher PSRR values are
Figure 12 shows that a PSRR of 83 dB is obtained at low frequencies. Higher PSRR values are
required to reduce
required the effect
to reduce of ripples
the effect generated
of ripples generateddue to the
due to thevariation
variationin in power
power supply.
supply.

Figure 12. The power supply rejection ratio (PSRR).

Figure 12. The power supply rejection ratio (PSRR).

Figure 12. The power supply rejection ratio (PSRR).
Electronics 2018, 7, 41 13 of 19

Electronics 2018, 7, x FOR PEER REVIEW 13 of 18

4.4. Slew Rate (SR)
Electronics 2018, 7, x FOR PEER REVIEW 13 of 18
4.4. Slew Rate (SR)
The slew rate is the rate of change of output voltage with respect to the input voltage.
Electronics 2018, 7, x FOR PEER REVIEW 13 of 18
The
proposed The Rate
slew
circuit
4.4. Slew rate
is(SR) is the rate
operated of change
in thte of outputregion
subthreshold voltagewhich
with respect
requires to athe input
very lowvoltage.
current, Thewhich
proposed
4.4. Slew circuit
Rate is operated in thte subthreshold ofregion which requires a very lowvaluecurrent, which
decreases the slew(SR)
Theslew rate
rateand slows
is the rate down the speed
of change of output OTA. However,
voltage the capacitor
with respect is kept
to the input voltage. The smaller
decreases
than 1proposed
pF which the slew rate and slows down the speed of OTA. However, the capacitor value is kept
The slew rate is the rate of change of output voltage with respect to the input voltage. The OTA
maintains
circuit is the
operated slew
in rate
thte at a desirable
subthreshold value.
region Figure
which 13
requiresshows
a very the
low response
current, of
whichthe
smaller than 1 pF which maintains the slew rate at a desirable value. Figure 13 shows the response of
when proposed
an input circuit
decreases is applied
the slew ratewith
and a
is operated in1thte
Vpp
slows square
down wave.
the speed
subthreshold of The
regionOTA.positive
whichHowever,SRthe
requires a(SR+) is 99.56
capacitor
very low V/ms
value
current, iswhich
keptand the
the OTA when an input is applied with a 1 Vpp square wave. The positive SR (SR+) is 99.56 V/ms
smaller
negative than 1 pF
−) slew which maintains the slew rate at a desirable value. Figure 13 shows the response of
andSR the(SR is 100 V/ms.
decreases the rate and slows down the speed of OTA. However, the capacitor value is kept
negative SR (SR−) is 100 V/ms.
the OTAthan
smaller when anwhich
1 pF inputmaintains
is appliedthe
with a 1rate
slew Vpp atsquare wave.
a desirable The Figure
value. positive
13SR (SR+)the
shows is response
99.56 V/ms
of
and the negative SR (SR−) is 100 V/ms.
the OTA when an input is applied with a 1 Vpp square wave. The positive SR (SR+) is 99.56 V/ms
and the negative SR (SR−) is 100 V/ms.

Figure 13. Slew Rate.

Figure 13. Slew Rate.
Figure 13. Slew Rate.
4.5. Transient Response
4.5. Transient Response Figure 13. Slew Rate.
The transient
4.5. Transient response of the OTA with the differential input signal and the differential output
Response
The transient
signal is shownresponse
in Figureof14.
theThe
OTA with the
transient differential
response of the input
OTA wassignal and theindifferential
simulated a unity gainoutput
4.5. Transient
The Response
transient response of the OTA with the differential input signal and the differential
signalconfiguration
is shown inusing Figurethe 14.
setupThe transient
shown response
in Figure of the OTA
15. The transient was was
response simulated
performed aoutput
in with
unity
an gain
signal is transient
The shown inresponse
Figure 14.of TheOTA
the transient
with response
the of theinput
differential OTAsignal
was and
simulated
the in a unity
differential gain
output
configuration using
input signal the mVpp
of 200 setup at
shown in Figure
a frequency 15.Hz.
of 100 The transient response was performed with an input
configuration
signal is shownusing the setup
in Figure 14. shown in Figure
The transient 15. Theoftransient
response the OTA response was performed
was simulated withgain
in a unity an
signal of 200 mVpp at a frequency of 100 Hz.
input signal ofusing
configuration 200 mVpp at a frequency
the setup shown in of 100 Hz.
Figure 15. The transient response was performed with an
input signal of 200 mVpp at a frequency of 100 Hz.

Figure 14. Transient response of the differential input and output.

Figure 14. Transient response of the differential input and output.

Figure 14. Transient response of the differential input and output.
Figure 14. Transient response of the differential input and output.

Figure 15. Setup for the fully differential to unity gain conversion.

Figure 15. Setup for the fully differential to unity gain conversion.
Figure 15. Setup for the fully differential to unity gain conversion.
Figure 15. Setup for the fully differential to unity gain conversion.
Electronics 2018, 7, 41 14 of 19
Electronics 2018, 7, x FOR PEER REVIEW 14 of 18
Electronics 2018, 7, x FOR PEER REVIEW 14 of 18
4.6. Transconductance
4.6. Transconductance
4.6. Transconductance
The transconductance of the OTA for low frequency applications should be very low—usually in
The transconductance of the OTA for low frequency applications should be very low—usually
the order
The of few nA/V—to obtain
transconductance of the the low
OTA forcut-off
low frequency which is required in
bebiomedical devices.
in the order of few nA/V—to obtain the low frequency applications
cut-off frequency which should veryin
is required low—usually
biomedical
A
in trade off exists
the order of fewfor lower values of Gm;
thethere is increased input referred isnoise levelsin
which can be
devices. A trade off nA/V—to obtain
exists for lower valueslow of cut-off frequency
Gm; there whichinput
is increased required
referred biomedical
noise levels
minimized
devices.can by
A trade properly sizing
off existsby the input
forproperly differential
lower values pairs. The sizes of the input transistors are kept
which be minimized sizingofthe Gm; theredifferential
input is increased input
pairs. Thereferred
sizes ofnoise
the levels
input
larger
which because
can are larger
be minimized sizes, particularly in terms of length, reduce the flicker noise, which, in turn,
transistors kept larger by properly
because sizing
larger sizes,the input differential
particularly in termspairs. The sizes
of length, reduceof the
the flicker
input
reduces the
transistors input
areinkeptreferred noise [27,33]. The transconductance obtained is 23 nA/V with a linear range
noise, which, turn,larger
reducesbecause larger
the input sizes, particularly
referred noise [27,33].inTheterms of length, reduce
transconductance the flicker
obtained is 23
of +/−which,
noise, 100 mV, in which
turn, is shownthe
reduces in input
Figurereferred
16. noise [27,33]. The16.
transconductance obtained is 23
nA/V with a linear range of +/− 100 mV, which is shown in Figure
nA/V with a linear range of +/− 100 mV, which is shown in Figure 16.

Figure
Figure 16.
16. Transconductance plot of
Transconductance plot of OTA.
OTA.
Figure 16. Transconductance plot of OTA.
4.7. Total Harmonic Distortion (THD)
4.7. Total Harmonic Distortion (THD)
4.7. Total Harmonic Distortion (THD)
The total harmonic distortion (THD) is a measurement of the harmonic distortion present in a
The total harmonic distortion (THD) is a measurement of the harmonic distortion present in a
signalThe
andtotal harmonic
is defined distortion
as the ratio of (THD)
the sum is of
a measurement
the powers of of
allthe harmonic
harmonic distortiontopresent
components in a
the power
signal and is defined as the ratio of the sum of the powers of all harmonic components to the power of
signal
of the and is defined frequency.
fundamental as the ratio The
of thetotal
sumharmonic
of the powers of all harmonic
distortion (THD) is components
obtained bytoapplying
the powera
the fundamental frequency. The total harmonic distortion (THD) is obtained by applying a sinusoidal
of the fundamental
sinusoidal frequency.
input of 200 mVpp atThe total harmonic
a frequency distortion
of 100 Hz. (THD) THD
The achieved is obtained bydB,
is −58.56 applying a
which is
input of 200 mVpp at a frequency of 100 Hz. The achieved THD is −58.56 dB, which is shown in
sinusoidal input 17.
shown in Figure of 200 mVpp
Second at a frequency
harmonics of 100 Hz.
are suppressed dueThe achieved
to the THDnature
differential is −58.56 dB,circuit.
of the which is
Figure 17. Second harmonics are suppressed due to the differential nature of the circuit.
shown in Figure 17. Second harmonics are suppressed due to the differential nature of the circuit.

Figure 17. Total harmonic distortion (THD) plot, applying a sinusoidal input of 200 mVpp at a
Figure 17. ofTotal
frequency
Figure 17. harmonic
harmonic distortion
100 Hz.
Total distortion (THD)
(THD) plot,
plot, applying
applying aa sinusoidal
sinusoidal input
input of
of 200
200 mVpp
mVpp at
at aa
frequency of 100 Hz.
frequency of 100 Hz.
Figure 18 shows the differential output current versus frequency plot, showing the linear range
of theFigure 18 shows
OTA with theto
respect differential
the outputoutput current versus frequency plot, showing the linear range
current.
Figure 18 shows the differential output current versus frequency plot, showing the linear range of
of the OTA with respect to the output current.
the OTA with respect to the output current.
Electronics 2018, 7, 41 15 of 19
Electronics 2018, 7, x FOR PEER REVIEW 15 of 18

Figure 18. Differential output current of OTA.

Figure 18. Differential output current of OTA.

4.8. Power Consumption

4.8. Power Consumption
The DC analysis of OTA was carried out in an open loop configuration to check the condition
The DC analysis of OTA was carried out in an open loop configuration to check the condition
involving saturation in the weak inversion region (≥3KT 3 ). The currents in each branch are 11 nA
involving saturation in the weak inversion region ≥ q . The currents in each branch are 11 nA and
and the total current consumed by the overall circuit is 74 nW with a supply voltage of 0.8 V.
the total current consumed by the overall circuit is 74 nW with a supply voltage of 0.8 V. Therefore, the
Therefore, the overall power consumption of the OTA is 59.04 nW.
overall power consumption of the OTA is 59.04 nW.
5.
5. Discussion
Discussion
Different simulationresults
Different simulation results were
were shown
shown in above
in the the above
sectionsection
to prove to that
prove that a considerable
a considerable linearity
linearity can be achieved by using the source degeneration technique,
can be achieved by using the source degeneration technique, bulk driven and cross coupled bulk driven and cross coupled
differential
differential pairs to improve the THD. Bulk driven transconductance is
pairs to improve the THD. Bulk driven transconductance is lower than that of the gate driven technique, lower than that of the gate
driven
but this technique, but this low
low transconductance transconductance
is favorable is favorable
for our circuit, because forthisour circuit,
circuit focusesbecause
on lowthis circuit
frequency
focuses on low frequency biomedical applications. The transconductance
biomedical applications. The transconductance obtained was 23 nA/V. The currents in each branch obtained was 23 nA/V. The
currents in each branch were 11 nA and the total current consumed by
were 11 nA and the total current consumed by the overall circuit was 74 nW. A low power of up to the overall circuit was 74 nW.
A lownW
59.04 power can ofbe up to 59.04for
obtained nW can be devices,
portable obtainedand for this
portable
power devices,
can beand this reduced
further power can be further
if the supply
voltage is reduced to 0.6 V (circuit works well), but the dynamic range can also be reduced,can
reduced if the supply voltage is reduced to 0.6 V (circuit works well), but the dynamic range also
which
be
canreduced,
reduce the which cantoreduce
signal noise theratiosignal
(SNR) toof
noise ratio (SNR)
the circuit, so the ofsupply
the circuit, so the
voltage was supply
kept at voltage
0.8 V. was
The
kept at 0.8 V. The highest CMRR was achieved which shows that the
highest CMRR was achieved which shows that the input common mode signal has a low effect, and input common mode signal has
it
a low effect, and it proves that the proposed OTA has good noise
proves that the proposed OTA has good noise immunity and is able to reject various common mode immunity and is able to reject
various
noises. PSRRcommon was mode noises. PSRR
also obtained to findwas
the also
effectobtained
of ripples togenerated
find the effect
due to ofvariation
ripples generated due to
in power supply.
variation in power supply. The slew rate obtained was 99.56/100 V/ms,
The slew rate obtained was 99.56/100 V/ms, which is comparatively low because the circuit operated which is comparatively low
because the circuit operated in the subthreshold region and in this region,
in the subthreshold region and in this region, currents are very low, which limits the speed of OTA. currents are very low,
which
Different limits the simulations
corner speed of OTA. have Different corner simulations
been executed to check the haveeffectbeen executedon
of variations to gain,
checkGBW, the effect
GM,
of variations on gain, GBW, GM, PM; not only this, but temperature
PM; not only this, but temperature variations were also observed. The PM remained stable around 80◦variations were also observed.
The PM
which remained
shows that thestable around
circuit is quite80°stable,
which even
shows at that the circuit
different corners.is The
quiteperformance
stable, evendeviation
at different at
corners. The performance deviation at the four corners with respect
the four corners with respect to gain, GBW, PM and GM values lay in the ranges of 34.24–56.32 to gain, GBW, PM and GM dB,
values K,
1.3–4.3 lay76.5–83.5
in the ranges of 34.24–56.32
◦ and 19.01–20.5 dB, 1.3–4.3whereas
dB, respectively, K, 76.5–83.5 ° and 19.01–20.5 dB, respectively,
the gain, GBW, PM and GM values for a
whereas
TT (typicalthetypical)
gain, GBW, PM48.4
case are anddb, GM3.1 values
KHz,for 80◦aandTT (typical
19.01 dB, typical) case are
respectively. A48.4 db, 3.1 KHz,
comparison 80°
of these
and 19.01 dB, respectively. A comparison of these
results with the results available in the literature is shown Table 4. results with the results available in the literature is
shown Table 4.
Table 4. Comparison of the different parameters of the OTA in the current study with different OTAs
available
Table in the literature.
4. Comparison of the different parameters of the OTA in the current study with different OTAs
available in the literature.
Parameters This Work [2018] [2017] Ref [7] [2015] Ref [34] [2015] Ref [35] [2015] Ref [36]
Parameters This Work [2018] [2017] Ref [7] [2015] Ref [34] [2015] Ref [35] [2015] Ref [36]
Technology (nm) 150 nm 180 nm 180 nm 350 nm 180 nm
Technology (nm) 150 nm 180 nm 180 nm 350 nm 180 nm
Topology BD (D) BD (D) GD (D) GD (S) BD (S)
Topology BD (D) BD (D) GD (D) GD (S) BD (S)
Stages Single Single Two Three Two
Stages
VDD Single
0.8 V Single
0.5 V Two
0.6 V Three 1V Two0.6 V
Gain VDD
(dB) 0.8dB
48.4 V 0.5 V
70.4 dB 0.6 V dB
90.1 1 120
V dB 0.6 V82 dB
GBWGain (dB)
(Hz) 48.4
3.1 KHzdB 70.4KHz
9.24 dB 90.1 dB
34.9 KHz 120 dB
20 KHz 82 dB KHz
19.1
GBW (Hz) 3.1 KHz 9.24 KHz 34.9 KHz 20 KHz 19.1 KHz
GM (dB) 19.01 dB 19.5 dB 20 dB - -
PM (degree) 80° 54° 62.2° 54° 60°
Electronics 2018, 7, 41 16 of 19

Table 4. Cont.

Parameters This Work [2018] [2017] Ref [7] [2015] Ref [34] [2015] Ref [35] [2015] Ref [36]
GM (dB) 19.01 dB 19.5 dB 20 dB - -
PM (degree) 80◦ 54◦ 62.2◦ 54◦ 60◦
CMRR (dB) 146.3 dB 106 dB 37 dB 70 dB 114.7 dB
PSRR (dB) 83 dB 70 dB 30.7 dB 184 dB
SR+/− (V/ms) 99.56/100 967 7.5 7.38/2.88 5.6
Power (W) 59.04 nW 64 nW 300 nW 195 nW 400 nW
THD (dB) −58.56 dB −52.4 dB −40 dB Less as SE −55.9 dB
Cap. load (pF) 1 pF 2 × 15 pF 2 × 7.5 pF 200 pF 15 pF
FOM 254.13 9828.5 78.6 90.83 21.92
where BD and GD represent bulk driven and gate driven topologies, respectively. S and D represent the single
ended and fully differential structures, FOM represents figure of merit and VDD represents the supply voltage.

From Table 4, it can be seen that a high CMRR, low power, greater PM and low THD were
achieved and were found to be favorable, compared to the results available in the literature. Due to
the differential nature of the structure, even harmonics were suppressed and the odd harmonics were
reduced by using cross coupled differential pairs, which helps in achieving a low THD below 55 dB.
The technology used was 150 nm which is a reduced size compared to others in the literature. The
circuit works well up to a supply voltage of 0.6 V, which can further reduce the power up to 44.2 nW,
but the output swing will be reduced for such low voltages; therefore, the supply voltage was kept at
0.8 V. To compare the proposed work with state of the art technologies, a figure of merit (FOM) was
adopted, which can be calculated by

( DC gain(dB))( Gainbandwidth(KHz))(Slewrate(V/ms))
FOM = (28)
Power dissipation(nW )

The designed OTA circuit can be used in different applications, such as amplifiers, filters,
oscillators, data converters, etc. In terms of portable biomedical applications, it can be used in
ECGs, EEGs, EMGs, neural recording networks, etc., as its power consumption is low which makes it
suitable for portable devices.

6. Conclusions
This paper presented the design of a fully differential, bulk driven OTA. The OTA comprised
a source degeneration MOS with a cross coupled differential pair to improve linearity. The bulk
driven technique was used to improve linearity and to reduce the supply voltage which removes the
threshold voltage from the signal path. Source degeneration and cross coupled techniques reduced
the transconductance which is favorable for our circuit because low transconductance is required for
low frequency applications. The transconductance obtained was 23 nA/V. A low voltage and low
power were obtained by operating the transistors in the subthreshold region, which is one of the best
options to make the circuit power efficient. The gain, GBW, PM and GM values obtained were 48.4 dB,
3.1 KHz, 80◦ and 19.01 dB, respectively. Different corner simulations were performed to check the
robustness of the circuit. Temperature effects were also observed on the ac response. The CMRR, PSRR
and slew rate+/− values were 146.3 dB, 83 dB and 99.56/100 V/ms, respectively. The circuit utilizes
self-cascode composite transistors to enhance the output resistance and thus the gain, from 32 dB to
48 dB; the self cascode MOS does not require any biasing circuitry and provides a Vth drop that is
less than that of a conventional MOS. The power of the circuit was also reduced by up to 59.04 nW
with a supply voltage of 0.8 V. The THD obtained was −58.56 dB for an input signal of 200 mVpp
at a frequency of 100 Hz. FOM was also calculated to compare the proposed work with state of the
art technology, and FOM was calculated as 254.13. The circuit was simulated in CADENCE virtuoso
environment using 150 nm LFoundry CMOS process. The obtained results prove that the circuit is
suitable for low voltage, low power and low frequency applications.
Electronics 2018, 7, 41 17 of 19

Author Contributions: Saleha Bano contributed to the idea, design and implementation of the simulation steps.
Ghous Bakhsh Narejo and Syed Muhammad Usman Ali Shah contributed in drafting and reviewing the final form.
Conflicts of Interest: The authors declare no conflict of interest.

Appendix A
To clearly understand the terms used in this paper a tabulated form of acronyms are included
which is shown in Table A1.

Table A1. Acronyms.

Acronyms Definition
Operational
OTA
transconductance amplifier
THD Total harmonic distortion
FOM Figure of merit
BD Bulk driven
GD Gate driven
GBW Gain bandwidth
GM Gain margin
PM Phase margin
SR Slew rate
Common mode rejection
CMRR
ratio
PSRR Power supply rejection ratio
SNR Signal to noise ratio
LV Low voltage
LP Low power

References
1. Rakus, M.; Stopjakova, V.; Arbet, D. Design techniques for low voltage analog integrated circuits. J. Electr. Eng.
2017, 68, 245–255. [CrossRef]
2. Raj, N.; Sharma, K.; Jasuja, A.; Gard, R. A low power OTA for biomedical applications. Cyber J. Multidiscip. J.
Sci. Technol./J. Sel. Areas Bioeng. 2010, 1–5. [CrossRef]
3. Wang, T.-Y.; Liu, L.-H.; Peng, S.Y. A power efficient highly linear reconfigurable bio-potential sensing
amplifier using gate balanced Pseudo resistors. IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 199–203.
[CrossRef]
4. Chakraborty, A. Low power low voltage operation of operational amplifier. Int. J. Res. Eng. Technol. 2015, 4,
297–300.
5. Yodtean, A.; Thanachayanont, A. Sub 1-V highly linear low power class AB bulk driven tunable CMOS
transconductor. Analog Integr. Circuits Signal Process. 2013, 73, 383–397. [CrossRef]
6. Hogervorst, R.; Huijsing, J. Design of Low-Voltage, Low-Power Operational Amplifier Cells, 3rd ed.; Springer:
Dordrecht, The Netherland, 2000; pp. 1–206, ISBN 978-1-4757-2489-9.
7. Sharan, T.; Bhadauria, V. Fully differential, bulk driven, class AB, sub-threshold OTA with enhanced slew
rates and gain. J. Circuits Syst. Comput. 2017, 26, 1750001. [CrossRef]
8. Sharan, T.; Chetri, P.; Bhadauria, V. Ultra-low-power bulk-driven fully differential subthreshold OTAs with
partial positive feedback for Gm-C filters. Analog Integr. Circuits Syst. 2018, 94, 427–447. [CrossRef]
9. Carrillo, J.M.; Torelli, G.; P-Aloe, R.; Valverde, J.M.; D-Carrillo, J.F. Single-pair bulk driven CMOS input stage:
A compact low-voltage analog cell for scaled technologies. Integr. VLSI J. 2010, 43, 251–257. [CrossRef]
10. Raikos, G.; Vlassis, S. 0.8V bulk driven operational amplifier. Analog Integr. Circuit Signal Process. 2010, 63,
425–432. [CrossRef]
11. Carvajal, R.G.; R-Angulo, J.; L-Martin, A.J.; Torralba, A.; Galan, J.A.G.; Carlosena, A.; Chavero, F.M.
The flipped voltage follower: A useful cell for low voltage low power circuit design. IEEE Trans. Circuits
Syst. I 2005, 52, 1276–1291. [CrossRef]
Electronics 2018, 7, 41 18 of 19

12. Rodriguez-Villegas, E.; Yufera, Y.; Reuda, A. A 1.25V micropower Gm-C filter based on FGMOS transistor
operating in weak inversion. IEEE J. Solid State Circuits 2004, 39, 100–111. [CrossRef]
13. Lo, T.-Y.; Hung, C.C. A 1-V 50 MHz pseudo differential OTA with compensation of mobility reduction.
IEEE Trans. Circuits Syst. II 2007, 54, 1047–1051. [CrossRef]
14. Szczepanski, S.; Pankiewicz, B.; Koziel, S.; Wojcikowski, M. Multiple output differential OTA with linearized
bulk driven active-error feedback loop for continuous time filter applications. Int. J. Circuit Theory Appl.
2015, 43, 1671–1686. [CrossRef]
15. Cotrim, E.D.C.; Ferreira, L.H.C. An ultra-low-power CMOS symmetrical OTA for low-frequency Gm-C
applications. Analog Integr. Circuits Signal Process. 2012, 71, 275–282. [CrossRef]
16. Khateb, F.; Biolek, D.; Khatib, N.; Vávra, J. Utilizing the Bulk-driven technique in analog circuit design.
In Proceedings of the IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits
and Systems (DDECS), Vienna, Austria, 14–16 April 2010.
17. Ferreira, L.H.C.; Pimenta, T.C.; Moreno, R.L. An ultra–low-voltage ultra-low power MOS miller OTA with
rail-to-rail input/output swing. IEEE Trans. Circuits Syst.-II Express Briefs 2007, 54, 843–847. [CrossRef]
18. Sharan, T.; Bhadauria, V. Sub-threshold, cascode compensated, bulk driven OTAs with enhanced gain and
phase margin. Microelectron. J. 2016, 54, 150–165. [CrossRef]
19. Azhari, S.J.; Rezaei, F. High linear, high CMRR, low power OTA with class AB output stage. Int. J. Comput.
Theory Eng. 2010, 2, 473–477. [CrossRef]
20. Mincey, J.S.; Briseno-Vidrios, C.; Martinez, J.S.; Rodenbeck, C.T. Low-power Gm-C filter employing current
re-use differential difference amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 2017, 64, 635–639.
[CrossRef]
21. El Mourabit, A.; Lu, G.; Pittet, P. Wide linear range sub-threshold OTA for low power, low voltage and low
frequency applications. IEEE Trans. Circuits Syst. I 2005, 52, 1481–1488. [CrossRef]
22. Worapishet, A.; Naphaphan, C. Current feedback source degenerated CMOS transconductor with very high
linearity. Electron. Lett. 2003, 39, 17–18. [CrossRef]
23. Kwon, K.; Kim, H.T.; Lee, K. A 50–300 MHz highly linear and low noise CMOS Gm-C filter adopting multiple
gated transistors for digital TV tuner ICs. IEEE Trans. Microw. Theory Tech. 2009, 57, 306–313. [CrossRef]
24. Razaei, F.; Azhari, S.J. Transconductor linearization based on adaptive biasing of source degenerative MOS
transistors. Circuits Syst. Signal Process. 2015, 34, 1149–1165. [CrossRef]
25. Moreno, R.F.L.; Baruqui, F.A.P.; Petraglia, A. Bulk-tuned Gm-C filter using current cancellation.
Microelectronics 2015, 46, 777–782. [CrossRef]
26. Kim, D.; Kim, B.; Nam, S. A transconductor and tunable Gm-C high-pass filter linearization technique using
feed forward Gm cancellation. IEEE Trans. Circuits Syst. II Express Brief 2015, 62, 1058–1062. [CrossRef]
27. Lee, S.-Y.; Cheng, C.-J. Systematic design and modeling of OTA-C filter for portable ECG detection.
IEEE Trans. Biomed. Circuits Syst. I 2009, 3, 53–64. [CrossRef] [PubMed]
28. Abbasalizadeh, S.; Sheikhaei, S.; Forouzandeh, B. A 0.9 V supply OTA in 0.18 um CMOS technology and its
application in realizing a tunable low-pass Gm-C filter for wireless sensor networks. Circuits Syst. 2013, 4,
34–43. [CrossRef]
29. Sarrafinazhad, A.; Kara, I.; Baskaya, F. Design of a digitally tunable 5th order Gm-C filter using linearized
OTA in 90 nm CMOS Technology. In Proceedings of the International Symposium on Signals, Circuits and
Systems (ISSCS), Iasi, Romania, 9–10 July 2015.
30. Ferreira, L.H.; Pimento, T.C.; Moreno, R.L. An ultra-low-voltage ultra-power weak inversion composite
MOS transistor: Concept and applications. IEICE Trans. Fundamental Commun./Electron. Inf. Syst. 2002,
E-85/A/B/C/D, 1–6. [CrossRef]
31. Jihai, D.; Chuang, L.; Weilin, X.; Baolin, W. OTA-C filter for ECG acquisition systems with highly linear range
and less pass band attenuation. J. Semicond. 2015, 36. [CrossRef]
32. Soares, C.F.T.; de Maoraes, G.S.; Pertaglia, A. Low transconductance OTA with improved linearity suitable
for low frequency Gm-C filters. Microelectronics 2014, 45, 1499–1507. [CrossRef]
33. Sun, C.-Y.; Lee, S.-Y. A fifth order Butterworth OTA-C LPF with multiple output differential input OTA-C
filter for ECG applications. IEEE Trans. Circuits Syst. II Express Brief 2017. [CrossRef]
34. Akbari, M.; Nazari, M.; Sharifi, L.; Hashemipour, O. Improving power efficiency of a two stage operational
amplifier for biomedical applications. Analog Integr. Circuits Signal Process. 2015, 84, 173–183. [CrossRef]
Electronics 2018, 7, 41 19 of 19

35. Grasso, A.D.; Marano, D.; Palumbo, G.; Pennisi, S. Design methodology of subthreshold three-stage CMOS
OTS suitable for ultra-low power low area and high driving capability. IEEE Trans. Circuit Syst. I 2015, 62,
1453–1462. [CrossRef]
36. Akbari, M.; Hashemipour, O. A 0.6 V, 0.4uW bulk driven operational amplifier with rail to rail input/output
swing. Analog Integr. Circuits Signal Process. 2016, 86, 341–351. [CrossRef]

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