Low-power high-speed full adder for to a strong-one (Vdd) accordingly.

In this way, the output of the

portable electronic applications NMOS multiplexer is reshaped with an improved output driving
capability.
C.-K. Tung, S.-H. Shieh and C.-H. Cheng
B

A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is

presented as an elegant way to reduce circuit complexity and improve
the performance thereof. Employing as few as 15 MOSFETs in total, H Co ¢

an LPHS-FA requires 60–73% fewer transistors than other existing

FAs with drivability. For validation purpose, HSPICE simulations Ci

are conducted on all the proposed and referenced FAs based on the
TSMC 0.18-μm CMOS process technology. The LPHS-FA is found H
to provide a 20.4–21.2% power saving, a 12.3–67.0% delay time H¢ Co
reduction and a 35–102% reduction in power delay product compared H¢
with the referenced FAs. In short, an LPHS-FA is presented in a
concise form as a high-performance FA in practical applications.
A A
a b

Introduction: Owing to the rapid growth in portable electronic devices H

with constraint of power, it becomes a critical challenge as well as a

Ci
competitive task to design high performance, small chip area and low
power consumption circuits to enhance product competitiveness for
H¢ So
integrated circuit designers nowadays. The full adder (FA) is regarded
as the most significant and crucial building block in an arithmetic unit
Co¢
of portable devices in today’s highly competitive markets. Therefore it
becomes a hot issue to design a low-power, high-speed FA H
(LPHS-FA) occupying a small chip area. c
As referred to previously, the performance of an arithmetic circuit is
found directly subject to all the FAs employed, stimulating the develop- Fig. 1 Modules in LPHS-FA
ment of a wide variety of FAs for various applications. As suggested in a XOR–XNOR module
[1, 2], a smaller number of transistors are adopted to achieve the aim of b Carry module
c Sum module
chip area reduction, but the accompanying disadvantages are threshold
voltage loss, a low noise margin and a low-output driving capability. In
contrast, a large number of studies have been conducted on features
Ci
elevation [3–6], e.g. low power consumption, high-speed arithmetic
operation, improved output driving capability, full-swing voltage and B So
so forth. Yet, the price paid is that it inevitably requires a greater
number of transistors, a larger chip area and higher circuit complexity. H
A state-of-the-art FA (NEW-HPSC) is designed using a combination
of pass transistor logic (PTL) and static CMOS design techniques to
provide high energy efficiency and improve driving capability [4]. For Co¢
further performance improvement, a hybrid-CMOS FA is proposed in H¢

[5] to achieve better power-delay product (PDP). An energy efficient

CMOS FA is implemented using swing restored complementary
pass-transistor logic (SR-CPL) and PTL techniques to optimise its
PDP [6].
Thus, this Letter presents a simple structured, high-performance FA
by use of the PTL design technique as an elegant way to advance the
overall performance of an arithmetic circuit and electronic devices.
Circuit design and analysis of proposed LPHS-FA: For performance
improvement and circuit complexity reduction, Boolean functions of
the LPHS-FA are reformulated as
So = H ′ Ci + HCo′ (1)
Co = HCi + H A ′
(2)
where H = A ⊕ B and H ′ = A ⊙ B. An LPHS-FA is made up of an
XOR–XNOR module, a sum module and a carry module. As illustrated
in Fig. 1a, the XOR–XNOR module performs XOR and XNOR logic
operations on inputs A and B, and then generates the outputs H and
H′. Subsequently, H and H′ both are applied to the sum and the carry
modules for generation of sum output So and carry output Co.
For the purpose of complexity reduction and output driving capability
enhancement, both the sum and the carry modules are realised with mul-
tiplexers. The carry module, as configured in Fig. 1b, is particularly
implemented by an NMOS multiplexer. Both H and H′ are applied to
the NMOS multiplexer as the control signals, whereas Ci and A are
the input signals to perform the operation in (2). In the simple structured
NMOS multiplexer consisting of two NMOS transistors, the carry signal
is propagated in a highly efficient manner, but an accompanying disad-
vantage is the existence of a weak-one signal level, which can be pulled
up to Vdd through an energy storage technique by combination of an
inverter and a pull-up PMOS transistor. In other words, the weak-one
signal level at node Co is inverted to ‘0’ at node C′o to enable the
pull-up transistor PMOS, and the signal level at node Co is pulled up
Co
A
Fig. 2 Circuit schematic of proposed LPHS-FA
In contrast, the sum module, as illustrated in Fig. 1c, is implemented
by a transmission gate (TG)-based multiplier. Both H and H′ are applied
to the multiplexer as the control signals, whereas Ci and C′o are the input
signals to perform the logical operation in (1). Taking Ci and C′o as the
input to the multiplexer, the sum module acquires a simple structure
advantage and an improved output driving capability. A good use of
the PTL technique in the circuit design gives rise to a simple configured
and elegant FA.
Based on the modules depicted in Fig. 1, a simple structured FA with
reduced complexity and improved performance is designed for a high-
speed arithmetic circuit. This proposed FA LPHS-FA, as shown in
Fig. 2, demonstrates low-power and high-speed advantages, and
merely requires 15 MOSFETs to implement.
Results and discussion: For performance validation, simulation com-
parisons are made among LPHS-FA, NEW-HPSC, hybrid-CMOS and
SR-CPL FAs. All the HSPICE simulations are performed on these
FAs based on the TSMC 0.18 μm CMOS process technology. For an
objective comparison, all the adders are simulated involving identical
transistors under the same test conditions.
The FA simulation results at input frequency f = 100 MHz and Vdd =
1.8 V are tabulated in Table 1. It is revealed that an LPHS-FA exhibits a
power (Pd) saving of 20.4–21.2%, a delay time (Td) reduction of 12.3–
67% and a PDP improvement of 35–102%. An LPHS-FA merely
employs 15 MOS transistors, which is 60–73% lower transistor count
than that required in other types of FAs. In this way, a smaller chip
area is occupied, leading to a reduced cost for the FA directly. The

ELECTRONICS LETTERS 15th August 2013 Vol. 49 No. 17

LPHS-FA has low power dissipation because of its low transistor count, C.-K. Tung (Ph.D. Program of Electrical and Communications
PTL- and TG-based building blocks and all full-swing nodes structure Engineering, Feng Chia University, Taichung, Taiwan)
without the threshold loss problem. The high-speed feature gained for S.-H. Shieh (Department of Electronic Engineering, National Chin-Yi
the LPHS-FA, thanks to the carry propagation path, has merely one University of Technology, Taichung, Taiwan)
pass transistor delay. Drivability of the LPHS-FA is guaranteed by its
all full-swing nodes structure and positive feedback loop structure at E-mail: ssh@ncut.edu.tw
Co node. In a brief conclusion, a superior performance is demonstrated C.-H. Cheng (Department of Electronic Engineering, Feng Chia
by the LPHS-FA relative to other types of FAs in any case. University, Taichung, Taiwan)
C.-K. Tung: Also with the Department of Electronic Engineering,
Table 1: Simulation results for various FAs with drivability at an National Chin-Yi University of Technology, Taichung, Taiwan
input frequency of 100 MHz
References Transistor count Pd (μW at 1.8 V) Td (ns) PDP (μW × ns) References
[4] 26 6.951 0.299 2.078 1 Bui, H.T., Wang, Y., and Jiang, Y.: ‘Design and analysis of low-power
[5] 24 6.907 0.278 1.920 10-transistor full adders using novel XOR–XNOR gates’, IEEE Trans.
[6] 26 6.910 0.201 1.388 Circuits Syst. II, 2002, 49, (1), pp. 25–30
2 Lin, J.-F., Hwang, Y.-T., Sheu, M.-H., and Ho, C.-C.: ‘A novel high-
This work 15 5.736 0.179 1.026
speed and energy efficient 10-transistor full adder design’, IEEE Trans.
Circuits Syst. I, 2007, 54, (5), pp. 1050–1059
Conclusion: As the core of an arithmetic circuit, that is a key module in 3 Radhakrishnan, D.: ‘Low-voltage low-power CMOS full adder’, IEE
a large number of portable electronic systems, an LPHS-FA is presented Proc., Circuits Devices Syst., 2001, 148, (1), pp. 19–24
in this Letter as a way to simplify the circuit architecture and hence 4 Chang, C.-H., Gu, J., and Zhang, M.: ‘A review of 0.18-um full adder
improve the performance. For performance validation, HSPICE simu- performances for tree structured arithmetic circuits’, IEEE Trans. Very
lations were conducted on FAs implemented with TSMC 0.18 μm Large Scale Integr. (VLSI) Syst., 2005, 13, (6), pp. 686–695
CMOS process technology in aspects of power consumption, delay 5 Goel, S., Kumar, A., and Bayoumi, M.A.: ‘Design of robust,
energy-efficient full adders for deep-submicrometer design using
time and PDP. In contrast to other types of LPFAs with drivability, an
hybrid-CMOS logic style’, IEEE Trans. Very Large Scale Integr.
LPHS-FA is superior to the other ones and can be applied to design (VLSI) Syst., 2006, 14, (12), pp. 1309–1321
related adder-based portable electronic products in practical applications 6 Aguirre-Hernandez, M., and Linares-Aranda, M.: ‘CMOS full-adders for
in today’s competitive markets. energy-efficient arithmetic applications’, IEEE Trans. Very Large Scale
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© The Institution of Engineering and Technology 2013
16 April 2013
doi: 10.1049/el.2013.0893

ELECTRONICS LETTERS 15th August 2013 Vol. 49 No. 17