A Low Complexity Splitter Based Parallel

Multiplier for DSP Applications

Arvind Chakrapani, T.Elanchezian,

G.Karthikeyan, N.Divya, K.Kabilarasan
& Chinchu Joseph
Proceedings of the National Academy
of Sciences, India Section A: Physical
Sciences
ISSN 0369-8203
Volume 85
Number 2
Proc. Natl. Acad. Sci., India, Sect. A Phys.
Sci. (2015) 85:277-281
DOI 10.1007/s40010-014-0193-x

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Proc. Natl. Acad. Sci., India, Sect. A Phys. Sci. (AprilJune 2015) 85(2):277281
DOI 10.1007/s40010-014-0193-x

RESEARCH ARTICLE

A Low Complexity Splitter Based Parallel Multiplier for DSP

Applications
Arvind Chakrapani T. Elanchezian G. Karthikeyan
N. Divya K. Kabilarasan Chinchu Joseph

Received: 27 June 2013 / Revised: 18 August 2014 / Accepted: 18 November 2014 / Published online: 7 February 2015
The National Academy of Sciences, India 2015

Abstract This paper proposes a splitter based parallel

multiplier (SBPM) for both signed and unsigned numbers.
The proposed SBPM reduces the number of partial products by a factor of two and demands lesser computational
complexity compared to Booth multiplier. The synthesis
report shows that SBPM is efficient when compared to
Booth multiplier in terms of hardware requirements including number of multiplexers, Ex-OR operations, slices
and 4 inputs look up table. Simulation result for 8 9 8
SBPM shows that the critical path delay is about 83.5 % of
that of Booth multiplier for unsigned numbers and about
72.71 % for signed numbers.
Keywords Binary multiplier
Parallel multiplier

Booth multiplier
Wallace tree multiplier

1 Introduction
The ever demanding need for high speed application have
replaced the microprocessors and its controllers by digital
signal processors. Since multipliers being the heart of
digital signal processors has to be efficient in terms of
speed, power, consumption and layout area or even a
combination of them. Most of the signals processing operations in recent applications are non-linear functions
A. Chakrapani (&)
Department of Electronics and Communication Engineering,
Info Institute of Engineering, Coimbatore 641 107, India
e-mail: arvichakra@gmail.com
T. Elanchezian
G. Karthikeyan
N. Divya
K. Kabilarasan

C. Joseph
Department of Electronics and Communication Engineering,
Tamilnadu College of Engineering, Coimbatore 641 659, India

which includes convolution, discrete Fourier transform

(DFT), discrete cosine transform (DCT) and discrete
wavelet transform (DWT). But the above mentioned tasks
were accomplished by repeated multiplication and addition
operations. Hence design of novel multipliers is an active
research topic and also makes them favorable for realizing
high speed and compact VLSI systems involving signal
processing.
Various multiplexers including Booth algorithm (BA)
and modified Booth algorithm (MBA) emphasized on the
fact that efficient multipliers can be designed by reducing
the number of partial products. Later researchers suggested
the idea of combining the advantages of different multipliers in order to design new multipliers. The execution
speed and performance of a parallel multiplier depends on
reducing the number of partial products. Wallace tree
multiplier [1] performs as a conventional multiplier to
produce n partial products for n bit numbers as multiplier
input. It gets complicated when input exceeds 32 bits due
to more number of half adders and full adders are required
and also it slows down the multiplication process. Even
though Booth multiplier [2] produces n/2 partial products
for n inputs it involves more computational complexity due
to the presence of 2s complement operation and summing
of overlapped partial products to compute the multiplier
result.
Erle et al. [3] employed a binary carry-save addition for
an efficient non-iterative pipelined implementation based
on Verilog register transfer level model to achieve better
latency and throughput performance when compared to
area. Vazquez et al. [4] suggested an architecture for parallel multiplier which generates reduced partial products
based on a multi operand tree structure. While Khan et al.
[5] introduced an energy efficient 16-bit multiplier architecture by employing Booth algorithm. The input data has to

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A. Chakrapani et al.

Fig. 1 Block diagram of splitter based parallel multiplier

be processed in its 2s complement form and the proposed

work ignored the hardware requirements for realizing the
multiplier architecture. Rao and Dubey [6] proposed a high
speed multiplier using modified Booth algorithm and
compression adder for high speed arithmetic circuits.
Baba and Rajaramesh [7] proposed a parallel multiplier
in which half the partial products are generated using
modified Booth encoder and an additional partial product is
produced by extending the sign bit. Carry save adder
(CSA) and carry look ahead adder is used as building block
to speed up the multiplication operation. Since design of
binary multipliers for high speed arithmetic circuits is
needed, we propose a multiplier splitter based architecture
to perform binary multiplication.

2 Splitter Based Parallel Multiplier (SBPM)

This section proposes a splitter based parallel multiplier
(SBPM) which is a hardware efficient Multiplier for both
unsigned and signed numbers when compared to that of

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Booth multiplier. The proposed n-bit parallel multiplier is

designed to reduce the number of partial products from n to
n/2 and also provides the result comparatively faster than
the existing multiplier.
The block representation of the proposed SBPM is
presented in Fig. 1 and it comprises of three functional
units namely multiplier splitter, multiplier splitter based
partial product generator (MSBPPG) and Wallace tree
adder (WTA). MSBPPG is the main building block of
SBPM which comprises of two sub blocks namely partial
product array (PPA) and 4 to 1 multiplexer is illustrated in
Fig. 2. This block receives input from both multiplier and
multiplicand bits, based in the pair of multiplier bits the
partial products are generated. The mandatory requirement
of the 2s complement representation of the multiplicand
bits is not required in the proposed method and hence leads
to low computational complexity.
In the block diagram of SBPM, n stipulates the number
of bits in the multiplier and multiplicand. The multiplicand
(A) is directly given as the input of PPA and it is designed
to produce the number of feasible partial products by

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Parallel Multiplier for DSP Applications

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Fig. 2 Multiplier splitter based

partial product generator

on the combination of selection lines the multiplicand is

scaled by its respective decimal value. The conventional
Wallace tree adder is used to add the partial products only.
In Wallace tree multiplier (WTM) each bit of the multiplier
is multiplied with multiplicand, therefore to multiply
n*n in WTM n partial products are obtained whereas in our
proposed SBPM a pair of bit (two bits) in multiplier are
multiplied with multiplicand based on the selection table
given in Table 1. Therefore to multiply n*n bits using
SBPM, n/2 partial products are obtained thereby reducing
the number of partial products by 50 %.
The sign detector block employs basic Ex-OR operation
to compute the sign bit of the resulting product in the case
of both signed and unsigned numbers Tables 2 and 3.

Table 1 Selection Table for partial product computation in SBPM

B1

B0

Partial Products

0 9 Multiplicand

1 9 Multiplicand

2 9 Multiplicand

3 9 Multiplicand

multiplying the multiplicand (A) with 4 different weights

such as 0, 1, 2, 3 based on the multiplier splitter. Multiplier
splitter is used to split the multiplier into 2 bit (n/2) sequence which acts as the selection lines (B1, B0) of the 4 to
1 multiplexer. While calculating the partial products, based

Table 2 Synthesis report for unsigned multipliers

Device utilization

Booth multiplier

Wallace tree multiplier

Splitter based parallel multiplier

Multiplexers

10-bit 8:1MUX (5)

10-bit 4:1MUX (4)

Total XORS

58

65

42

1-bit XOR2

27

19

12

1-bit XOR3

31

46

30

No. of Slices

88 out of 960 (9 %)

86 out of 960 (8 %)

71 out of 960 (7 %)

No. of 4 input LUT

160 out of 1920 (8 %)

150 out of 1920 (7 %)

131 out of 1920 (6 %)

No. of IOs

34

32

34

Delay

41.428 ns

47.635 ns

34.595 ns

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Table 3 Synthesis report for signed multipliers

Device utilization

Booth multiplier

Splitter based parallel multiplier

Multiplexers

1-bit 4:1 MUX (16) 10-bit 8:1 MUX (4)

10-bit 4:1 MUX (4)

Total XORS

59

42

1-bit XOR2

35

12

1-bit XOR3

24

30

No. of Slices

108 out of 960 (11 %)

71 out of 960 (7 %)

No. of 4 input LUT

203 out of 1,920 (10 %)

131 out of 1,920 (6 %)

No. of IOs

37

37

Delay

47.635 ns

34.639 ns

Fig. 3 Wallace tree adder

PP07 PP06 PP05 PP04 PP03
PP17

PP02 PP01 PP00

PP16 PP15 PP14 PP13 PP12 PP11 PP10

PP27 PP26 PP25 PP24 PP23 PP22 PP21 PP20

PP37 PP36 PP35 PP34 PP33 PP32 PP31 PP30

Partial
Product 0
Partial
Product 1
Partial
Product 3
Partial
Product 4

Fig. 4 Simulation output of SBPM for unsigned numbers

The partial product is chosen based on the selection

table. Finally all the partial products are arranged in a
Wallace tree adder as given in Fig. 3.
The steps followed in SBPM are summarized below
(i)
(ii)

Express the given numbers into binary form.

Multiplier bits are sub divided into 2 bits which acts
as selection lines.
(iii) Multiply the multiplicand with different weights (0,
1, 2 and 3).
(iv) Based on the selection line, any one of the partial
products is selected.
(v) Add the partial products by using Wallace tree adder.
(vi) Deduce the sign bit for the resulting product.

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3 Simulation and Synthesis Result Analysis

The simulation results of the proposed SBPM for unsigned
and signed numbers are given in Fig. 4 and 5 respectively.
The proposed SBPM is coded in very high speed integrated
circuit hardware description language (VHDL) to perform
simulation and it is synthesized using Xilinx ISE tool.
Based on the synthesis report it is evident that SBPMs
hardware requirements for implementation and the computational time are lesser compared to Booth multiplier.
Since the proposed multiplier is a parallel multiplier, it can
be used in multiply and accumulate (MAC) unit of a digital
signal processor and it involves a single processor cycle to
fetch, execute the instruction and also to store the result.

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Fig. 5 Simulation output of SBPM for signed numbers

Moreover the proposed architecture of SBPM involves

computationally efficient MSBPPG and Wallace tree adder
such that trade-off between execution speed and computational complexity is reduced.

for constructing high speed multipliers for digital signal

processors.

References
4 Conclusion
The proposed splitter based multiplier is designed and
synthesized to produce the product faster and also overcomes the limitation of other basic multipliers. The performance analysis shows that the hardware requirement for
implementing the proposed SBPM both signed and unsigned number is less compared to that of Booth multiplier
and Wallace tree multiplier. The synthesis report also
shows that the computational time of SBPM is about
12.996 and 6.833 ns lesser compared to Booth multiplier
for signed and unsigned numbers respectively. Even
though the SBPM is simulated for a 8 9 8 multiplier, it can
be extended even for multiplier with arbitrary number of
bits. Hence the low complexity SBPM is a feasible method

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