Natl. Acad. Sci. Lett.
https://doi.org/10.1007/s40009-021-01061-y
SHORT COMMUNICATION
Energy-Efficient Hybrid Full Adder (EEHFA) for Arithmetic
Applications
Thiruvengadam Rajagopal1 • Arvind Chakrapani2
Received: 15 September 2020 / Revised: 4 November 2020 / Accepted: 8 June 2021
Ó The National Academy of Sciences, India 2021
Abstract A high performance and energy-efficient 1-bit
full adder (FA) circuit is proposed. For circuit validation,
Cadence simulation is performed on the proposed and
conventional FAs using 45 nm CMOS process technology.
The proposed circuit achieves 19.68–65.33% saving in
energy and 22.80–85.44% reduction in energy delay pro-
duct (EDP) when compared to other reported adders.
Monte Carlo simulation reveals that the proposed design
yields good functionality and robustness against process
variation. The design has been extended up to 32-bit adder.
In short, the proposed adder offers comparable improve-
ment in terms of power consumption, speed, energy and
EDP.
Keywords Adder  CMOS  Energy-efficient 
High-speed  Hybrid  Monte Carlo simulation 
VLSI
Significant statement Single bit FA circuit is an essential
module in arithmetic circuits such as adders, multiplier and
MAC unit in recent digital signal processors. Reduction of
energy consumption in adder improves the overall
& Thiruvengadam Rajagopal
thirukvp@gmail.com
Arvind Chakrapani
arvichakra@gmail.com
1
Department of Electronics and Communication Engineering,
Tamilnadu College of Engineering, Coimbatore, Tamilnadu
641659, India
2 overall circuit. It supports the high-speed operation due to
Department of Electronics and Communication Engineering,
Karpagam College of Engineering, Coimbatore 641032,
Tamilnadu, India
performance of the subsystems in portable device appli-
cations. Hence, a high performance and energy-efficient
1-bit CMOS FA is proposed to support the realization of
arithmetic circuits in modern digital systems.
Low power, high performance and energy-efficient
VLSI systems are widely used in portable devices,
biomedical instruments and multistandard wireless recei-
vers. Adder is the main block of an arithmetic unit. Several
adders are combined to construct an advanced digital signal
processor (DSP). An efficient adder cell design improves
the performance of complex DSPs. Reduction of power
consumption and improving speed of the multiply and
accumulate unit is very important for the design of DSP
chip [1]. Optimizing the transistor size in a circuit is a
desired approach to reduce energy [2]. Different logic
styles were investigated to implement energy-efficient FA
[1, 3]. In this letter, we propose an energy-efficient adder
with low power and high speed. It uses the features of pass
transistor and transmission gate logic. The performance
parameters of the proposed hybrid adder are compared with
other conventional adders such as the 28 transistors CMOS
[4], DPL [5], SR-CPL [5], Hybrid1 [6] and Hybrid2 [7].
The design was initially executed for 1 bit and it is
extended to 8, 16 and 32 bit adder to justify the optimal
features of the proposed adder. Monte Carlo simulation is
performed to validate its robustness against process and
mismatch variation in chip design.
There are three major modules in the proposed design:
XOR–XNOR, carry and sum. The proposed XOR–XNOR
module based on pass transistor logic produces balanced
full swing outputs. Simultaneous XOR–XNOR avoids
glitches in the output and improves the performance of the
cross-coupled PMOS pull-up and NMOS pull-down tran-
sistors. As illustrated in Fig. 1a, the logic operations such
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 T. Rajagopal, A. Chakrapani

are the complementary control signals to this transmission

gate. This module propagates the Cin signal to the output
when H is at logic ‘‘0’’ and H is at logic ‘‘1’’. Two NMOS
pull-down transistors in series with two PMOS pull-up
transistors are used to generate A  B, while Cin , A and B are
the input signals given to the carry module to perform the
operation in (1). The symmetric structure of carry module
leads to a compact layout and reduces the signal path delay.
The driving capability is improved by the inverter
employed at the output stage.
(a) Figure 1c shows a five transistor sum module [9] used in
FA to eliminate threshold loss at the output. This circuit
uses the intermediate H, H and input Cin signals to perform
the logical operation (2). It do not suffer from output
voltage loss and have been widely used in adder imple-
mentation [1]. The output signal of this module reaches
either power supply or ground connection, thereby it
eliminates the direct path and the subsequent short circuit
current between the supply rails.
The three modules are interconnected to design a high-
speed and energy-efficient FA for arithmetic applications.
(b) (c) Figure 1d shows that the schematic of proposed FA design,
which operates at high speed and consumes less power
with full swing output voltage.
The simulations are performed by using cadence tool in
45 nm CMOS technology with a 1.1 V nominal supply
voltage in room temperature. The layout of proposed
design is presented in Fig. 2. The parasitic capacitances
and resistances are extracted from the layout, and it is
considered during post-layout simulation.
For an impartial comparison, all the FA designs are
simulated under the same loading and operating conditions.
By transistor sizing optimization of the FAs considered, the
delay is reduced without compromising the power dissi-
pation. However, the power delay product (PDP) reduces
drastically. All adders were optimized toward PDP (en-
(d)
ergy) by an iterative process after post-layout simulation
Fig. 1 Modules in EEHFA a XOR–XNOR module, b carry module and the corresponding size of transistors are chosen.
[8], c sum module [9], d schematic of proposed EEHFA Optimized transistor size (width in lm) of the proposed

as XOR and XNOR are performed by XOR–XNOR mod-

ule on inputs A and B and generate the intermediate output
H ¼ A  B and H ¼ A  B simultaneously. Both H and H
are passed to the sum and carry modules, in order to pro-
duce carry Cout and sum So output signals expressed as
Cout ¼ H  Cin þ A  B ð1Þ

So ¼ H  Cin þ H  Cin ð2Þ

A carry module, as illustrated in Fig. 1b, is realized by

using the features of transmission gate and the static
CMOS inverter. A transmission gate preceded by a CMOS
inverter is used to implement ðA  BÞ  Cin . Here, H and H
Fig. 2 Layout of proposed FA (3:55  1:875 lm2)

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Energy-Efficient Hybrid Full Adder (EEHFA) for Arithmetic Applications
adder is mentioned in Fig. 1d, while maintaining the
minimal channel length.
The delay time is calculated from 50% voltage level of
both input and output signal transitions. All low-to-high
and high-to-low output transitions (32 transitions) have
been tested. The average delay time is measured as adder
delay. To test the circuit performance, different supply
voltages and loading conditions are applied.
The performance validation is carried out among six
different FAs. The post-layout simulation results at supply
voltage 1.1 V and input frequency 50 MHz are listed in
Table 1.
(a) Power and delay The simulation result shows that the
EEHFA cell consumes 16.4%, 19.9%, 16% and 19.9%
less power than the DPL, SRCPL, Hybrid1 and
Hybrid2, respectively. The power consumption of the
proposed adder is significantly less than CMOS adder
but with reduced supply voltage, the power consump-
tion is minimized further. With respect to speed, due
to layout regularity and reduced interconnectivity the
propagation delay is improved around 1:25, 2:40
and 2:31 when compared with the CMOS, Hybrid1
and Hybrid2 FA, respectively.
(b) Energy and EDP The result presents the lowest
energy metric, up to 65.3% of saving, due to
combined reduction of propagation delay and power
consumption. The energy consumption under various
load (1–6 fF) is presented in Fig. 3a, which ensures
the energy efficiency of the proposed design among
the existing FAs. When compared to Hybrid1 and
Hybrid2, the EDP is more than six times lower.
(c) Voltage scaling Figure 3b shows energy (normalized
to 1 at 0.8 V) as a function of supply voltage. At
0.6 V, the energy consumption of EEHFA is reduced
27.21%, 40.72% and 47.58% when compared to
CMOS, SRCPL and DPL, respectively. Hybrid1 and
Hybrid2 adder fails to operate below 0.85 V and
1.0 V, respectively. Hence, the proposed EEHFA
exhibits circuit functionality and robustness against
supply voltage scaling.
Table 1 Analysis of various FAs
Design Power (nW) Delay (ps)
CMOS [4] 651.29 172.63
DPL [5] 770.50 143.17
SRCPL [5] 804.19 144.31
Hybrid1 [6] 766.24 330.52
Hybrid2 [7] 804.14 317.97
EEHFA 643.98 137.58
(d) Area The proposed FA requires 38.7% less area than
the CMOS adder which is one of the reason to achieve
low power consumption and delay. Proposed FA has
less transistor count, and hence, it has low parasitic
capacitance than CMOS, DPL, SRCPL and Hybrid1
adders.
(e) Higher order circuitry The 1-bit adder cell has been
extended to different bit-width. Figure 3c, d shows the
behavior of energy consumption and EDP when the
EEHFA is extended to increased bit-width. Hybrid2
adder fails in their functionality when extended to 32
bits. The proposed adder exhibits remarkable perfor-
mance in both single and extended form when
compared to the reported designs.
(f) Process sensitivity To understand the process variation
impact on the performance characteristics of the
proposed EEHFA, we performed Monte Carlo simu-
lation with 1000 samples by considering both process
variation and mismatch. It achieves a mean value of
97.90 aJ on energy, which is 12.1–67% less when
compared to conventional designs. Maximum energy
spread occurs within the 3r (r—standard deviation)
limit without any functionality error.
A high-speed and energy-efficient hybrid FA which is a
key module in an arithmetic circuit is presented in this
letter. It uses pass transistors and transmission gates. Low
energy is targeted in the transistor-design level. The post-
layout simulation was carried out on FAs implemented
with 45 nm CMOS process technology with respect to
power consumption, speed, energy and EDP. The proposed
adder consumes less energy and operates at high speed
under different load conditions owing to the proposed
XOR–XNOR module. The simulation results show that the
energy consumption of proposed design 38.06%, 20.60%,
26.40% and 58.72% improvement when compared to
CMOS, DPL, SRCPL and Hybrid1 adder, respectively,
when the bit-width extended to 32 bits. The proposed
design works flawlessly when increasing the bit-width and
it has less sensitivity against process variation. The pro-
posed design has superior performance than other
Energy (aJ) EDP (normalized) Transistor count
112.44 1.59 28
110.31 1.30 28
116.05 1.37 26
253.26 6.87 30
255.69 6.67 22
88.60 1.00 24
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 T. Rajagopal, A. Chakrapani

Fig. 3 Performance comparison 450 10 CMOS

a energy versus load, 400 CMOS
DPL
350 DPL
b normalized energy versus SRCPL
SRCPL
300 Hybrid1
supply voltage, c energy Hybrid1
250

Normalized Energy
consumption for different bit- 5 Hybrid2
Hybrid2
EEHFA

Energy (aJ)
width, d EDP for different bit- 200 EEHFA
width
150
2
100

1
50

0.5
1 2 3 4 5 6 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Load (fF) Supply voltage (V)
(a) (b)
25 CMOS
CMOS
100 DPL
DPL
SRCPL
10 SRCPL Hybrid1
Hybrid1

EDP (10-25 J-s)

Hybrid2
Hybrid2
Energy (fJ)

5 EEHFA
EEHFA

10

1
8 16 32 8 16 32
bit-width (n) bit-width (n)
(c) (d)

compared FAs and can be used in portable electronic
applications.
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