2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)

Analysis of 1- bit full adder using different

techniques in Cadence 45nm Technology
Chandran Venkatesan
Department of Electronics and Thabsera Sulthana M Sumithra M.G
Communication Engineering Department of Electronics and Department of Electronics and
KPR Institute of Engineering and Communication Engineering Communication Engineering
Technology Bannari Amman Institute of technology KPR Institute of Engineering and
Coimbatore, India Sathyamangalam, Erode, India Technology
https://orcid.org/0000-0003-2412-9493 thabse94@gmail.com Coimbatore, India
https://orcid.org/0000-0002-0504-2061
Suriya M
Department of Computer Science
Engineering
KPR Institute of Engineering and
Technology
Coimbatore, India
suriya.m@kpriet.ac.in

Abstract — The full adder is an important component for
controller or processor design like microprocessors, digital
signal processors etc. It is also used to do arithmetic and logical
operations. The objective of this project is to reduce power,
delay and increase the stability factor of a full adder by using
various 1bit full adder designs and techniques. Here 10T full
adder circuits using CMOS technology plots the minimum
power consumption rather than others. Because CMOS
technology dissipates low power. A comparative data analysis
is shown for power, delay and stability using SERF (Static
Energy Recovery Full Adder), GDI(Gate Diffused Input)
method with different number of transistors which is used to
extend the battery life. The adders are designed and
implemented in the virtuoso platform using Cadence 45nm
tool.
Keywords— Full Adder, Cadence Virtuoso, SERF(Static
Energy Recovery Full Adder, GDI(Gate Diffusion Input)
I. INTRODUCTION
In recent applications of VLSI(Very Large Scale
Integration) such as audio and video processing,
microprocessors and digital signal processing etc., using
arithmetic operations. In past times VLSI applications are
mainly depends on area, reliability and cost rather than
power. The power increasing demand was mainly due to
latest growth of electronic products such as portable mobile
phones, laptops and other devices needs high speed and low
power consumption. The major drawback in portable devices
was that takes high power which leads to less battery life and
causes failure in silicon parts of the devices. To control the
heat levels, the device requires high packaging cost and
cooling arrangements with less power consumption. So,
Nowadays in semiconductor industry with low power
devices was critical. Parallely, we need to reduce the critical
path delay of the devices when reducing its power[1].
The power dissipation mainly depends on two types of
devices which was static power dissipation and dynamic
power dissipation. Static power dissipation occurs due to sub
threshold leakage and short circuit transistors current
leakage. This may be eliminated by resizing the CMOS
transistors. Dynamic power dissipation mainly due to
switching activity of the transistors while charging and
discharging [8]. The average power dissipation can be
calculated as
Pavg power = Pdynamic power + Pstatic power (1)
Power dissipation can be eliminated may be architectural
design level, algorithmic level , gate level designs or circuit
level designs. Here we minimized the power at transistor
level. Till now, there are many adder circuits designed using
full adder with different number of transistors [2]. In this
paper, to design existing circuits and modify those designs
with different topologies then shows the comparative
analysis for power, delay and stability. Finally, we conclude
that which is the best design for applications.
The paper is divided as follows. Next section describes
the existing and proposed designs of various full adders.
Section 3 explains the captured designs of those adders.
Section 4 presents the implemented designs using cadence
tool with the suitable results. Section 5 concludes the project
and future work.
II. EXISTING AND PROPOSED ADDER DESIGNS
Here different 1 bit full adder designs are considered for
comparative analysis, namely 28T CMOS Structure, 10T
CMOS design, 10T GDI style design, 10T SERF design and
8T CMOS design [3].
A. Basic Full Adder Design
A basic full adder design has 3 single input bits with the
addition of these bits gives the output as sum and carry. This
is the basic model of the adder design to design different
topologies. The equation for full adder can be derived as,
Sum = A xor B xor Cin (2)
Carry = (A and B) or (B and Cin) or (A and Cin) (3)

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
Fig.1. Block Diagram of Full Adder
B. 28T CMOS 1-bit Full Adder Design
A CMOS design has a combination of pmos and nmos
transistors. The pull up transistors gives strong ‘1’ and pull
down transistors gives weak ‘0’. The average power
dissipation was calculated using CMOS design with different
types. The 28T designs was designed using pull up and pull
down transistors with full swing result and better driving
capacities. The disadvantage of this design is more number
of transistors are used [9]. This leads to high dynamic power
consumption, increasing delay and input capacitances. The
structure was shown in below .
Fig.2. Block Diagram of 28T CMOS 1 bit Full Adder
C. 10T CMOS 1-bit Full Adder Design
Here 1 bit 10T CMOS full adder design was presented.
This is smaller in size compare with 28T design and less
area, power, delay [4]. The structure of the design was used
by XOR and XNOR gates. The design shown in below
figure.
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Fig.3. Block Diagram of 10T CMOS 1 bit Full Adder
D. 10T SERF Full Adder Design
Static Energy Recovering Full adder logic design is used
to implement the design with XOR and XNOR gates and
balancing the delays of output gates [5] & [6]. The power
consumption has been reduced due to this design consists no
direct path for ground. So the control gates reused the charge
stored in a load capacitance. This is an efficient structure to
store energy but it has some disadvantages. The output nodes
has full swings this issue leads to failed in the internal node
power supply. This cascaded power supply may have
threshold problems occurs in multiple places of the design.
The block diagram is shown in below.
Fig.4. Block Diagram of 10T SERF Full Adder
E. 10T GDI 1-bit Full Adder Design
Gate Diffusion Input Full adder design was presented.
Full adder has 3 inputs and 2 outputs. But this design
technique consists of 4 terminals [7]. There are Gate(Input of
CMOS), PMOS(Outer most diffusion node), NMOS(Outer
most diffusion node), Drain(CMOS transistors diffusion
node). This design consists of 3 inputs - Gate input, PMOS
has no connection with VDD (source input) and NMOS has
no connection with VSS (source input). N or P are connected
using bulk amount of both NMOS and PMOS transistors. So
the bias made arbitrarily in contrast to the inverter design
[10]. This is suitable to implement large designs with two
transistors. Compare with SERF design, this technique has
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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
improved low power, swing limited design. The structure Fig.5. Block Diagram of 10T GDI 1 bit Full Adder
was shown in below .
III. SCHEMATIC DESIGN AND SIMULATION RESULTS

A. 28T CMOS Full Adder Design Using Cadence

Fig.6. Schematic of 28T CMOS 1 bit Full Adder

The schematic design of 28T CMOS 1 bit full adder

using cadence 45nm technology is shown in above fig 6. The
length of the transistor is 45nm but the width may varies.
The layout and output is shown in below fig 7 and fig 8.

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)

Fig.7. Output of 28T CMOS 1 bit Full Adder

Fig.9. Schematic of 10T CMOS 1 bit Full Adder

The schematic design of 10T CMOS 1 bit full adder

using cadence 45nm technology is shown in above fig 9. The
length of the transistor is 45nm but the width may varies.
The output is shown in below fig 10.
C. 10T SERF Full Adder Design using Cadence

Fig.8. Layout of 28T CMOS 1 bit Full Adder

B. 10T CMOS Full AdderDesign using Cadence Fig.11. Schematic of 10T SERF 1 bit Full Adder

The schematic design of 10T SERF 1 bit full adder using

cadence 45nm technology is shown in above fig 11. The

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
length of the transistor is 45nm but the width may varies. The layout is shown in below fig 12.

Fig.10. Output of 10T CMOS 1 bit Full Adder

Fig.13. Schematic of 10T GDI 1 bit Full Adder

The schematic design of 10T GDI 1 bit full adder using

cadence 45nm technology is shown in above fig 13. The
length of the transistor is 45nm but the width may varies.
The Layout is shown in below fig 14. The power
consumption has been reduced compared with other
technique full adders.

Fig.12. Layout of 10T SERF 1 bit Full Adder

D. 10T Proposed GDI Full Adder Design using Cadence

Fig.14. Layout of 10T GDI 1 bit Full Adder

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
Comparative analysis of CMOS 28T full adder, 10T CONCLUSION AND FUTURE SCOPE
CMOS full adder, 10T SERF full adder, 10T GDI full adders
A 1bit full adder with various design techniques and
area, power and delay shown in the below Table I and
their area, power delay are calculated using cadence 45nm
Table II.
tool environment with a supply voltage of 1.8V. This project
TABLE I COMPARISON OF 1-BIT FULL ADDER POWER AND finally concludes that 10T GDI technique is best in all
DELAY measurements with low power. The circuit used less number
of transistors so area and leakage power can be reduced. In
future, we can improve the design of 1 bit full adders using
Avg. 8T or 6T and also varies the width of those transistors. We
Technology Delay
Adders power can compare those adders in various nanometer technologies
(nm) (ns) like 90nm, 180nm, 45nm so that can improve the area,
(uW)
power and delay of the designs.
28T
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Fig.15. Comparison of 1 bit full adder Area, Power and Delay

From the above analysis 10T Gate Diffusion Input Full

adder consumes less power and area.

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