See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/234965779

Design A 1Bit Low Power Full Adder Using Cadence Tool

Article · November 2010

DOI: 10.1063/1.3526237

CITATIONS READS
2 15,359

2 authors:

Kavita Khare Krishna dayal Shukla

Maulana Azad National Institute of Technology, Bhopal Indian Institute of Technology Indore
105 PUBLICATIONS 536 CITATIONS 8 PUBLICATIONS 61 CITATIONS

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

IVC and GR approach View project

CORDIC algorithm based QPSK modulator View project

All content following this page was uploaded by Krishna dayal Shukla on 17 January 2014.

The user has requested enhancement of the downloaded file.

 Design A 1Bit Low Power Full Adder Using Cadence Tool
Kavita Khare and Krishna Dayal Shukla

Citation: AIP Conference Proceedings 1324, 373 (2010); doi: 10.1063/1.3526237

View online: http://dx.doi.org/10.1063/1.3526237
View Table of Contents: http://scitation.aip.org/content/aip/proceeding/aipcp/1324?ver=pdfcov
Published by the AIP Publishing

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 14.139.35.2
On: Fri, 17 Jan 2014 12:23:00
 Design A 1Bit Low Power Full Adder Using Cadence Tool
Kavita Khare* , Krishna Dayal Shukla**,
*MANIT/ Electronics & Communication, Bhopal, India
** MANIT/ Electronics & Communication, Bhopal, India
Abstract: This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors in its
structure. The power consumption and general characteristics of an adder are then compared against low power adders, the
transmission function adder (TFA) and the conventional CMOS full adder. The circuits simulated using CADENCE tool 0.18µm
CMOS process technology. The power consumption is decreased by 22% and delay is increased by 347ps.

Keywords: Low-power Full-adder, Low-power CMOS design, transmission function adder.

structure and reduced power consumption in

I. INTRODUCTION comparison to another designs. The reduction in
power consumption due simple structure of circuit
With the continuously increasing chips’ and decreased number of transistors used in the
complexity and number of transistors, circuits’ power circuit.
consumption is growing as well. Technology trends II. FULL ADDER
shows that circuit delay is scaling down by 30%,
A basic cell in digital computing systems is
performance and transistor density are doubled
the 1-bit full adder which has three 1-bit inputs (A, B,
approximately every two years, and the transistor’s and Cin) and two 1-bit outputs (sum and carry). The
threshold voltage is reduced by almost 15% every relations between the inputs and the outputs are
generation. All of these technology trend leads to expressed as:
higher and higher power consumption in circuits.[1]
The battery technology does not advance at the same The above Boolean expressions may be rearranged
as:
rate as the microelectronics technology and there is a
limited amount of power available for the mobile sum = c (a +b +c)+abc (1)
systems. The goal of extending the battery life span
of portable electronics is to reduce the energy carry =ab +c (a +b) (2)

consumed per arithmetic operation, but low power

consumption does not necessarily imply low
energy.[2]

The most conventional one is

complementary CMOS full-adder (C-CMOS) [3]. It is
based on regular CMOS structure with pull-up and
pull-down transistors and has 28 transistors. the
Transmission Function Full-Adder (TFA) is
proposed. It is based on transmission function theory
and transmission gates and has 16 transistors.
Figure 1. XOR Full Adder Circuit
Transmission gates [7,9] consists of a PMOS
transistor and an NMOS transistor that are connected A. Conventional full adder
in parallel. Another Transmission Gate Full-Adder The 1-bit conventional CMOS full adder cell
(TGA) presented in [8] contains 20 transistors. TFA is shown in Fig1. The 1-bit full adder cell has 28
and TGA are inherently low- power consuming and transistors. Different logic styles can be investigated
they are good for designing XOR or XNOR gates from different points of view. Evidently, they tend to
[3,9]. The main disadvantage of these logic styles is favor one performance aspect at the expense of
the lack of driving capability. When TGA or TFA are others. In other words, it is different design
cascaded, their performance degrades significantly. constraints imposed by the application that each logic
In this paper a novel full adder circuit is style has its place in the cell library development.
introduced which designed
CREDIT LINEby (BELOW)
using inverters and ON THE
TO BE INSERTED Even
FIRSTa PAGE
selected style
OF EACH appropriate for a specific
PAPER
transmission gate. This full adder having simple

CP1324, International Conference on Methods and Models in Science and Technology (ICM2ST-10)
This article is copyrighted as indicated in the article. Reuse of AIP content is subject
edited to the
by R. B. Patel and terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 14.139.35.2
B. P. Singh
© 2010 American Institute of Physics 978-0-7354-0879-1/10/$30.00
On: Fri, 17 Jan 2014 12:23:00

373
 function may not be suitable for another one. For
example, static approach presents robustness against
noise effects, so automatically provides a reliable
operation. The issue of ease of design is not always
attained easily. The CMOS design style is not area
efficient for complex gates with large fan-ins. Thus,
care must be taken when a static logic style is
selected to realize a logic function[5].

Figure 3. Transmission gate Full Adder

III. TECHNIQUE FOR LOW

POWER DESIGN
The power consumption in CMOS circuits is
due to dynamic power , short circuit power and static
power.

Ptotal = Pdynamic + Pshortcircuit + Pstatic

= VddFclk∑ Vi swing Ci loadαi +Vdd∑Ii sc +VddIl

Figure2. Conventional CMOS Full Adder

B. Transmission Gate Full Adder

The TG full adder [8], shown in Fig. 3, is
based on transmission gates and introduced for its
low power dissipation [4]. As in the case of the LP
circuit, cascading full adders leads to an overall
propagation delay roughly proportional to , which
becomes excessive for long chains of full adders.
This drawback is solved in the TG drivcap [6]. Output
buffers which interrupt the transmission gate chain
when cascading full adders are added.
Where Fclk is clock frequency ,Vi swing is the
voltage swing at node i, Ci load is load capacitance at
node i αi is the activity factor at node i, and Ii sc and Il
are the short circuit power and leakage current.
The power consumption reduces in CMOS full adder
circuit
1) The static power and dynamic power reduce
by reduction in Vdd.
2) The dynamic power also effected by load
capacitance.
3) The short circuit power is reduced by
reduction in Isc

IV. PROPOSED FULL ADDER

The proposed full adder circuit implement using

NAND , NOR and Majority NOT gates. These gates
are designed by using a simple inverter and MOS
capacitance. To change threshold voltage of PMOS

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 14.139.35.2
On: Fri, 17 Jan 2014 12:23:00

374
 and NMOS of the inverter it work as NAND, NOR
and majority NOT gates.

Figure 5. New Full adder circuit

Figure 4. Three input NAND, NOR MAJORITY NOT function
gate with capacitor

The circuit shown in Fig.4 is works as a universal TABLE 2

circuit. The NAND gate implement NMOS transistor
FULL ADDER TRUTH TABLE
at higher threshold voltage level and PMOS
transistor at low threshold voltage level. For
implement the NOR gate PMOS at high threshold
voltage level and NMOS at low threshold voltage.
For implement the majority NOT function both
transistor are at high threshold voltage level. The
threshold voltage change by changing the MOS size.

TABLE 1.

RESULT OF THE NOT,NOR AND NAND GATES

Design Power Delay PDP

(nW) (ns) (pj)
NAND 29.9 0.533 15.4

NOR 91.4 0.167 15.2

For the six state of the adder both output transistors
MP1 and MN1 are off and the output is same as
Majority 44.9 0.406 17.8
NOT Cout. Another two state when all the inputs are at
logic zero the output of NOR gate is logic one. Then
The full adder circuit design main idea shown in MN1 transistor goes to ON state sum of the adder is
fig(iii) the carry output is compliment of majority connected to the ground and the SUM output is logic
NOT gate. In the table (2) shown the six state of sum zero. When all the three inputs are at logic one. The
output are reverse of carry output. output of NAND transistor is logic zero. Then MP1
transistor ON and sum of the adder is connected to
Vdd and it is logic one.

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 14.139.35.2
On: Fri, 17 Jan 2014 12:23:00

375
 For six state of the sum are same as the Cout. In that
case output transistor MP1 and MN1 are off. To
connect the Cout to SUM PMOS and NMOS
transistors are use as pass transistors shown in fig.6.
Figure 6 New inverter base full adder with pass transistor
Figure.7 Result of proposed full adder
V. SIMULATION RESULT
The proposed circuit evaluated and compared to
conventional full adder , TFA,. The full adder cell
simulate 0.18µm CMOS technology with 50MHz
input signal frequency at 27o C temperature. The
input voltage is 0.8V and supply voltage is 0.8V.
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 14.139.35.2
On: Fri, 17 Jan 2014 12:23:00
376
View publication stats
TABLE 2
SIMULATION RESULT AT 0.8 VDD
Design Power Delay PDP
(µW) (ns) (pj)
CCMOS 0.497 0.759 0.377
TFA 1.03 0.673 0.693
PROPOSED 0.386 1.103 0.425
FA
VI. CONCLUSION
Its simple 12 transistors structure results in a
significant improvement in power consumption, PDP
and performance of a 1-bit full-adder cell. Few
transistor counts, the ability to work at ultra low-
power supply voltages, and finally elimination of
short circuit current are the three major features of
the proposed adder cell. Cadence virtuoso
simulations have been performed to evaluate the full-
adder cell. This observation indicates that the
inverter- based full-adder is a suitable structure for
constructing big low- power and high-performance
VLSI systems.
REFERENCES
[1] M. W. Elgharbawy, M. A. Bayoumi, “Leakge Sources and
Possible Solutions in Nanometer CMOS Technology,” IEEE
circuit and system magazine, pp. 6-16, 2005.
[2] K. Navi, M. Maeen, V. Foroutan, S. Timarchi, O. Kavehi, “A
Novel low-power full-adder cell for low voltage”, Integration, the
VLSI Journal (2009)10.1016/ j.vlsi.2009.02.001.
[3] Y.Jiang,A.Al Sheraidah ,Y. Wang, E. Sha ,J. Chung, “A novel
multiplexer-based low-power full adder”,IEEE Transactionson
Circuitsand Syst ms—II: Express Briefs 51(7)(2004July
[4] R. Zimmermann, W. Fichtner, “Low-power logic styles:
CMOS versus pass- transistor logic”, IEEE Journal of Solid-State
Circuits 32 (7) (1997) 1079–1089.
[5] K. Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi,
N. Dadkhahi, “Low power and high-performance 1 bit CMOS full-
adder cell”, Journal of Computers 3 (2) (2008 February).
[6] M. Rahimi Azghadi, O. Kavehei, K. Navi, “A novel design for
quantum-dot cellular automata cells and full-adders”, Journal of
Applied Sciences 7 (22) (2007) 3460–3468
[7] M.M. Vai, VLSI Design, CRC, Boca Raton, FL, 2001
[8] N. Weste, K. Eshraghian, “Principles of CMOS VLSI Design”:
A System Perspective, Addison-Wesley, Reading, MA, 1993
[9] C.H.Chang, J.Gu,M.Zhang ,”A review of 0.18 mm full-adder
performancesfor tree structure arithmetic ccircuits”, IEEE
Transactionson Very Large Scale Integration (VLSI) Systems
13(6)(2005 June