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An implementation of 1-bit low power full adder based on multiplexer and

pass transistor logic

Article · February 2015

DOI: 10.1109/ICICES.2014.7034071

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 International Conference on Information Communication & Embedded Systems (ICICES 2014)

AN IMPLEMENTATION OF 1- BIT LOW POWER

FULL ADDER BASED ON MULTIPLEXER AND
PASS TRANSISTOR LOGIC
Rajesh Parihar 1, Nidhi Tiwari2, Aditya Mandloi3, Dr.Binod Kumar4
1,2,3
EC Department, Medicaps Group of Institutions, Indore, INDIA
4
MCA Department, JSPM Technical Campus Pune, INDIA
1
parihar.rajesh@gmail.com
2
nidhitiwari.vlsi@gmail.com
3
aditya.mandloi@gmail.com
4
binod.istar.1970@gmail.com

Abstract –A novel implementation of 1 bit full adder based on
multiplexer cell is being proposed. This paper presents the
design of low power full adder based on XOR pass transistor
logic and transmission gate for carry. To reduce the transition
activity and charge recycling capability we have not connected
power supply rail directly instead of that inputs are given
directly and this result in great amount of reduction in power
consumption. Power is decreased to a substantial amount while
transistor count has gone up to 14T rather 12T. Exhaustive
and intensive Tanner SPICE simulation is done and it shows
that there is saving of power supply by the factor of 30% as
compare to 10T and 26% reduction in power as compare to
conventional 28-T CMOS adder[1]-[2].
Keywords- Full adder low power multiplexer Very Large Scale
Integration (VLSI) circuit.
I. INTRODUCTION
set up and result with the help of TANNER EDA tools.
Finally the section V concludes the paper.
1. Switching Power (Pswitch): It is consumed in
charging and discharging of the circuit
capacitances during transistor switching.
2. Short-Circuit Power (Psc): It is consumed due to
short-circuit current from power supply to ground
during transistor.
3. Static Power It is consumed due to static and
leakage currents flowing while the circuit is in a
stable state.
The first two components Pswitch and Psc are dynamic
power because the power is consumed dynamically while
the circuit is changing its states. Dynamic power is majorly
responsible for total power consumption in digital CMOS
VLSI circuits [6], [12].

The increasing demand for the high fidelity portable
devices has laid on the development of low power and high
performance systems. In the next generation processors, the
low power design has to be incorporated into fundamental
computation units like adders and multipliers. [1]- [3],[4]-
[5], [6].
Single bit full adder is one of the most versatile and
critical component of processors, as it is used in the floating
point unit address generation for cache or memory access
[1]. There are many full adders exist and quoted in the
literature [1]-[9]. 34 of them have been found in [3] alone,
which includes well known static complementary CMOS
adders using conventional 28 transistors as shown in fig 1.
The paper is organized as follow. In section II the
literature survey review is presented. In section III the new
approach for implementation of single bit low power full
adder based on multiplexer and pass transistor logic adder is
proposed. In section IV we present simulation environment
The total power is given by the following equation [6]:
PTotal Vdd.Fclk. Vswing.Cload. pi Vdd. isc Vdd.Il
Here the overall power is the summation is over all the
node capacitances of the circuit. With the constant increase
in systems clock frequency, designing systems with low
power consumption is not a straightforward task, as it
involves different system abstraction levels. Beginning from
system behavioral description and ending with fabrication
process and packaging, all the steps can be tailored toward
low power design. In this paper, low power consumption is
targeted at the circuit level. Reducing the number and
magnitude of the circuit capacitances, reducing the voltage
swing at some internal nodes, and reducing the spurious
transitions in the output signal are some of the techniques
used at the circuit level to reduce the power consumption.

ISBN No.978-1-4799-3834-6/14/$31.00©2014 IEEE

 International Conference on Information Communication & Embedded Systems (ICICES 2014)

II. LITERATURE REVIEW

In [1]-[3]is proposed which requires only ten transistor III. A NEW APPROACH FOR FULL ADDERS
to implement full adder as shown in figure 2.SERF BASED ON MULTIPLEXER AND PTL.
consumes less power than TFA[4].In [5]-[6],some new full
adders using 10T have been proposed . These adders either A single bit full adder is built of 14T using 2-T MUX as
use novel approach for adders using EXOR –EX NOR gate shown in Fig 2
[7].
In [4] the novel approach for multiplexer based low
power full adder name MBA-12T that uses 6 identical
multiplexer within all 12 transistors. This novel approach
has low short circuit current and reduce transition activity
than the previously proposed [3] low power adders. The
MBA 12T adder was tested along with the 28 transistor
complementary CMOS adder and four other low power 10
transistor full adders [4],[5] using HSPICE[11].The result
shown in that proposed module consumes 26% less power
as compared to 28 transistor CMOS adder while MBA 10T
consumes 23% less power than the 10 transistors module
and with a minimum of 64% in speed improvement over the
fastest of all other adders.

Fig. 2: Schematic Diagram of Full adder using 14T in

Fig 1 (a) : Conventional 28 Transistors based full adder
Carry logic.
Tanner S-Edit
IV. SIMULATION RESULT WAVEFORMS:
In this we have overcome the transistor count by 14T to
6T and Full adder is the most widely used element in
many of the arithmetic operations. A basic full adder
circuit has three inputs and two outputs and the two
outputs are sum and carry.

Fig.1 (b): Conventional 28 Transistors based full adder

Sum logic

ISBN No.978-1-4799-3834-6/14/$31.00©2014 IEEE

 International Conference on Information Communication & Embedded Systems (ICICES 2014)

C ell0

v( c out )

Average Power 1.677356e-005

3. 0

2. 5
V o lta g e (V )

2. 0

1. 5

1. 0

0. 5

0. 0
dissipation in
watts
0 10 20 30 40 50 60 70 80 90 10 0

Ti m e (ns )

3. 0
Max power 7.328616e-004
C ell0

at v( s um )

2. 5

time 6.07722e-008
V o lta g e (V )

2. 0

1. 5

Min power 6.755391e-010 at

1. 0

0. 5

0. 0

time 6e-008
0 10 20 30 40 50 60 70 80 90 10 0

Ti m e (ns )

C ell0

3. 0

2. 5
No. of Transistors 14 v( c in)

The main advantages of the proposed 14 transistor

V o lta g e (V )

2. 0

1. 5

1. 0

0. 5
full adder circuit is its small size so that large number of
0. 0
0 10 20 30 40

Ti m e (ns )
50 60 70 80 90 10 0

devices can be placed on a single silicon chip results in less

C ell0

v( b )
area, it has less power dissipation compared to the
previously designed design of high speed and low power six
3. 0

2. 5
V o lta g e (V )

2. 0

transistor full adder using two transistor xor gate .full adder
1. 5

1. 0

0. 5

0. 0

circuits and the speed of operation is also high. the proposed

0 10 20 30 40 50 60 70 80 90 10 0

Ti m e (ns )

3. 0
C ell0

v( a )
full adder also reduces the two stage delay associated with
2. 5

the sum and carry elements of eight transistor full adder

V o lta g e (V )

2. 0

1. 5

1. 0

0. 5

0. 0
circuit. in order to establish the technology independence of
the, the adder has been designed using 0.13μm and 0.25μm
0 10 20 30 40 50 60 70 80 90 10 0

Ti m e (ns )

Fig. 3: Simulation Results of 14T Full Adder cell on technologies. The power-delay simulation of the adder has
different power supply been carried out. Simulation results indicate that the
designed full adder has much less power-delay product Due
to these advantages the proposed full adder can be used in
many advanced applications where less power is the main
requirement.

CONCLUSIONS
The current work proposes the design of 14 transistor full
adder, which has transistor count more than the previous
existing design but power consumption of our novel
proposed full adder has been reduced the full adder with
tradeoff between transistor count of two. In designing the
proposed 14 transistor full adder, a 2 transistor based on
multiplexer and Pass transistor logic has been proposed.
The proposed logic of our novel design is summarizes in
the table 1. The power dissipation in watts are as Average
Power dissipation in watts 16.67uwatts. Maximum Power
732uwatts. Minimum Power Delay 675.53 pwats . The main
aim of this paper is to design a high performance and low
power full adder cell with less power dissipation and
acquires least area. Simulation results shows that this
Fig.4: Rise and Fall time delay proposed full adder achieves better power reduction when
compared with other commonly used full adders. Because of
Further full adder is the basic element in many of the low the less power dissipation and less transistor count the
power VLSI devices where low power and less area is the proposed logic can be useful in portable and low power
primary requirement. To reduce the area of the overall chip applications. Due to less number of iterations the
the elements inside the chip are to be designed as small as complexity of the design is also low and it require less
possible. The size of the individual elements inside the chips memory.
can be minimized by modifying their basic logical
representation in a meaning full manner so that the desired
logic can be obtained with less size. REFERENCES
[1] R.Shalem, E. John and L.K.John, “A novel low power energy
recovery full adder cell,” in Proc. Great Lakes Symp. VLSI,
Table. I: Power results of 14T Full Adder cell Feb. 1999, pp. 380-383.
[2] H.T. Bui, A.K. Sheraidah, and Y.Wang, “Design and analysis of
10-transistor full adders using novel XOR-XNOR gate” in Proc.

ISBN No.978-1-4799-3834-6/14/$31.00©2014 IEEE

 International Conference on Information Communication & Embedded Systems (ICICES 2014)

Int. Conf. Signal Processing 2000 (World Computer Congress),

Beijing, China Aug. 2000.
[3] Y.Jiang, Y. Wang, and J.Wu, “Comprehensive Power
Evaluation of Full Adders,” Florida Atlantice Univ., Boca
Raton, Tech. Rep., 2000.
[4] Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin
Sha and Jin-Gyun Chung, “A Novel Multiplexer- Based Low
Power Full Adder,” IEEE Trans on Ckts. & Systems-II:
Express Briefs, Vol. 51, No. 7, July 2004, 345-348.
[5] Ahmed .M. Shams, M.A. Bayoumi, “A Novel High-
Performance CMOS 1-Bit Full-Adder Cell”, IEEE Trans.
Circuits Syst. II: Analog Digital Signal Processing. 47 (2000)
478–481.
[6] A.P. Chandrakasan, S.Sheng and R.W. Broderson, “Low Power
CMOS Digital Design,” IEEE J. Solid State circuits, vol. 27, pp.
473-483, Apr. 1992.
[7] R.Pedram and M.Pedram, “Low power Design Methodologies”
Norwell, MA: Kluwer, 1996.
[8] J.-M. Wang, S.-C. Fang, and W.-S. Feng, “New efficient
designs for XOR and XNOR functions on the transistor level,”
IEEE J. Solid-State Circuits, vol. 29, pp. 780–786, July 1994.
[9] N.Weste and K. Eshraghian, Principles of CMOS VLSI Design,
a System Perspective. Reading, MA: Addison-Wesley, 1993
[10] R. Zimmermann and W. Fichtner, “Low-power logic styles:
CMOS versus pass-transistor logic,” IEEE J. Solid-State
Circuits, vol. 32, pp. 1079–1090, July 1997.
[11] Meta Software: HSPICE User Manual Version H9002,1992
[12] S.Devadas and S.Malik, “A survey of optimization techniques
targeting low power VLSI Circuits”, in Proc.32nd ACM/IEEE
Design Automation Conf., 1995, pp. 242-247.
[13] G.M Blair, “ Designing low power CMOS,” IEEE Electron.
Commun. Eng. J., vol 6, pp 229-236, Oct. 1994.

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