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Performance analysis of 1 bit full adder using GDI logic

Article · February 2015

DOI: 10.1109/ICICES.2014.7034029

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 International Conference on Information Communication & Embedded Systems (ICICES 2014)
Performance Analysis of 1 bit Full Adder Using
GDI Logic
Shoba Mohan
Department of Electronics engineering
School of Engineering and Technology
Pondicherry University,Puducherry
shobamalar@gmail.com
Abstract—This paper focuses on the design of 1 bit full
addercircuit using Gate Diffusion Input Logic.The proposed
adder schematics are developed using DSCH2 CAD tool, and
their layouts are generated with Microwind 3 VLSI CAD tool. A
1 bitadder circuits are analyzed using standard CMOS 120nm
features with corresponding voltage of 1.2V.The Simulated
results of the proposed adder iscompared with those of Pass
transistor,Transmission Function, and CMOS based adder
circuits. The proposed adder dissipates low power and responds
faster.
Keywords; low power,adder,full swing.
I. INTRODUCTION
The tremendous proliferation in battery powered devices like
mobile, laptop put a tight requirement on low power
consumption to achieve consistent heat dissipation over period
of operating cycle .The evolution in integrated circuit
increases the number of transistor in a chip thereby complexity
increased in multi fold. As per the moore’s Law the number of
transistor in a year is getting doubled for every eighteen
month[8]. To validate this statement the size of the transistor
is getting shrink down as the technology advances. While
increasing the transistor count and decrease in the size directly
impacts on the increase in power consumption. The main
contributors of power dissipation are static, dynamic and
leakage power consumption[9]. Static is due to direct path
exists when the supply rails are shortened the input transition
is a key factor for charging and discharging the node
capacitance which produces dynamic power consumption it is
given by where is activity factor is
load capacitance is supply voltage is the operating
frequency[10]. While scaling the feature size of MOSFET
supply voltage also scaled down which in turn reduces the
threshold voltage of the transistor [13]. The reduction in
threshold voltage causes increase in standby current. So the
efficient power control mechanism is needed for minimizing
static power dissipation [11]. Adder is a basic building block
of an arithmetic circuit. It is not only used for addition and
also used for subtraction, multiplication and division [5]. It is
used in microprocessor and implementation of address
generation circuits. So the optimization in design of adder
yields better performance of system as a whole. The
Nakkeeran Rangaswamy
Department of Electronics Engineering
School of Engineering and Technology
Pondicherry University,Puducherry
nakkeeranpu@gmail.com
optimization can be carried out in two stage system level and
circuit level. In the system level the optimization can be
carried out by input pattern such way to minimize the number
of transition, architectural realization, gate level optimization,
minimizing the critical path i.e. longest path takes reaching the
output from an input [7]. These approaches lead to minimize
the number of transition, transistor count and increase the
speed respectively. In the circuit level, the implementation
logic style decides the power consumption, speed of the
circuit, minimum number of transistor, full swing output, good
driving capability for different load conditions and regular
layout [14].
The paper is organized as follows. In section 2 different full
adder topologies are discussed. In section 3 full adder designs
using GDI logic is presented, section 4 shows simulation
results of the adder and the work is concluded in section 5.
II. DIFFERENT FULL ADDER TOPOLOGIES
The standard implementation of full adder (FA) uses
Complementary Metal Oxide Semiconductor Logic [3].It uses
28 transistors and consists of both pull up and pull down
transistor. This logic needs an inverter at the output to produce
normal output from the intermediate complementary signal.
The input capacitance is large due to increase in transistor
count.The lesser number of transistor realization is possible
using pass transistor logicis explained [9].This logic has a
drawback of threshold voltage problem which can be
mitigated using restoring circuit or keeper transistor[9].The
additional circuit posses increase in transistor and the presence
of inverter in restoration circuit increases the power
consumption considerably[14].The problem is alleviated using
variant of pass transistor logic are complementary PTL called
CPL, but the minimum requirement is generation of
complementary signal which increase circuit
overhead[12].The full adder is designed using transmission
gate[7] which consists of PMOS and NMOS connected in
parallel controlled by the gate inputs.It is suitable for
designing XOR/XNOR gates with less number of transistor
and suffered by lack of driving capability and when connected
in series its performance degrading[15].
ISBN No.978-1-4799-3834-6/14/$31.00©2014 IEEE
 International Conference on Information Communication & Embedded Systems (ICICES 2014)

III. IMPLEMNTATION OF FULL ADDER USINGGDI
LOGIC
GDI logic[2] is a technique which offers the implementation
of all the function using basic GDI cell. The basic GDI cell is
shown in fig it uses only two transistors and having three
inputs namely G(Common Gate input of both PMOS and
NMOS),N(input to source/drain of NMOS),P(input to the
source of source/drain of PMOS) bodies of both PMOS and
NMOS are tied to P or N respectively. The basic GDI cell is
shown in fig.1.GDI method is suitable for implementation
various logic function such as adder, multiplier, flip-flop and
counter. The various function implemented using GDI cell is
listed out in Table I. The implementation results shows
reduction in power. The GDI cell is suitable for fabrication
techniques of SOI or twin well process. This issue is mitigated
by the technique modified GDI(MGDI) proposed in [1] yet the
basic cell is suffered by lagging in full swing output. This
problem is addressed in [4]-[6] and the various techniques are
proposed for mitigating the problem still it opens window for
better implementation to achieve low power, lesser delay and
minimal number of transistor.
generation of SUM and carry are independent which shows
better in response rather than intermediate results as given
in[5].The simple logic for getting full swing is the use of two
inverters at the output [6]. This technique leads to static power
consumption and increases the power consumption which
offsets the main advantages of GDI logic. An another
technique [5]uses diodes for surmounting swing problems but
its lagged by leakage current and difficult to maintain the
characteristics diode while making transistor as a diode and
leads to integration issues. In F1 and F2 function the
achievement of full swing operation is explained in[4] but the
realization of full adder using above function increases the
number of transistor count and it leads to lessen the use of
GDI logic. The full swing operation is possible by the use of
one transistor at the output. For AND operation when A=B≠1
the output is lagged by threshold voltage drop V th this is
overcome by the use of one NMOS transistor at the output
similarly for OR operation lagging in output voltage of logic 1
is overcome by the use of PMOS transistor at the output. So
this technique is suitable for minimal area and power
consumption. The use of PMOS transistor in load may have
negative impact on response of the circuits. The proposed full
adder is given in fig.2

Fig.1.Basic GDI cell

TABLE I
The logic functions of GDI cell
N P G OUT FUNCTION
0 B A B F1
B 1 A +B F2
1 B A A+B OR
B O A AB AND
C B A B+AC MUX Fig.2.Proposed Full Adder
0 1 A NOT
IV. SIMULATION RESULTS
A full adder has three inputs and produces two outputs namely The proposed full adder is simulated using DSCH3 and the
sum and carry. The logic expression for sum and carry is corresponding layouts are generated using microwind tool and
described as their characteristics such as delay, power consumption and
area are analyzed. The Simulated input and output voltages for
full adder circuit are shown in fig.3. The aspect ratio of the
PMOS and NMOS transistor are chosen as 2.0µm/0.12µm and
The basic equation of carry can be modified i.e. when cin=0
1.0 µm/0.12µm respectively for all the circuit
carry is AND of input operands A and B otherwise carry is
OR operation of input operands A and B respectively [5]. This simulations.From these simulation results,the power
technique utilizesoperation of MUX,OR and AND gates. The consumption of PTL adder is high due many intermediate

ISBN No.978-1-4799-3834-6/14/$31.00©2014 IEEE

 International Conference on Information Communication & Embedded Systems (ICICES 2014)

nodes and frequent switching activity and the worst case delay
is reported in MGDI is due to use of inverters at the output for
providing full swing delays the response of circuits. The
Proposed full adder is slightly increased in transistor count but
it is capable of providing lesser delay and power consumption
compared to other adders are reported in literature.

Fig.3..Input and Output Waveform of proposed Full Adder

V. CONCLUSION
The full adder is designed using proposed technique.It
outperforms the adder based on CMOS,PTL and
transmission.The proposed adder achieves better performance
in terms of delay,power consumption with slight increase in
transistor count compared to other published works.The circuit
can be used as a building block for Arithmetic Logic
Unit(ALU),and Digital Signal Processing related applications
due to its lower delay and decreased power consumption.
TABLE II
SIMULATED RESULTS OF DIFFERENT FULL ADDER
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ISBN No.978-1-4799-3834-6/14/$31.00©2014 IEEE

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