Project review 1

On

DESIGN OF LOW POWER,HIGH SPEED ADDER

USING CADENCE TOOL

A Project Seminar Report submitted by (BE 4/4 ECE-2 Students)

Date of Seminar: Aug 28 , 2019th

Batch No: 212

Bh
ABHILASH KURLEPU - 160116735086
KRISHNA ABHISHITH
PURIHELLA - 160116735097

YATINDRA ROHIT CHODISETTI - 160116735119

Under the esteemed guidance of

SRI . CHANDRASEKHAR P
Assistant Professor,

Submitted to
Dept of ECE, CBIT

Department of Electronics and Communication Engineering

Chaitanya Bharathi Institute of Technology (Autonomous)
Hyderabad- 500 075

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 CERTIFICATE

This to certify that the project seminar report titled “DESIGN OF LOW
POWER,HIGH SPEED ADDER USING CADENCE TOOL” is submitted by
ABHILASH KURLEPU(160116735086), KRISHNA ABHISHITH.P(160116735098)
& YATINDRA ROHIT.CH(1601167350119), the students of department of
ECE,CBIT in partial fulfilment of the requirements for awarding degree in Bachelor of
Engineering (B.E.). This report has not been submitted in this institution or any other
institution/ universities for the fulfilment of requirement in any course or study.

Internal Guide: Project Co-Coordinator: Project Co-Coordinator:

Sri. Chandrasekhar.P Sri. Mohd Ziauddin Jahangir Smt.M.V.Sireesha
Dept of ECE, CBIT Dept of ECE, CBIT Dept of ECE, CBIT

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 ABSTRACT

VLSI technology is an emerging field in the current technological scenario due to its
advancements in fields of systems architecture, analog and digital logic and adders are
the basic building blocks in digital integrated circuit based designs. The existing Ripple
Carry Adder (RCA) has the most compact design but takes longer computation time. The
time critical applications use Carry Look-ahead Adder (CLA) but they lead to increase in
area. Parallel prefix adders are a tree structure based and are preferred to speed up the
binary additions. Brent Kung (BK) adder is a parallel prefix adder which gives improved
performance in terms of speed.
In this paper we presented a new 32T full adder design based on hybrid – CMOS logic
design style. The new design is compared with some existing designs for power
consumption, delay at various frequencies such as 10 MHz, 200 MHz and 1 GHz. The
simulations are carried out on Cadence Virtuoso at 65nm CMOS technology and the
simulation results are analyzed to verify the superiority of the proposed design over the
existing designs. The design of adders are done with CMOS and MTCMOS technologies
and are compared. We can observe some significant results improved by using
MTCMOS technology on power consumption and delay. The necessity for low-power
design is also important in high performance digital systems.

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 CONTENTS:
Abstract
Contents
CHAPTER 1 : INTRODUCTION
1.1 AIM OF THE PROJECT
1.2 MOTIVATION OF THESIS
1.3 OBJECTIVES OF THE PROJECT
1.4 COMPONENTS
1.5 ORGANIZATION OF THESIS
CHAPTER 2 : LITERATURE SURVEY
CHAPTER 3 : THEORETICAL BACKGROUND
3.1 ADDERS ARCHITECTURE
3.2 HALF ADDER AND FULL ADDER
3.3 RIPPLE CARRY ADDER
3.4 CARRY SELECT ADDER
3.5 CARRY LOOK AHEAD ADDER
3.6 BRENT KUNG ADDER
CHAPTER 4 : METHODOLOGY
CHAPTER 5 : RESULTS AND DISCUSSIONS
CHAPTER 6: CONCLUSION AND FUTURE WORK
CHAPTER 7 : REFERENCES
Page 4
 CHAPTER 1
INTRODUCTION

Area and power reduction in data path logic systems are the main area of
research in VLSI system design. High speed addition and multiplication has
always been a fundamental requirement of high-performance processors and
systems.
1.1 AIM OF THE PROJECT :
 To design and implement adders.
 Compare their efficiencies.

1.2 MOTIVATION OF THESIS :

Addition is the most common and often used arithmetic operation on

microprocessor, digital signal processor, especially digital computers. Also,
it serves as a building block for synthesis all other arithmetic operations.
Therefore, regarding the efficient implementation of an arithmetic unit, the
binary adder structures become a very critical hardware unit.
In digital adders, the speed of addition is limited by the time required
to propagate a carry through the adder. The sum for each bit position in an
elementary adder is generated sequentially only after the previous bit position
has been summed and a carry propagated into the next position.

The major speed limitation in any adder is in the production of carries and
many authors have considered the addition problem. The carry select adder
is used in many computational systems to moderate the problem of carry
propagation delay by independently generating multiple carries and then
select a carry to generate the sum.

1.3 OBJECTIVES:
 Design of logic gates
 Design of various adders using CMOS and MTCMOS
technology.
 Extension of 16-bit brent kung adder to 32-bit brent kung adder.
 To find the best adder and to replace the poor adders to avoid delay
and make better utilization of the power.
 1.4 COMPONENTS :

CADENCE SOFTWARE is the type of software used in

thisproject.With the help of this software we will design design different
types of adders using the technologies present in the software.This software
is also used not only for getting the characterstics of devices but also in
designing the layouts for the chips designed.This is the reason for choosing
this software.

1.5 ORGANIZATION OF THESIS:

This thesis report contains four chapters.

The second chapter encloses the literature surveys.

The third Chapter enclose the type of adders and discuss the working of various adders like

Full adder,Ripple carry adder,carry select, carry lookahead,brent kung adders.

In fourth chapter methodologies are discussed .

 Design of gates and adders using both CMOS and MTCMOS technologies.

 Extension of 16-bit adder to 32-bit Brentkung adder.

 Advantages, Conclusion,References.

CHAPTER 2

2.1 LITERATURE SURVEY:

Brent, Richard Pierce,Kung,HsiangTe had designed the Brent-Kung

adder and published this journal. This brings the first journal regarding

Brent-Kung adder.

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 CHAPTER 3

THEORETICAL BACKGROUND

3.1 ADDERS ARCHITECTURE:

In electronics, an adder or summer is a digital circuit that performs

addition of numbers. In many computers and other kinds of processors,
adders are used not only in the arithmetic logic units, but also in other parts of
the processor, where they are used to calculate addresses, table indices, and
similar operations.

Although adders can be constructed for many numerical representations, such

as binary- coded decimalor excess-3, the most common adders operate on
binary numbers. In cases where two’s complement or ones complement is
being used to represent negative number.

3.2 HALF ADDER:

Schematic diagram of Halfadder

The half adder is an example of a simple, functional digital circuit built from
two logic gates. The half adder adds to one-bit binary numbers (AB). The
output is the sum of the two bits (S) and the carry (C). Note how the same two
inputs are directed to two different gates.

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Truth table of half adder:

FULL ADDER:

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit
full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the
operands, and Cin is a bit carried in from the previous less significant stage.[2]The full adder
is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers.
The circuit produces a two-bit output, output carry and sum .

Where as the equation of the sum and carry is

S= AXORB; -------------------------------------------------------------------( 1)

Cout= A AND B; -------------------------------------------------------------(2)

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 Schematic diagram of Full adder.

Truth table Of Full Adder

3.3 RIPPLE CARRY ADDER:

Arithmetic operation like addition ,subtraction ,multiplication ,division are

basic operation to be implemented digital computer using basic gates among all
arithmetic operation if we can implemented addition then it is easy to perform
multiplication repeated addition .Half adders can be used to add two one bit
binary numbers .it is also possible to create a logical circuit using multiple
adder to add N bit binary number .each full adder inputs carry ,which is the
output carry of the previous adder .this kind of adder is a ripple carry adder
,since each carry bits “ripples” to the next full adder .the first full adder may be
replaced by the half adder.

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 Ripple carry adder

3.4 CARRY SELECT ADDER:

A Carry Select Adder is a particular way to implement an adder, which is a

logic element that computes the (n+1) bit sum of two n-bit numbers .The
carry-select adder is simple but rather fast. The carry-select adder generally
consists of two ripple carry adders and a multiplexer. Adding two n-bit
numbers with a carry-select adder is done with two adders (therefore two
ripple carry adders) in order to perform the calculation twice, one time with the
assumption of the carry being zero and the other assuming one. After the two
results are calculated, the correct sum, as well as the correct carry, is then
selected with the multiplexer once the correct carry is known.

Carry select adder

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3.5 CARRY LOOKAHEAD ADDER:

CLA is a type of adder using in digital logic. A carry look ahead adder
improves speed by reducing amount of time required to determine carry bits. it
can contrasted with the simpler but usually slower, ripple carry adder for
which the carry bit is calculated alongside the sum bit and each bit must wait
until the previous carry has been calculated to begin calculating its own result
and carry bits .The carry look ahead adder calculates one or more carry bits
before the sum, which reduces the wait and time .To calculate the result of a
larger value bit. The Kogge-stone adder and Brent-Kung adder are the
example of this type of adder.

Carry lookahead adder

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3.6 BRENTKUNG ADDER (16-Bit):

The Brent Kung adder computes the prefixes for 2 bit groups. These prefixes are used to
find the prefixes for the 4 bit groups, which in turn are used to compute the prefixes for 8 bit
groups and so on. These prefixes are then used to compute the carry out of the particular bit
stage. These carries will be used along with the Group Propagate of the next stage to
compute the Sum bit of that stage. Brent Kung Tree will be using 2log2N - 1 stages. Since
we are designing a 32-bit adder the number of stages will be 9. The fanout for each bit stage
is limited to 2. The diagram below shows the fanout being minimized and the loading on the
further stages being reduced. But while actually implemented the buffers are generally
omitted.

16-bit Brentkung adder

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 CHAPTER 4

4.1 METHADOLOGY:
1. Design of NAND and NOR gates using CMOS transistors.

2. Design of Full Adder and implementation using CMOS and

MTCMOS technologies.

3. Design of Ripple carry adder,Carry select adder, Carry lookahead

adder,Brentkung adder.

MTCMOS TECHNOLOGY:

Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology which

has transistorswith multiple threshold voltages(Vth) in order to optimize delay or
power. The Vth of a MOSFETis the gate voltage where an inversion layerforms at the
interface between the insulating layer (oxide) and the substrate (body) of the
transistor. Low Vth devices switch faster, and are therefore useful on critical delay
paths to minimize clock periods. The penalty is that low Vth devices have substantially
higher static leakage power. High Vth devices are used on non-critical paths to reduce
static leakage power without incurring a delay penalty. Typical high Vth devices
reduce static leakage by 10 times compared with low Vth devices.

MTCMOS schematic

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32- bit EXTENSION FROM 16-bit BRENTKUNG ADDER:

The diagram of a 16-bit Brent Kung Adder is shown above. 16-bit adder will contain
7 stages of operation. 32-bit will contain 9 stages of operation as per the equation
2log2N - 1. Now we will add a Gray Cell of 16 bit prefix at 31st bit to the 5 th and 8
bit prefix at 23rd bit to the 6 th stage. A Black cell of 8 bit prefix will be added to the
5th stage at the 31st bit.

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 CHAPTER 5:

RESULTS AND DISCUSSION:

NAND:

NOR:

EXOR:
 CHAPTER 6:

CONCLUSION:
1. The main objective of this adder is to make it time saving and more efficient than existing
adders.
2.By comparing the power consumption values and time delay with respect to other adders it
is more efficient and user friendly.
PLAN OF ACTION:
• Design of logic gates 03-02-2020

• Design of various adders using CMOS and MTCMOS technology 03-03-2020

• Extension of 16-bit brent kung adder to 32-bit brent kung adder. 15-03-2020

• To find the best adder and to replace the poor adders to avoid delay 25-03-2020

and make better utilization of the power.

4.4 REFERENCES:

1. https://search.ieice.org/bin/summary.php

2. Brent, Richard Pierce,Kung,HsiangTe had designed the Brent-Kung adder

and published this journal. This brings the first journal regarding Brent-Kung
adder.

3. Design of MTCMOS LOGIC CIRCUITS FOR LOW POWER ADDERS by

Dr.M.MadhaviLatha and V.Leelarani .

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