Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)
IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8
Design and Performance Analysis of 32 Bit
VLSI Hybrid adder
Vishwa Shah Urvisha Fatak
Electronics & Communication Dept. Electronics & Communication Dept.
Vishwakarma Government Vishwakarma Government
Engineering College Engineering College
Gujarat, India. Gujarat, India.
Email: shahvishwa10@gmail.com Email urvishafatak@gmail.com
Abstract: The Adder circuit is basically required in many application
of DSP digital signal processing architecture, Microprocessor,
Microcontroller, Filter designing and data Processing units. A system
if contains a hybrid adder than it is sure that the system must have low
power consumption, high speed (Less delay) and occupies less area
space in memory unit. From many years researchers are trying to make
devices small in size with high operating speed and Low power
consuming so they are trying various techniques In this paper different
32 bit adders are studied and design implementation is done and Some
32 bit hybrid adder are proposed by using various adder combinations,
Performance analysis in terms of area (according to the number of
LUTs) and delay (in ns) is performed in Xilinx ISE 14.7 using Verilog
code.
Keywords-Adders, Hybrid adder, Xilinx, Kogge stone adder (KSA),
Carry lookahead adder (CLA), Carry Save Adder (CSA)
I. INTRODUCTION
The addition operation is a binary operation. It is a basic and
fundamental operation in any calculative system which is
responsible for addition, substraction, division, multiplication,
finding complement, encoding and decoding In between 1868-
1869 Charles Webb created several patents for calculating
Device for adding Machine Long back many Adder topologies
are introduced which are designed and implemented [1], [2], [3].
Most of the digital systems like laptop, computers, notepads and
mobiles may have low performance which make user in trouble
and thinks to format or upgrade the system but this is not better
solution. So, a system is needed with best performance. A
computer having processors contains a 32 Bit processor
architecture contains 32 bit integers, 32 bit registers and 32 bit
memory addresses, multiplier, substractor, adder, Registers,
cache etc. In this research work we are focusing on Adder circuit.
In Very large scale integrated circuits the major problems found
are more power consuming, slow working and taking large space
in memory units it was generally observed that a system is
required having low power consuming, High speed and less area.
In this recent digital world it is becoming essential to sustain
resources and save time so many research is going on for better
performing system units. The design engineers are trying to
design a system which can perform its best by giving high
performance Parameters. The parameters are observed by trial
and fault analysis the designs are tested and fabricated. In this
research work we are focusing on adder circuit. If the delay is
reduce than the speed can be increased. To have a best system it
is essential to focus on all the parameters such as less area, low
power, less time consuming, occupying less frequency and high
speed .All this good performing system can be obtained if a
hybrid adder structure is inserted in arithmetic unit. In this paper
978-1-5386-9439-8/19/$31.00 ©2019 IEEE
Jagruti Makwana
Electronics & Communication Dept.
Vishwakarma Government
Engineering College
Gujarat, India
Email jagruti_ec@yahoo.com
Different adders are studied in brief then 32 bit different adders are
implemented in Xilinx ISE 14.7 using Verilog code and Analysis of
performance of different adders is done in terms of area (by number
of look up tables LUT) and delay(in Nano second). We have proposed
a 32 bit various hybrid adders which are fast adder as compared to
others. This research paper is organized in the following way Section
I is describing the introduction of the research work, Section II gives
short summary about literature review, Section III Revising about
different Adders, Section IV Tells about hybrid adder,Section V
shows simulation results and Section VI ending with Conclusion of
the research work.
II. LITERATURE REVIEW
Different electronic device has problems regarding power
Consumption, area for memory and delay for data operation so from many
years research is ongoing by using different techniques and checking its
performance. Adders were designed by transistor gate logic and pass
transistor logic style in 0.25 micrometer CMOS technology and its
performance analysis was observed [4].Adders were designed by Gate
diffusion technology & Pass transistor logic in 180nm technology [8],
[10].A method of domino logic based on PMOS Pull up network was used
[11].BCD adder was designed by two approaches –pipelining and
parallelism[12].A technique called as quantum dot cellular automata 1 bit
adder was designed by reversible logic [13],[14].Energy minimization in
ripple carry adder by tracking loop method was implemented which
measures energy consumed through a DC-DC converter[9].Redundant
binary signed adder was designed and performance analysis was done [6].A
novel approximate adder structure was designed and implemented based on
LUT [7].A idea comes to picture of proposing a new adder structure by
using different adder topologies called as heterogeneous structure or hybrid
structure[16]so researchers started designing and implementing various
adders and observing & comparing its area, power ,delay and gate
counts[1],[2],[3],[5],[15] by analysis describing its advantages and
limitations a new hybrid adder architecture was proposed.
III.ADDERS
Adder is an electronic circuit which adds binary numbers as an output sum
and carry is generated.According to carry generated name is given of
different adders. Let us we recall the different adders which are introduce
so far.
A. Carry Save Adder(CSA)
In carry save adder three bits are added parallel at a time the carry is not
propagated through the next stages. The carry is stored in present stage and
updated in next stage. In this adder delay can reduce due to carry
generation it is also called as multioperand adder. A Carry save adder
contain full adder according to its bits which gives single sum and carry
Fig 1 shows block diagram of Carry save adder which shows sum is
generated and carry pass it’s Update to next stage.
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 Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)
IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8

D. Carry Increment adder(CIA)

The carry increment adder consists carry ripple adder and

incremental circuit. The circuit is designed in sequential order by using
half adder in ripple carry chain. Fig 3 shows the block diagram of carry
increment adder

Fig 1 Block diagram of carry save adder

Advantages
 Carry is stored at present stage
 We can add three input values at a time
 The delay calculation is 0 log n where n is number of
bits
Disadvantages
 It occupy large area because transistor number is high Fig 3 Block diagram of carry increment adder
 For lower operating bit it has high delay and power E. Carry Lookahead Adder (CLA)
consumption.
 Result of addition occurs once
The basic principle of this adder is looking at lower adder bits of
 We still do not know result of the carry is longer or
argument and addend if higher orders carry generated. As number of
smaller than a given number (whether it is positive or
gate is reduce the delay can be reduced during this adder two stages
negative) take place propagation stage and generation stage the values are
B. Carry Select Adder(CSelA) occurred in both stage in second stage carry generated is calculated and
Carry select adder sum and carry are generated independently. in final stage sum value is calculated. It is used in hierarchical structure
Depending upon carry the external multiplexers select the carry to be
propagated to next stage then on the basis of the carry input the sum
will be selected hence delay gets reduce .It contains multiplexer and
two ripple carry adder which assume carry as 1 and carry as 0 after
the overall calculation sum and carry is generated . Fig2 shows the
block diagram of carry select adder.

Fig 4 Working flow of CLA

The Fig 4 is showing working flow of CLA
The propagation stage is also called generation stage

G(i)= a[i].b[i]…………………………… (1)

P (i) = a[i] ^ b[i]………………………… (2)
Equations (1) and (2) are formulas of generation part and
Propagating part.
The internal carry is generated by formula (3)
C (i)=G(i)+ P(i).C(i-1)……….................. (3)
The sum generation is calculated by formula (4)
Fig2 Block diagram of carry select adder Sum[i] = a[i] ^ b [i] ^ c [i-1]………………….. (4)
Here i=1, 2, 3……
C. Carry Skip adder(CSKA) Advantages
Carry skip adder uses the principle of skip logic in carry propagation.
 It is fastest adder
It is used to speed addition operation by adding a propagation of
 It reduce propagating delay
carry bit around entire adder. It consists two logical gates AND gate
is used for carry -in bit which compares with propagated signals  It has less number of gates
Advantages Disadvantages
 In higher bit operation it gives better response  It has complex carry logic blocks
 It has fast adder because of skip logic
Disadvantages F. Carry Ripple adder (CRA or RCA)
 The adder is more power consuming Because of Carry ripple adder perform addition operation. It contains series
using many skip logical circuit structure of full adder each full adder cell add two bit along the carry
bit .The carry generated from each full adder is given to next full adder
 In lowest bit operation the parameters are high
and so on.
which can effect entire processor

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 Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)
IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8

III. HYBRID ADDER

When an adder is constructed by implementing one or more logic is called

as hybrid adder
Fig 6 is the block diagram of hybrid adder A and B are the inputs in module
1, module2 and module 3 we can put same or different type of adder which
is giving sum and carry as output using different adder or same adder can
form multiple logic values the both the logical values are having some
advantages which shows that it can perform better.
Fig5 Block Diagram of ripple carry adder

Advantages
 More number of bits can easily added

Disadvantages
 Carry has rippling effect
 Delay is more
G. Kogge stone adder(KSA)
Kogge stone adder was introduce by kogge stone in 1973.It works
on three stage operation-preprocessing, carry generation and post
processing. Carry is generated by calculating the expanded area.
Delay can calculate by formula-
Fig 6 Block diagram of hybrid adder
2 log n …………………….. (5)
n – Number of input bits
There is two types of architecture of forming hybrid adder
Advantages
 It has low fan out
 It has lowest delay
1 Homogeneous
 It has fast operation
Disadvantage The merger of same type of two or more adders forms
 The functioning is very complex Homogeneous architecture.
Let us describe the three stages
2 Heterogeneous
Preprocessing stage
Propagation and generation blocks are calculated by formula (6) The merger of different type of two or more adder forms
and (7) Heterogeneous Architecture.
P[i] = A[i]XORB[i]………………………. (6)
G[i] = A[i]ANDB[i]………….................... (7) The idea of combing designs to form hybrid structure brings the
Carry generation High performance and low cost products. The design engineers
Can perform a hybrid adder by keeping limitation and advantages
Black cell-It takes two pairs of generate and propagate signal. In Of individual adder in consideration.
output It computes one pair of generate and propagate signal

Grey cell-it gives two pairs of generate and propagate signal’s
input and in output gives generate signal.
Post processing
It is also called final computing.it computes sum
bits the formula is given in equation (8)
S[i] = P[i]XORC [i-1]…………….…….. (8)
Advantages
 It is fastest adder which focus on design time.
Disadvantage
 It occupy more area in memory cell
IV. SIMULATION RESULTS
Different 32 bit adders are implemented like carry select adder, carry
Save adder, carry increment adder, carry skip adder, carry ripple adder,
Carry Lookahead adder, kogge stone adder and by taking this individual
Adder it was modified into 32 bit hybrid adder is implemented in Xilinx
ISE 14.7 using Verilog HDL family Vertex 6 selecting device
XC6VCX75T By grade Speed -2.The new hybrid structure is formed by
Heterogeneous adder Architecture technique. Performance analysis of
All adder structure was observed in terms of Area and propagation
Delay. It was observed that If less area is occupied in memory cell than
Signals can pass easily than there will be less propagation delay
So speed will increase. The modified adder is discussed as below

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 Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)
IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8

 CLA-KSA hybrid adder  CSA_KSA_CSelA

In this modified adder 16 bit carry lookahead adder and 16 bit In this adder 16 bit CSel_KSA is merged with the 16 bit carry
Kogge Stone adder is merged which form 32 bit hybrid adder Save adder. RTL Design is shown in Fig 10
The CLA takes 8 bit input from A and 8 bit input from B
Which produce sum and Carry which goes with 16 bit
Input to kogge store adder the both adder Produce output of 32
Bit. The RTL design is shown in Fig7.

Fig 10 RTL Design of 32 bit CSA_KSA_CSelA

 RCA_CSA

In this modified adder 16 bit Ripple carry Adder is merged with 16 bit
Fig7 RTL Design of 32 bit CLA_KSA carry save adder. RTL Design is shown in Fig 11

 CSelA-KSA
In this hybrid adder there is 16 bit carry select adder and 16 bit
Kogge Stone adder is merged RTL design is shown in Fig 8

Fig 11 RTL design of 32 bit CSA_RCA

Fig 8 RTL Design of CSelA-KSA

 CSel_KSA_KSA  RCA_KSA

In this modified of adder 8bit carry select adder with In this modified adder 16 bit ripple carry adder is merged with 16 bit
8 bit of kogge stone adder and 16 bit of kogge stone adder KSA.RTL design in Fig 12
Is combined. Fig 9 shows RTL design of this modified adder.

Fig 12 RTL Design o 32 bit RCA_KSA

Fig 9 RTL design of CSelA_KSA_KSA

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 Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)
IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8

ADDER DESIGN AREA(LUT) DELAY(In

ns)
Carry select adder 42 5.001
Carry save adder 30 4.766
Carry skip adder 46 6.743
Carry Ripple adder 67 6.925
Carry increment 81 9.456
adder
Carry lookahead 90 10.077
adder
Kogge stone adder 144 5.905
Modified adder-1 78 4.862
KSA_CLA Fig 15 Simulation result of modified adder 3
Modified adder-2 85 3.944
CSelA_KSA
Modified 69 5.770
adder-3
(CSelA_KSA)+KSA
Modified 50 8.65
Adder-4
(CSelA_KSA)+CSA
Modified Adder-5 78 4.262
(RCA_CSA)
Modified Adder-6 86 4.326
(RCA_KSA)

Fig 16 Simulation result of modified adder 4

Table 1 Performance analysis of 32 bit adders

Fig 13, 14, 15, 16, 17, 18 shows simulation waveform result of
modified adders. The modified adder can extend with placing
different adders in modules if one adder is placed in one module
which has inputs A and B which adds produce sum and carry which
pass through other adder that is added with inputs of other adder. All
inputs are added sum and carry is generated
.

Fig 17 Simulation result of modified adder 5

Fig 13 Simulation result of modified adder 1

Fig 14 Simulation result of modified adder 2 Fig 18 Simulation result of modified adder 6

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 Proceedings of the Third International Conference on Trends in Electronics and Informatics (ICOEI 2019)
IEEE Xplore Part Number: CFP19J32-ART; ISBN: 978-1-5386-9439-8

It was observed from table 1 that the kogge stone adder has Large
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