File: /home/vlsilab/Pratik200/jkFF/jkFFexternal/jksim/netlist.

spi Page 1 of 2
* ELDO netlist generated with ICnet by 'vlsilab' on Mon Oct 29 2018 at 13:00:16

.CONNECT GROUND 0

*
* Globals.
*
.global VDD GROUND

*
* Component pathname : /home/vlsilab/Pratik200/2ipNand/nandinternal
*
.subckt NANDINTERNAL$D2$ OUT IN1 IN2

M2 N$7 IN2 GROUND GROUND N L=0.35u W=1.4u M=1

M1 OUT IN1 N$7 GROUND N L=0.35u W=1.4u M=1
M4 OUT IN2 VDD VDD P L=0.35u W=3.4u M=1
M3 OUT IN1 VDD VDD P L=0.35u W=3.4u M=1
.ends NANDINTERNAL$D2$

*
* Component pathname : /home/vlsilab/Desktop/Pratik200/cmosinv/invinternal
*
.subckt INVINTERNAL OUT IN

M2 OUT IN GROUND GROUND N L=0.35u W=1.4u M=1

M1 OUT IN VDD VDD P L=0.35u W=3.4u M=1
.ends INVINTERNAL

*
* Component pathname : /home/vlsilab/Desktop/Pratik200/2ipNand/nandinternal
*
.subckt NANDINTERNAL$D1$ OUT IN1 IN2

M2 N$7 IN2 GROUND GROUND N L=0.35u W=1.4u M=1

M1 OUT IN1 N$7 GROUND N L=0.35u W=1.4u M=1
M4 OUT IN2 VDD VDD P L=0.35u W=3.4u M=1
M3 OUT IN1 VDD VDD P L=0.35u W=3.4u M=1
.ends NANDINTERNAL$D1$

*
* Component pathname : /home/vlsilab/Desktop/Pratik200/2ipand/andinternal
*
.subckt ANDINTERNAL OUT A B

X_INVINTERNAL1 OUT N$7 INVINTERNAL

X_NANDINTERNAL1 N$7 A B NANDINTERNAL$D1$
.ends ANDINTERNAL

*
* Component pathname : /home/vlsilab/Desktop/Pratik200/3ipnand/nand3ipinternal
*
.subckt NAND3IPINTERNAL OUT A B C

X_INVINTERNAL1 OUT N$10 INVINTERNAL

X_ANDINTERNAL2 N$10 N$8 C ANDINTERNAL
X_ANDINTERNAL1 N$8 A B ANDINTERNAL
.ends NAND3IPINTERNAL

*
* Component pathname : /home/vlsilab/Pratik200/jkFF/jkFFinternal
*
.subckt JKFFINTERNAL Q Q_BAR CLOCK J K

X_NANDINTERNAL2 Q_BAR Q N$14 NANDINTERNAL$D2$

X_NANDINTERNAL1 Q N$12 Q_BAR NANDINTERNAL$D2$
X_NAND3IPINTERNAL2 N$14 CLOCK K Q NAND3IPINTERNAL
File: /home/vlsilab/Pratik200/jkFFexternal/jksim/netlist.spi Page 2 of 2
X_NAND3IPINTERNAL1 N$12 Q_BAR J CLOCK NAND3IPINTERNAL
.ends JKFFINTERNAL

*
* MAIN CELL: Component pathname : /home/vlsilab/Pratik200/jkFF/jkFFexternal
*
V3 J GROUND PULSE ( 0V 5V 0 1nS 1nS 60nS 120nS )
V2 K GROUND PULSE ( 0V 5V 0 1nS 1nS 40nS 100nS )
V1 CLK GROUND PULSE ( 0V 5V 0 1nS 1nS 20nS 50nS )
V4 VDD GROUND DC 5V
X_JKFFINTERNAL1 Q Q_BAR CLK J K JKFFINTERNAL
*

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.end

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