Student Verilog HDL LAB MANUAL FOR BE/B.TECH ECE STUDENTS

METHODIST COLLEGE OF
ENGINEERING AND TECHNOLOGY
Department of Electronics and Communication Engineering
VERILOG HDL LAB (EC 382)
B.E III YEAR I SEMESTER
STUDENT OBSERVATION BOOK

NAME: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ROLL NO: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
BRANCH: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
YEAR & SEM: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Prepared by HOD
I.Srikanth
Asst.Prof ECE Dept
MCET , ABIDS
I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

EC332
VERILOG HDL LAB
Instructions 3 Periods per week

Duration of University Examination 3 Hours
University Examination 50 Marks
Sessional 25 Marks
List of Experiments:
Part A
Write the Code using VERILOG, Simulate and synthesize the following:
1. Write structural and dataflow Verilog HDL models for

a) 4-bit ripple carry adder.
b) 4-bit carry Adder – cum Subtractor.
c) 2-digit BCD adder / subtractor.
d) 4-bit carry look ahead adder
e) 4-bit comparator
2. Write a Verilog HDL program in Hierarchical structural model for
a) 16:1 mux realization using 4:1 mux

b) 3:8 decoder realization through 2:4 decoder
c) 8-bit comparator using 4-bit comparators and additional logic
3. Write a Verilog HDL program in behavioral model for
a) 8:1 mux
b) 3:8 decoder
c) 8:3 encoder
d) 8 bit parity generator and checker
4. Write a Verilog HDL program in structural and behavioral models for
a) 8 bit asynchronous up-down counter

b) 8 bit synchronous up-down counter
5. Write a Verilog HDL program for 4 bit sequence detector through Mealy and Moore state
machines.
6. Write a Verilog HDL program for traffic light controller realization through state machine.
7. Write a Verilog HDL program for vending machine controller through state machine.
8. Write a Verilog HDL program in behavioral model for 8 bit shift and add multiplier.

9. Write a Verilog HDL program in structural model for 8 bit Universal Shift Register.
10. Write a Verilog HDL program for implementation of data path and controller units
a) Serial Adder
b) ALU
Note:
1. All the programs should be simulated using test benches.

2. Minimum of two experiments to be implemented on FPGA/CPLD boards.
Part B
General Note: Mini Project cum Design exercise:
The student must design, develop code and test and design the following problems:
i) 8 bit CPU
ii) Generation of different waveforms using DAC
iii) RTL code for Booth’s algorithm for signed binary number multiplication
iv) MAC unit and DSP modules: FIR and IIR Filter
v) Synchronous and Asynchronous Data transfer, UART and Baud rate generator.
v) Design of 4 - bit thermometer to Binary Code Converter
Suggested Reading:
nd
1. Samir Palnitkar, “Verilog HDL A Guide to Digital Design and Synthesis,” 2 Edition,
Pearson Education, 2006.
2. Stephen Brown ,ZvonkoVranesic , “Fundamentals of Digital Logic with Verilog
Design” 3rd Edition Tata McGrahill.
3. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL”, PHI, 2005.

INDEX
S.No EXPERIMENT PERFORME SUBMITED SIGN OF

D DATE DATE FACULTY

D DATE DATE FACULTY

D DATE DATE FACULTY

D DATE DATE FACULTY

4-bit ripple carry adder
AIM:
To write the Verilog code for 4-bit ripple carry adder and obtain the simulation, synthesis results
using Xilinx ISE tool.
APPARATUS:
1. Computer system
2. Xilinx ISE software tool
THEORY:
Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N- bit
parallel adder, there must be N number of full adder circuits. A ripple carry adder is a logic circuit in
which the carry-out of each full adder is the carry in of the succeeding next most significant full
adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. In a
ripple carry adder the sum and carry out bits of any half adder stage is not valid until the carry in of
that stage occurs. Propagation delays inside the logic circuitry is the reason behind this. Propagation
delay is time elapsed between the application of an input and occurance of the corresponding output.
Consider a NOT gate, When the input is “0” the output will be “1” and vice versa. The time taken for
the NOT gate’s output to become “0” after the application of logic “1” to the NOT gate’s input is the
propagation delay here. Similarly the carry propagation delay is the time elapsed between the
application of the carry in signal and the occurance of the carry out (Cout) signal. Circuit diagram of
a 4-bit ripple carry adder is shown below.

PROGRAM:
module ripplecarryadder_4bit(a, b, cin, s, cout);

input [3:0] a;
input [3:0] b;
input cin;
output [3:0] s;
output cout;
wire[0:2]c;
fulladder fa1 (a[0],b[0],cin,s[0],c[0]);
fulladder fa2 (a[1],b[1],c[0],s[1],c[1]);
fulladder fa3 (a[2],b[2],c[1],s[2],c[2]);
fulladder fa4 (a[3],b[3],c[2],s[3],cout);
endmodule
//-------------------- Full Adder Design ---------------------
module fulladder ( a ,b ,c ,sum ,carry );
output sum ;
output carry ;
input a ;input b ;input c ;
assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);
endmodule
TEST BENCH:
module rca4bt_v;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] s;

wire cout;
// Instantiate the Unit Under Test (UUT)

rca4b uut (.a(a), .b(b), .cin(cin), .s(s), .cout(cout));
initial begin
a=0;b=0;cin=0;
#5 a=5;b=2;cin=0;
#5 a=6;b=3;cin=1;
#5 a=10;b=5;cin=1;
end
endmodule

4-bit carry adder – cum subtractor
AIM:
To write the Verilog code for 4-bit carry adder – cum subtractor and obtain the simulation, synthesis
results using Xilinx ISE tool.
APPARATUS:
1. Computer system
THEORY:
The operations of both addition and subtraction can be performed by a one common binary
adder. Such binary circuit can be designed by adding an Ex-OR gate with each full adder as shown in
below figure. The figure below shows the 4 bit parallel binary adder/subtractor which has two 4 bit
inputs as A3A2A1A0 and B3B2B1B0. The mode input control line M is connected with carry input
of the least significant bit of the full adder. This control line decides the type of operation, whether
addition or subtraction.
When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder. The Ex-OR gate
consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-
OR of 0 produce B. Then full adders add the B with A with carry input zero and hence an addition
operation is performed. When M = 1, B Ex-OR of 0 produce B complement and also carry input is
1. Hence the complemented B inputs are added to A and 1 is added through the input carry, nothing
but a 2’s complement operation. Therefore, the subtraction operation is performed.

PROGRAM:
module adder_subtactor_4bit ( a ,b ,sel ,dout );

output [3:0] dout ;
input [3:0] a ;input [3:0] b ;input sel ;

wire [3:0]m;
wire [3:0]n;
adder_4bit u0 (.a (a),.b (b),.sum (m));
subtractor_4bit u1 (.a(a),.b(b),.diff (n));
mux_4bit u2 (.a(m),.b(n),.sel(sel),.dout(dout));
endmodule
//--------------------- Design of 4 bit adder -------------------
module adder_4bit ( a ,b ,sum ,carry );
output [3:0] sum ;
output carry ;
input [3:0] a ;input [3:0] b ; wire [2:0]s;
full_adder u0 (a[0],b[0],1'b0,sum[0],s[0]);
full_adder u1 (a[1],b[1],s[0],sum[1],s[1]);
full_adder u3 (a[3],b[3],s[2],sum[3],carry);
endmodule
//-------------- 4 bit subtractor --------------------
module subtractor_4bit ( a ,b ,diff ,borrow );

output [3:0] diff ;
output borrow ;

input [3:0] a ;
input [3:0] b ;
wire [2:0]s;
wire [3:0]l;
xor(l[0],b[0],1'b1);
xor(l[1],b[1],1'b1);
xor(l[2],b[2],1'b1);
xor(l[3],b[3],1'b1);
fulladder u0 (a[0],l[0],1'b1,diff[0],s[0]);
fulladder u1 (a[1],l[1],s[0],diff[1],s[1]);
fulladder u2 (a[2],l[2],s[1],diff[2],s[2]);
fulladder u3 (a[3],l[3],s[2],diff[3],borrow);
endmodule
//-------------------- Full Adder Design ---------------------
module full_adder ( a ,b ,c ,sum ,carry );
output sum ;
output carry ;
input a ;input b ;input c ;
endmodule
//------------- 2 : 1 Multiplexer (4 bit) Design ------------
module mux_4bit ( a ,b , sel, dout );

output [3:0]dout ;
input [3:0]a ;
input [3:0]b ;
input sel ;
assign dout = sel ? b : a;endmodule

TEST BENCH:
module addsubtf_v;
/ Inputs reg [3:0] a;
reg [3:0] b; reg sel;
/ Outputs
wire [3:0] dout;
adder_subtactor_4bit uut (.a(a), .b(b), .sel(sel), .dout(dout)); initial

begin a=4'b0100;
b=4'b0110;
sel=0;
#100 sel=1;
end
endmodule

AIM:
To write the Verilog code for 4-bit BCD adder/subtractor and obtain the simulation, synthesis results
using Xilinx ISE tool.
APPARATUS:
1. Computer system
THEORY:
BCD binary numbers represent decimal digits 0 to 9. A 4-bit BCD code is used to represent
the ten numbers 0 to 9. Since the 4-bit code allows 16 possibilities, therefore the first 10 4-bit
combinations are considered to be valid combinations. The later six combinations are invalid and
do not occur. BCD Code has applications in Decimal Number display Systems such as Counters
and Digital Clocks. BCD Numbers can be added together using BCD Addition. BCD Addition is
similar to normal Binary Addition except for the case when sum of two BCD digits exceeds 9 or a
Carry is generated. When the sum of two BCD numbers exceeds 9 or a Carry is generated a 6 is
added to convert the invalid number in to a valid number. The carry generated by adding a 6 to the
invalid BDC digit is passed on to the next BCD digit.
Addition of two BCD digits requires two 4-bit Parallel Adder Circuits. One 4-bit parallel
Adder adds the two BCD digits. A BCD Adder uses a circuit which checks the result at the output of
the first adder circuit to determine if the result has exceeded 9 or a Carry has been generated. If the
circuit determines any of the two error conditions the circuit adds a 6 to the original result using the
second Adder circuit. The output of the second Adder gives the correct BCD output. If the circuit
finds the result of the first Adder circuit to be a valid BCD number (between 0 and 9 and no Carry
has been generated), the circuit adds a zero to the valid BCD result using the second Adder. The
output of the second Adder gives the same result.

PROGRAM:
module bcdadder_subtractor ( a ,b ,sel ,dout );

output [3:0] dout ;
input [3:0] a ;
input [3:0] b ;
input sel ;
wire [3:0]m;
wire [3:0]n;
adder_4bit u0 (.a (a),.b (b),.sum (m));
subtractor_4bit u1 (.a(a),.b(b),.diff (n));
mux_4bit u2 (.a(m),.b(n),.sel(sel),.dout(dout));
endmodule
module adder_4bit ( a ,b ,sum ,carry );
output [3:0] sum ;
output carry ;
input [3:0] a ;
input [3:0] b ;
wire [2:0]s;
full_adder u0 (a[0],b[0],1'b0,sum[0],s[0]);
full_adder u3 (a[3],b[3],s[2],sum[3],carry);
endmodule
module full_adder ( a ,b ,c ,sum ,carry );
output sum ;
output carry ;
input a ;
input b ;
input c ;

endmodule
module mux_4bit ( a ,b , sel, dout );
output [3:0]dout ;
input [3:0]a ;
input [3:0]b ;
input sel ;
assign dout = sel ? b : a;
endmodule
module subtractor_4bit ( a ,b ,diff ,borrow );
output [3:0] diff ;
output borrow ;
input [3:0] a ;
input [3:0] b ;
wire [2:0]s;
wire [3:0]l;
xor(l[0],b[0],1'b1);
xor(l[1],b[1],1'b1);
xor(l[2],b[2],1'b1);
xor(l[3],b[3],1'b1);
full_adder u0 (a[0],l[0],1'b1,diff[0],s[0]);
full_adder u1 (a[1],l[1],s[0],diff[1],s[1]);
full_adder u2 (a[2],l[2],s[1],diff[2],s[2]);
full_adder u3 (a[3],l[3],s[2],diff[3],borrow);endmodule
TEST BENCH:
module bcdtest_v;
// Inputs reg [3:0] a;

reg [3:0] b;
reg sel;
// Outputs
wire [3:0] dout;
/ Instantiate the Unit Under Test (UUT) bcdaddersub uut (.a(a),
.b(b), .sel(sel), .dout(dout)); initial

begin a=4'b0001;
b=4'b0010;
sel=0; #100 sel=1;
end
endmodule

4-bit carry look ahead adder
AIM:
To write the Verilog code for 4-bit carry look ahead adder and obtain the simulation, synthesis
APPARATUS:
1. Computer system
THEORY:
The Lookahead Carry Generator provides Carry's C1,C2,C3 and C4 simultaneously after a gate
delay of two. Carry's C1,C2 andC3 are used internally, where asC4 provides the Cout from the
74LS283. Referring to the LookAhead Carry Generator Circuit the C1,C2,C3 and C4 terms are
generated on the basis ofP0,P1,P2 and P3 the four Carry Propagate terms and G0,G1,G2 and G3 the
four Carry Generateterms. These terms are used to generate GroupCarry LookAhead outputs that can
be usedto cascade together multiple units eliminating the problem of rippling carry. The G and P
output provide the groupcarry lookahead outputs that allow multipleALUs tobe cascaded together.
The activelow outputs G and P are represented by theBoolean expressions.
PROGRAM:
module CLA(a,b,cin,sum,carry);
input [3:0] a;
input [3:0] b;
input cin;

output [3:0] sum;
output carry;
wire [3:0]p,g;
wire [2:0]cy;
assign p=a^b;
assign g=a&b;
assign sum[0] = p[0]^cin,
sum[1] = p[1]^cy[0],
sum[2] = p[2]^cy[1],
sum[3] = p[3]^cy[2];
assign cy[0]= g[0]|(p[0]&cin),

cy[1]= g[1]|(p[1]&g[0])|(p[1]&p[0]&cin),
cy[2]= g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&cin);
assign carry =
g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&
cin);
endmodule
TEST BENCH:
module carrylooktest_v;

reg [3:0] b; reg cin;
/ Outputs wire [3:0]

sum; wire carry;
/ Instantiate the Unit Under Test (UUT)
CLA uut (.a(a), .b(b), .cin(cin), .sum(sum), .carry(carry)); initial

begin a=4'b1011;

b=4'b0011;
cin=0;
#10;
a=4'b0101;
b=4'b1111;
cin=1;
end
endmodule

4-bit comparator
AIM:
To write the Verilog code for 4-bit comparator and obtain the simulation, synthesis results using
Xilinx ISE tool.
APPARATUS:
3. Computer system
BLOCK DIAGRAM AND TRUTH TABLE:
PROGRAM:
module comparator4bit(agtb, aetb, altb, a, b);

output agtb;
output aetb;
output altb;
input [3:0]a,b;
reg agtb,aetb,altb;

always@(a,b)
begin
agtb=0;
aetb=0;
altb=0;
if(a==b)
aetb=1;
else if(a>b)
agtb=1;
else
altb=1;
end
endmodule
TEST BENCH:
module comparator_v;
reg [3:0] b;
/ Outputs wire agtb;
wire aetb; wire altb;
comparator4bit uut (.agtb(agtb), .aetb(aetb), .altb(altb), .a(a), .b(b)); initial

begin a=4'b0011;
b=4'b0000;
#100 a=4'b0000;
b=4'b0011;
#100 a=4'b0010;
b=4'b0010;
end
endmodule

6:1 MUX realization using 4:1 MUX
AIM:
To write the Verilog HDL program in hierarchical structural model for 16:1 MUX realization using
4:1 MUX and obtain the simulation, synthesis results using Xilinx ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module mux_4_1(a, b, c, d, s0, s1, y);

input a,b, c, d;
input s1, s0;

output y;
wire s0_bar,s1_bar;
assign s0_bar=~s0;
assign s1_bar=~s1;
assign y = (s0_bar&s1_bar&a)|(s0&s1_bar&b)|(s0_bar&s1&c)|(s0&s1&d);
endmodule
/ Code for /* 16x1 Multiplexer using 4x1 multiplexer*/
module mux_16_1(i, sel, y);

input [15:0]i;
input [3:0] sel;
output y;
wire a,b,c,d;
mux_4_1 m1(i[0],i[1],i[2],i[3],sel[1],sel[0],a);
mux_4_1 m2(i[4],i[5],i[6],i[7],sel[1],sel[0],b); mux_4_1
m3(i[8],i[9],i[10],i[11],sel[1],sel[0],c); mux_4_1
m4(i[12],i[13],i[14],i[15],sel[1],sel[0],d); mux_4_1
m5(a,b,c,d,sel[3],sel[2],y); endmodule
TEST BENCH:
module muxtext_v;
/ Inputs reg [15:0] i;

reg [3:0] sel;
/ Outputs wire y;
/ Instantiate the Unit Under Test (UUT) mux_16_1

uut (.i(i), .sel(sel), .y(y)); initial begin
i=16'b1101_0101_0011_1010;
sel = 0;
#5 sel =1; #5 sel =2;

#5 sel =3; #5 sel =4;
#5 sel =5; #5 sel =6;
#5 sel =7; #5 sel =8;
#5 sel =9; #5 sel =10;
#5 sel =11; #5 sel =12;
#5 sel =13; #5 sel =14;

#5 sel =15;
#100 $finish;
end
endmodule

3:8 decoder realization through 2:4 decoder
AIM:
To write the Verilog HDL program in hierarchical structural model for 3:8 decoder realization
through 2:4 decoder and obtain the simulation, synthesis results using Xilinx ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module decoder2by4(a,en,y);
input [1:0] a;
input en;
output [3:0] y;
reg [3:0] y;
always @(a,en)
if(en==0)
y=1'b0;
else
case(a)

2'b00:y=4'b0001;
2'b01:y=4'b0010;
2'b10:y=4'b0100;
2'b11:y=4'b1000;
default:y=1'bx;
endcase
endmodule
/* Code for 3:8 decoder using 2:4 decoder*/
module dec_3_8(I,y);
input [2:0]I;
output [7:0]y;
decoder2by4 d0 (I[1:0],~I[2],y[3:0]);
decoder2by4 d1 (I[1:0],I[2],y[7:4]);
endmodule
TEST BENCH:
module decoder_v;
/ Inputs reg [2:0] I;
/ Outputs wire [7:0] y;
/ Instantiate the Unit Under Test (UUT) dec_3_8 uut

(.I(I), .y(y));
initial begin I=3'b000;
#10 I=3'b001;
#10 I=3'b010;
#10 I=3'b011;
#10 I=3'b100;
#10 I=3'b101;

#10 I=3'b110;
#10 I=3'b111;
#10 $finish;
end
endmodule

8-bit comparator using 4-bit comparators
AIM:
To write the Verilog HDL program in hierarchical structural model for 8-bit comparator using 4-bit
comparators and additional logic and obtain the simulation, synthesis results using Xilinx ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
An 8-bit comparator compares the two 8-bit numbers by cascading of two 4-bit comparators.
The circuit connection of this comparator is shown below in which the lower order comparator A<B,
A=B and A>B outputs are connected to the respective cascade inputs of the higher order comparator.
For the lower order comparator, the A=B cascade input must be connected High, while the other two
cascading inputs A ,B must be connected to LOW. The outputs of the higher order comparator
become the outputs of this eight-bit comparator.
PROGRAM:
module comp8bit(a, b, a_gt_b, a_lt_b, a_eq_b);

input [7:0]a;
input [7:0]b;
output a_gt_b;
output a_lt_b;
output a_eq_b;
wire agb1,alb1,aeb1,agb2,alb2,aeb2;
wire g,h;
comp4bit compc1(agb1,alb1,aeb1,a[7:4],b[7:4]);

comp4bit compc2(agb2,alb2,aeb2,a[3:0],b[3:0]);
and a1(g,aeb1,agb2);
and a2(h,aeb1,alb2);
or o1(a_gt_b,g,agb1);
or o2(a_lt_b,h,alb1);
and o3(a_eq_b,aeb1,aeb2);
endmodule
module comp4bit(agtb, aetb, altb, a, b);

output agtb;
output aetb;
output altb;
input [3:0]a,b;
reg agtb,aetb,altb;
always@(a,b)
begin
agtb=0;
aetb=0;
altb=0;
if(a==b)
aetb=1;
else if(a>b)
agtb=1;
else
altb=1;
end
endmodule
TEST BENCH:
module compararator_v;
// Inputs

reg [7:0] a;
reg [7:0] b;
/ Outputs wire a_gt_b;
wire a_lt_b; wire a_eq_b;

comp8bit uut (.a(a), .b(b), .a_gt_b(a_gt_b), .a_lt_b(a_lt_b),.a_eq_b(a_eq_b)); initial begin
a = 10; b=2;
#10 a=2;b=2;
#10 a=5;b=7;
end
endmodule

8:1 MUX
AIM:
To write the Verilog code for 8:1 MUX and obtain the simulation, synthesis results using Xilinx ISE
tool.
APPARATUS:
1. Computer system
Selected inputs output

A B C Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
PROGRAM:
module mux8b(i, s, y);

input [0:7] i;
input [0:2] s;
output y;
reg y;
always @ (i or s)
begin

if (s==0)
y=i[0]; else if(s==1)

y=i[6]; else
y=i[7];
end
endmodule
TEST BENCH:
module muxb1_v;
reg [0:2] s;
/ Outputs wire y;
/ Instantiate the Unit Under Test (UUT) mux8b uut

(.i(i), .s(s), .y(y));
initial begin i=8'b0000_1111;s=3'b000;
#5 s=3'b001;
#5 s=3'b010;
#5 s=3'b011;
#5 s=3'b100;
#5 s=3'b101;
#5 s=3'b110;
#5 s=3'b111;end endmodule

3:8 Decoder
AIM:
To write the Verilog code for 3:8 Decoder and obtain the simulation, synthesis results using Xilinx
ISE tool.
APPARATUS:
1. Computer system
PROGRAM:
module decoder3by8(a, b, c, y);

input a;
input b;
input c;
output [0:7] y;
reg [0:7]y;
always @ (a,b,c)
begin

case ({a,b,c})
3'b000:y=8'b0000_0001;
3'b001:y=8'b0000_0010;
3'b010:y=8'b0000_0100;
3'b011:y=8'b0000_1000;
3'b100:y=8'b0001_0000;
3'b101:y=8'b0010_0000;
3'b110:y=8'b0100_0000;
3'b111:y=8'b1000_0000;
default: y=8'b0000_0000;
endcase
end
endmodule
TEST BENCH:
module decoder3by81_v;
/ Inputs reg a; reg
b; reg c;
/ Instantiate the Unit Under Test (UUT) decoder3by8
uut (.a(a), .b(b), .c(c), .y(y)); initial begin
a=1'b0;b=1'b0;c=1'b0;
#5 a=1'b0;b=1'b0;c=1'b1; #5
a=1'b0;b=1'b1;c=1'b0; #5
a=1'b0;b=1'b1;c=1'b1; #5
a=1'b1;b=1'b0;c=1'b0;
#5 a=1'b1;b=1'b0;c=1'b1;
#5 a=1'b1;b=1'b1;c=1'b0;
#5 a=1'b1;b=1'b1;c=1'b1;
end
endmodule

8:3 Encoder
AIM:
To write the Verilog code for 8:3 Encoder and obtain the simulation, synthesis results using Xilinx
ISE tool.
APPARATUS:
1. Computer system
PROGRAM:
module encoder8by3(i, y);
input [7:0] i;
output [2:0] y;
reg [2:0]y;
always @ (i)
begin
case (i)
8'b0000_0001:y=3'b000;
8'b0000_0010:y=3'b001;
8'b0000_0100:y=3'b010;
8'b0000_1000:y=3'b011;
8'b0001_0000:y=3'b100;
8'b0010_0000:y=3'b101;
8'b0100_0000:y=3'b110;
8'b1000_0000:y=3'b111;
default:y=3'bxxx;
endcase
end
endmodule
TEST BENCH:
module encoder8by31_v;
/ Instantiate the Unit Under Test (UUT) encoder8by3

uut (.i(i), .y(y));
initial begin
i=8'b0000_0001;
#10 i=8'b0000_0010;
#10 i=8'b0000_0100;
#10 i=8'b0000_1000;
#10 i=8'b0001_0000;
#10 i=8'b0010_0000;
#10 i=8'b0100_0000;
#10 i=8'b1000_0000;
end
endmodule

8-bit parity generator and checker
AIM:
To write the Verilog code for 8-bit parity generator and checker and obtain the simulation, synthesis
APPARATUS:
1. Computer system
PROGRAM:
module paritychecker(a, y);

input [7:0] a;
output [8:0] y;
reg [8:0] y;
reg even=1;
reg odd=0;
integer i,count;
always @(a)
begin
//count<=0;

for (i=0;i<=7;i=i+1)
begin
if (a[i]==1)
count=count+1;
end
if (count%2==0)
begin
y<={even,a};
$display (" even parity");
end
else
begin
y<={odd,a};
$display (" odd parity");
end
end
endmodule
TEST BENCH:
module paritycheckertb_v;
/ Instantiate the Unit Under Test (UUT) paritychecker

uut (.a(a), .y(y));
initial begin a=8'b00001111; #100
a=8'b00110011; #100
a=8'b10101011;
end
endmodule

Mealy state machines
AIM:
To write the Verilog code for 4 bit sequence detector through Mealy state machines and obtain the
simulation, synthesis results using Xilinx ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module mealy1001(x, clk, rst, y, ps, ns);

input x;
input clk;
input rst;
output y;
output [1:0] ps;
output [1:0] ns;
reg [1:0] ps;
reg [1:0] ns;
reg y;
parameter[1:0] a=2'b00,b=2'b01,c=2'b10,d=2'b11;
always@(posedge clk )
begin
if (rst)

ps<=a;
else
ps<=ns;
end
always@(ps,x)
begin
case(ps)
2'b00: if (x)
ns<=b;
else
ns<=a;
2'b01: if (~x)
ns<=c;
else
ns<=b;
2'b10: if (~x)
ns<=d;
else
ns<=b;
2'b11: if (x)
ns<=b;
else
ns<=a;
endcase
end
always @(ps,ns,x)
begin
if(ps==d & ns==b)
y=1'b1;

else
y=1'b0;
end
endmodule
TEST BENCH:
module mealy1001t_v;
/ Inputs reg x; reg clk;
reg rst;
/ Outputs wire y; wire
[1:0] ps; wire [1:0] ns;

mealy1001 uut (.x(x), .clk(clk), .rst(rst), .y(y), .ps(ps), .ns(ns));
always #5 clk=~clk;
initial begin
clk=1'b0;rst=1'b1;x=1'b0;
#7 rst=1'b0;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;
#10 x=1'b0;
#5 x=1'b1;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;

#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b1;
end
endmodule

Moore state machines
AIM:
To write the Verilog code for 4 bit sequence detector through Moore state machines and obtain the
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module moore(x, clk, rst, y, ps, ns);

input x;
input clk;
input rst;
output y;
output [2:0] ps;
output [2:0] ns;
reg [2:0] ps;
reg [2:0] ns;
reg y;
parameter[2:0] a=3'b000,b=3'b001,c=3'b010,d=3'b011,e=3'b100;
always@(posedge clk )
begin
if (rst)
ps<=a;
else

ps<=ns;
end
always@(ps,x)
begin
case(ps)
3'b000:
if (x)
ns<=b;
else
ns<=a;
3'b001:
if (~x)
ns<=c;
else
ns<=b;
3'b010:
if (~x)
ns<=d;
else
ns<=b;
3'b011:
if (x)
ns<=e;
else
ns<=a;
3'b100:if(x)
ns<=b;
else
ns<=a;

endcase
end
always @(ps,ns,x)
begin
if(ps==e & ns=={a,b})

y=1'b1;
else
y=1'b0;
end
endmodule
TEST BENCH:
module morret_v;
/ Inputs reg x; reg clk;
reg rst;
/ Outputs wire y; wire
[2:0] ps; wire [2:0] ns;

moore uut (.x(x), .clk(clk), .rst(rst), .y(y), .ps(ps), .ns(ns));
always #5 clk=~clk;
initial begin
clk=1'b0;rst=1'b1;x=1'b0;
#7 rst=1'b0;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;

#10 x=1'b0;
#5 x=1'b1;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b0;
#10 x=1'b1;
end
endmodule

Traffic light controller
AIM:
To write the Verilog code for traffic light controller realization through state machine and obtain the
APPARATUS:
1. Computer system
SPECIFICATIONS AND STATE DIAGRAM:
PROGRAM:
module trafficcontroller(clk, clr, x, h, c);
input clk;
input clr;
input x;

output h;
output c;
reg [1:0]h;
reg [1:0]c;
reg [2:0]pst;
reg [2:0]nst;
parameter true=1'b1;
parameter false=1'b0;
parameter red=2'd0;
parameter yellow=2'd1;
parameter green=2'd2;
parameter s0=3'd0;
parameter s1=3'd1;
parameter s2=3'd2;
parameter s3=3'd3;
parameter s4=3'd4;
parameter g2ydelay4=12'b0;
parameter y2rdelay3=12'b1;
initial begin
pst=s0;
nst=s0;
h=green;
c=yellow;
end
always@(posedge clk)
pst=nst;
always@(pst)
begin
case (pst)
s0:begin
h=green;

c=yellow;
end
s1:begin
h=yellow;
c=red;
end
s2:begin
h=red;
c=yellow;
end
s3:begin
h=red;
c=green;
end
s4:begin
h=red;
c=yellow;
end
endcase
end
endmodule
TEST BENCH:
module trafficcontroller1_v;
/ Inputs reg clk;
reg clr; reg x;

/ Outputs wire [1:0] h;
wire [1:0] c;

trafficcontroller uut (.clk(clk), .clr(clr), .x(x), .h(h), .c(c));
always #5clk=~clk;
initial begin
clr=1'b1;
clk=1'b0;
x=1'b0;
#7 clr=1'b0;x=1'b0;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b0;
#10 x=1'b1;
#10 x=1'b1;
#10 x=1'b0;
end
endmodule

vending machine controller
AIM:
To write the Verilog code for vending machine controller through state machine and obtain the
APPARATUS:
1. Computer system
STATE DIAGRAM :
PROGRAM:
module vendingm(clk, clr, n, d, q, y);

input clk;
input clr;
input n;
input d;
input q;
output y;
reg y;
reg[2:0] pst,nst;
parameter s0=3'b000;

always@(pst or d or n or q)
begin
case(pst)
s0:if(n==1'b1&&d==1'b0&&q==1'b0)
begin
nst=s1;
y=1'b0;
end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s2;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)
begin
nst=s5;
y=1'b0;
end
else
begin
nst=s0;
y=1'b0;
end
s1:if(n==1'b1&&d==1'b0&&q==1'b0)
begin
nst=s2;
y=1'b0;

end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s3;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)
begin
nst=s6;
y=1'b0;
end
else
begin
nst=s1;
y=1'b0;
end
s2:if(n==1'b1&&d==1'b0&&q==1'b0)
begin
nst=s3;
y=1'b0;
end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s4;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)
begin
nst=s0;

y=1'b0;
end
else
begin
nst=s2;
y=1'b0;
end
s3:if(n==1'b1&&d==1'b0&&q==1'b0)
begin
nst=s4;
y=1'b0;
end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s5;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)
begin
nst=s1;
y=1'b0;
end
else
begin
nst=s3;
y=1'b0;
end
s4:if(n==1'b1&&d==1'b0&&q==1'b0)
begin

nst=s5;
y=1'b0;
end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s6;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)
begin
nst=s2;
y=1'b0;
end
else
begin
nst=s4;
y=1'b0;
end
s5:if(n==1'b1&&d==1'b0&&q==1'b0)
begin
nst=s6;
y=1'b0;
end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s0;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)

begin
nst=s3;
y=1'b0;
end
else
begin
nst=s5;
y=1'b0;
end
s6:if(n==1'b1&&d==1'b0&&q==1'b0)
begin
nst=s0;
y=1'b0;
end
else if(n==1'b0&&d==1'b1&&q==1'b0)
begin
nst=s1;
y=1'b0;
end
else if(n==1'b0&&d==1'b0&&q==1'b1)
begin
nst=s4;
y=1'b0;
end
else
begin
nst=s6;
y=1'b0;
end

default:nst=s0;
endcase
end
begin
if(clr==1'b1)
nst=s0;
else
pst=nst;
end
endmodule
TEST BENCH:
module vendingmtb_v;
/ Inputs reg clk; reg
clr; reg n; reg d; reg q;
/ Outputs wire y;
vendingm uut (.clk(clk), .clr(clr), .n(n), .d(d), .q(q), .y(y)); always #5

clk=~clk;
initial begin
clr=1'b0;
clk=1'b0;
n=0;
d=0;

q=0;
#10 clr=1'b0;
#10 n=1'b0; d=1'b0; q=1'b0;
#10 n=1'b0; d=1'b0; q=1'b1;
#10 n=1'b0; d=1'b1; q=1'b0;

#10 n=1'b0; d=1'b1; q=1'b1;
#10 n=1'b1; d=1'b0; q=1'b0;
#10 n=1'b1; d=1'b0; q=1'b1;
#10 n=1'b1; d=1'b1; q=1'b0;
#10 n=1'b1; d=1'b1; q=1'b1;
end
endmodule

8- bit shift and add multiplier
AIM:
To write the Verilog code for 8 -bit shift and add multiplier and obtain the simulation, synthesis
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
Example
PROGRAM:
module shiftadd(p,a,b,clk,s);
output reg[7:0]p;
input [3:0]a,b;
input clk,s;
reg [3:0]x;
reg [7:0]y;
always @(posedge clk)
begin
case(s)
1'b0:begin

x=a;
y[3:0]=b;
y[7:4]=4'b0000;
end
1'b1:begin
if(y[0]) y[7:4]=y[7:4]+x;
y={1'b0,y[7:1]};
end
endcase
p=y;
end
endmodule
module multfix_v;
TEST BENCH:
/ Inputs reg [3:0] a; reg
[3:0] b; reg clk; reg s;
/ Outputs wire [7:0] p;
/ Instantiate the Unit Under Test (UUT) shiftadd uut (.p(p),
.a(a), .b(b), .clk(clk), .s(s)); always #5

clk=~clk; initial begin
/ Initialize Inputs clk=1'b1;

s<=1'b0;
a=4'b0011;
b=4'b0010;
#100 s<=1'b1;
end
endmodule

8- bit Universal Shift Register
AIM:
To write the Verilog code for 8- bit Universal Shift Register and obtain the simulation, synthesis
APPARATUS:
3. Computer system
BLOCK DIAGRAM :
PROGRAM:
module unv(load, shift, inp, clk, rst, op);

input load;
input [1:0] shift;
input [7:0] inp;
input clk;
input rst;
output reg[7:0] op;
reg[7:0] temp;
always@(posedge clk or posedge rst)
begin
if(rst)
op=0;
else

case(load)
1'b1:
begin
temp=inp;
end
1'b0:
case(shift)
2'b00:op=temp>>1; //right
2'b01:op=temp<<1; //left
2'b10:op={temp[6:0], temp[7]}; //rotateleft
2'b11:op={temp[0], temp[7:0]}; //rotateright

endcase
endcase
end
endmodule
TEST BENCH:
module unvtb_v;
// Inputs
reg load;
reg [1:0] shift;
reg [7:0] inp;
reg clk;
reg rst;
// Outputs
wire [7:0] op;
unv uut (.load(load), .shift(shift), .inp(inp), .clk(clk), .rst(rst), .op(op)); initial

begin clk=1'b1;

forever #50 clk=~clk;
end
initial begin
inp=8'b11001100;
rst=1'b0;
load=1'b0;
shift=2'b00;
#100;
inp=8'b10001100;
rst=1'b1;
load=1'b1;
shift=2'b01;
#100;
inp=8'b11001100;
load=1'b1;
shift=2'b10;
#100;
inp=8'b10101011;
rst=1'b1;
load=1'b1;
shift=2'b11;
end
endmodule

Serial adder
AIM:
To write the Verilog code for serial adder and obtain the simulation, synthesis results using Xilinx
ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module shift(y,d,clk);
input [3:0] d;
input clk;
output [3:0] y;
reg [3:0] y;
initial begin
assign y=d;
end
begin
assign y=y>>1;

end
endmodule
//serial in parallel out register to store the 4 bit sum
module sipo(y,s,clk);
input s;
input clk;
output [3:0] y;
reg [3:0] y;
begin
assign y={y[3:1],s};
end
endmodule
//1 bit full adder
module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
assign s=a ^ b ^ cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule //d flipflop to store the cout of each stage
module dff(q,d,clk);
input d,clk;
output q;
reg q;
//initial begin
//q=1'b0;
//end
begin

q=d;
end
endmodule //main module serial adder//
module serial(sum,cout,a,b,clk);
input [3:0] a,b;

input clk;
wire [3:0] x,z;
output [3:0] sum;
output cout;
wire s,cin;
fa k(s,cout,x[3:0],z[3:0],cin); //1 bit full adder
dff q(cin,cout,clk); //d flipflop to store the cout value after each 1 bit full
adder operation
sipo m(sum,s,clk); //serial sum(s) converted to parallel output(4 bit sum)///

shift g(x,a,clk); //shifts the input a
shift h(z,b,clk); //shifts the input b
endmodule
TEST BENCH:
module textfix_v;
reg [3:0] b; reg clk;
/ Outputs wire [3:0]

sum; wire cout;
serial uut (.sum(sum), .cout(cout), .a(a), .b(b), .clk(clk)); initial

begin clk=0;
a=4'b0010;b=4'b0110;
#30 $finish;
end
always
#5 clk=~clk;
endmodule

ALU
AIM:
To write the Verilog code for ALU and obtain the simulation, synthesis results using Xilinx ISE tool.
APPARATUS:
3. Computer system
BLOCK DIAGRAM :
PROGRAM:
module alu8op(a,b,s,f);
input [3:0]a;
input [3:0]b;
input [2:0]s;
output [3:0]f;
reg[3:0]f;
always@(s,a,b)
case(s)
0:f=4'b0000;
1:f=b-a;
2:f=a-b;
3:f=a+b;
4:f=a^b;
5:f=a|b;

6:f=a&b;
7:f=4'b1111;
endcase
endmodule
TEST BENCH:
module alu8op1_v;
reg [3:0] b; reg [2:0] s;
/ Outputs wire [3:0] f;
/ Instantiate the Unit Under Test (UUT) alu8op uut

(.a(a), .b(b), .s(s), .f(f)); initial begin
a=4'b0110;b=4'b1001;
s=3'b000; #10 s=3'b001; #10
s=3'b010; #10 s=3'b011; #10
s=3'b100; #10 s=3'b101; #10
s=3'b110; #10 s=3'b111;
a=4'b1010;b=4'b0110; s=3'b00;
#10 s=3'b001; #10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;
end
endmodule

8-bit Synchronous clear up-down counter
AIM:
To write the Verilog code for 8-bit Synchronous clear up-down counter and obtain the simulation,
synthesis results using Xilinx ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module sync_counter(rst, clk, up_down,out);

input rst, clk, up_down;
output reg [7:0]out;
begin
if(rst)
out <= 0;
else
if(up_down)
out <= out+1;
else
out <=out-1;
end
endmodule

TEST BENCH:
module synch_v;
/ Inputs reg rst; reg

clk;
reg up_down;
/ Outputs wire [7:0] out;

sync_counter uut (.rst(rst), .clk(clk), .up_down(up_down), .out(out));
initial begin
clk=1;
rst =1;
up_down = 1;
#10 rst = 0;
#125 up_down = 0;
//#30 up_down = 1;
end
always #5 clk=~clk;
endmodule

8-bit Asynchronous clear up-down counter
AIM:
To write the Verilog code for 8-bit Asynchronous clear up-down counter and obtain the simulation,
synthesis results using Xilinx ISE tool.
APPARATUS:
1. Computer system
BLOCK DIAGRAM :
PROGRAM:
module counter (CLK, CLR, UP_DOWN, Q);
input CLK, CLR, UP_DOWN;

output [7:0] Q;
reg [7:0] tmp;
always @(posedge CLK or posedge CLR)
begin
if (CLR)
tmp = 8'b00000000;
else
if (UP_DOWN)
tmp = tmp + 1'b1;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule
TEST BENCH:
module countertb_v;

/ Inputs reg C; reg
CLR;
reg UP_DOWN;
/ Outputs
wire [7:0] Q;
counter uut (.C(C), .CLR(CLR), .UP_DOWN(UP_DOWN), .Q(Q)); initial
begin CLK=1;
CLR =1;
UP_DOWN = 1;
#10 CLR = 0;
#125 UP_DOWN = 0;
//#30 up_down = 1;
end
always #5 CLK=~CLK;
endmodule


Student Verilog HDL LAB MANUAL FOR BE/B.TECH ECE STUDENTS

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Student Verilog HDL LAB MANUAL FOR BE/B.TECH ECE STUDENTS

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METHODIST COLLEGE OF

ENGINEERING AND TECHNOLOGY

Department of Electronics and Communication Engineering

VERILOG HDL LAB (EC 382)

B.E III YEAR I SEMESTER

STUDENT OBSERVATION BOOK

YEAR & SEM: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

Instructions 3 Periods per week

1. Write structural and dataflow Verilog HDL models for

2. Write a Verilog HDL program in Hierarchical structural model for

a) 16:1 mux realization using 4:1 mux

3. Write a Verilog HDL program in behavioral model for

4. Write a Verilog HDL program in structural and behavioral models for

a) 8 bit asynchronous up-down counter

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

1. All the programs should be simulated using test benches.

General Note: Mini Project cum Design exercise:

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

S.No EXPERIMENT PERFORME SUBMITED SIGN OF

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

S.No EXPERIMENT PERFORME SUBMITED SIGN OF

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

module ripplecarryadder_4bit(a, b, cin, s, cout);

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

// Instantiate the Unit Under Test (UUT)

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

module adder_subtactor_4bit ( a ,b ,sel ,dout );

input [3:0] a ;input [3:0] b ;input sel ;

module subtractor_4bit ( a ,b ,diff ,borrow );

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

module mux_4bit ( a ,b , sel, dout );

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

/ Inputs reg [3:0] a;

reg [3:0] b; reg sel;

// Instantiate the Unit Under Test (UUT)

adder_subtactor_4bit uut (.a(a), .b(b), .sel(sel), .dout(dout)); initial

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

module bcdadder_subtractor ( a ,b ,sel ,dout );

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

/ Instantiate the Unit Under Test (UUT) bcdaddersub uut (.a(a),

.b(b), .sel(sel), .dout(dout)); initial

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

assign cy[0]= g[0]|(p[0]&cin),

/ Inputs reg [3:0] a;

/ Outputs wire [3:0]

CLA uut (.a(a), .b(b), .cin(cin), .sum(sum), .carry(carry)); initial

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

module comparator4bit(agtb, aetb, altb, a, b);

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

/ Inputs reg [3:0] a;

/ Outputs wire agtb;

wire aetb; wire altb;

/ Instantiate the Unit Under Test (UUT)

comparator4bit uut (.agtb(agtb), .aetb(aetb), .altb(altb), .a(a), .b(b)); initial

I.Srikanth Asst.Prof ECE Dept, MCET ,ABIDS

module mux_4_1(a, b, c, d, s0, s1, y);