Vlsi Lab Manual 17ecl77 2020 Sait

DEPARTMENT OF ELECTRONICS AND COMMUNICTION ENGINEERING
M.S.PALYA, BANGALORE – 560097.
VLSI LAB MANUAL

(17ECL77)
Prepared By
Prof.K.Ezhilarasan
Professor, Department of ECE
Sambhram IT
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2020
Sambhram Institute of Technology
K.Ezhilarasan
Professor,
Dept of Electronics and communication
Cadence
Analog Design Digital Design Analog and Mixed

signal Design
VLSI LAB MANUAL Page 2 of 69
Digital design & Analog Design

VLSI LAB
SUBJECT CODE: 17ECL77 I.A.MARKS:40
NO.OF PRACTICAL HRS/WEEK: 03 EXAM HOURS: 03
TOTAL NO.OF PRACTICAL HRS: 42 EXAM MARKS: 60
PART-A
DIGITAL DESIGN
ASIC-DIGITAL DESIGN FLOW
1. Write VERILOG code for the following circuits and their test bench for Verification, observe
the waveform and synthesis the code with technological library with given constraints*. Do the
initial timing verification with gate level simulation.
(i). an Inverter
(ii). A Buffer
(iii). Transmission Gate
(IV). Basic/Universal gates
(v). Flip flop –RS flip flop, D flip flop, JK flip f lop, Master Slave flip flop, T flip flop
(vi). Serial & Parallel adder
(vii). 4-bit counter [synchronous and Asynchronous counter]
(viii).Successive approximation registers [SAR]
*An approximation constraint should be given
PART-B
ANALOG DESIGN
ANALOG DESIGN FLOW
1. Design an Inverter with the given specifications*, completing the design flow mentioned
below:
a. Draw the schematic and verify the following
(i) DC Analysis
(ii) Transient Analysis
b. Draw the Layout and verify the DRC [Design Rule Checker], ERC [Electrical Rule
Checker]
c. Check for LVS [Layout Vs Schematic]
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint***
2. Design the following circuits with given specifications*, completing the design flow
mentioned below:
(i) DC Analysis
(ii) AC Analysis
(iii) Transient Analysis
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Checker]
(i) A single stage differential amplifier
(ii) Common source and Common Drain amplifier
3. Design an Op-amp with given specification* using the differential amplifier Common source
and Common Drain amplifier in library** and completing the design flow mentioned below:
(i) DC Analysis
(ii) AC Analysis
Checker]
4. Design a 4-bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
(i) DC Analysis
(ii) AC Analysis
Checker]
5.For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and
verify the functionality by completing ASIC design FLOW.[ specifications too GDS-II]
Comparator
Vin
High when Vtest< Vin
Vtest
DAC Output
B0
bn
Clock
SAR
Reset
* Appropriate specification should be given

**Applicable Library should be added & information should be given to the designer
***An approximate constraint should be given
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VLSI DESIGN FLOW (Front end & Back end Design)
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PART-A
Digital Design
Procedure:
1. In the desktop, right click and go to terminal window

2. In the terminal window type the given below
csh
source cshrc (Note: cshrc is a file, that will communicate client machine to the VLSI server)
nclaunch
3. The following screen will appear like shown in figure
4. nclaunch window will open now..
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5. Go to Fileset design directory
6. In set design directory browse (design directory) now u have to set your design
directory( where you are created your design directory)(path is root/cadence/and_gate)
7. Now u have to set library mapping file, in that click on create cds.lib file and save it in your
design directory (Note :cds.lib file will be create for each and every folder created by user)
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8.Now the Verilog files will appear in design browser window
9. Now compile the design file and test bench file (click the vlog icon)
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Vlog
10. Now elaborate the both files, in right side expand the work lib directory and click the both
file (click next to vlog icon)
Elaborator
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Here it shows Source File
names (or) HDL File names
Here it shows the Module

name of the HDL File
11.Now go to tools click simulate
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12. Now in the simulate window, click the drop down menu in snapshot and set the
testbench.module, then click ok
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13. Now minimize/close the console window… In the design browser window, click the test
bench in left side, then in right side click the send to waveform icon
Click this
icon
14. Now click the run button in simulation window for simulation. (Now click the mouse inside
the wave form and drag it for checking the output)
Click the Run

Button to get
waveform
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Click this Arrow to go
for previous/next edge
of the pulse
RTL Compiler procedure:

In terminal window, type the following commands
csh
Source cshrc
rc –gui
Now RTL compiler window will open, and then minimize that window
In the rc shell window, you have to type the following command
Note: copy the library file and keep it in separate folder (Eg.root/cadence/rclabs/library) and
create folder named rtl in the same path (root/cadence/rclabs/rtl)
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Example rc script:
set_attr lib_search_path /root/Cadence/rclabs/library  this is for to set up the library path

set_attr hdl_search_path /root/Cadence/rclabs/rtl  this is for to set up the hdl search path
set_attr library {slow_highvt.lib slow_normal.lib}-- these are available libraries in the library
folder (Path is…../root/Cadence/rclabs/library)
read_hdl hdl_file name.v (Eg.not1.v)--. This command will read the hdl file
elaborate topmodule_name (module name of inverter)… this will create the drivers for i/p and
o/p
synthesize –to_mapped
Note: for elaborate you have to give the top level module name .E.g..for parallel adder
read_hdl {fulladdder.v parallel_adder.v}

elaborate parallel_adder
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Switch Level Model Tutorial
Syntax for MOS Switch:
nmos n1(out , data , control ) ; => nmos na (drain, source, gate)

pmos p1(out , data , control ) ; => pmos p1 (drain, source, gate)
Two types of MOS switches, nmos is used to model NMOS transistor, pmos is used to
model PMOS transistors. The symbols for NMOS and PMOS switches are shown below.
CMOS Switch
cmos c1(out , data , ncontrol , pcontrol ) ;
CMOS switches are declared with the keyword cmos. A CMOS device can be
modeled with a NMOS and PMOS devices. The symbol for a CMOS switch is shown
below.
Bidirection Switch
tran t1( inout1, inout2 ) ;

tranif0 t2 (inout1, inout2 , control ) ;
tranif1 t3 (inout1, inout2 , control ) ;
The tran switch acts as a buffer between the two signals inout1 and in-out2. Either
inout1, or inout2 can be driver signal. The tranif0 switch connects the two signals inout1 and
inout2 only if the control signal is logic 0. If the control signal is a logic 1, the nondriver
signal gets a high impedance value z. The driver signal retains value from its driver. The
tranif1 switch conducts if the control signal is a logic 1.
The symbols for these switches are shown below.
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Resistive Switch
rnmos n2(out , data , control ) ;
rpmos p2(out , data , control ) ;
rcmos c2(out , data , control ) ; rtran
t4(inout1 , inout2 ) ;
rtranif0 t5(inout1 , inout2 , control ) ;
rtranif1 t6(inout1 , inout2 , control ) ;
Resistive switches have a higher source to drain impedance than regular switches and
reduce the strength of signals when the signal passes through them. Resistive
switches have the same syntax as regular switches.
Basic Design Example
There are four examples to describe the gate level design. Each example will contain
(1) transistor circuit (2) verilog code (3) test stimulus code (4) simulation result
(5) simulation waveform
CMOS NOR Gate Design
We design our own nor gate, using CMOS switches. The gate and the switch level
circuit diagram for the nor gate is show below.
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Verilog Code
Using the switch primitives discussed first, the verilog description of the circuit is shown below.
module my_nor(out, A, B);

output out;
input A, B;
wire c;
Pwr is connected supply1 pwr; //pwr is connected to Vdd
to vdd supply0 gnd; //gnd is connected to Vss(ground)
pmos (c, pwr, B);
pmos (out, c, A);
nmos (out, gnd, A);
Gnd is connected nmos (out, gnd, B);
to vss endmodule
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Test Stimulus Code
Now, we can test our_nor gate, using the stimulus is shown below.
module stimulus;
Call my_nor reg A, B;
module wire OUT;
my_nor n1(OUT, A, B);

initial
Test all possible begin
combinations
A = 1'b0; B = 1'b0;
#10 A = 1'b0; B = 1'b1;
#10 A = 1'b1; B = 1'b0;
#10 A = 1'b1; B = 1'b1;
#10 A = 1'b0; B = 1'b0;
Show result
end
initial
$monitor($time, " OUT = %b, A = %b, B = %b", OUT, A, B);
endmodule
Simulation Result
The output of the simulation is shown below.
Simulation result
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Simulation Waveform
According truth table, when input contains 1, then output is 0.
1-Bit Full Adder Design
Using the CMOS design the 1-bit full adder, the logic diagram is shown below.
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Verilog Code
We are now ready to write the verilog description for a full adder. First, we need to
design our own inverter my_not and my_xor by using switches. We can write the
verilog module description for the CMOS inverter from the switch-level circuit
diagram.
module my_not(out, in);

Built my_not //Define output input
module output out;
input in;
//Define power and ground
supply1 pwr;
supply0 gnd;
//Instantiate the CMOS switches pmos
(out,pwr,in);
nmos (out,gnd,in);
endmodule
We need to design our xor module by using switches, too. We can write the verilog
module description for CMOS xor form the switch-level
circuit diagram.
module my_xor(out,a,b);
output out;
input a,b; wire
c;
Call my_not
module previous
my_not nt(c,a);
//Instantiate the CMOS switches cmos

(out,b,c,a);
pmos (out,a,b); nmos
(out,c,b); endmodule
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Now, the 1-bit full adder can be defined using the CMOS switch and my_not inverter. The
verilog description for a 1-bit full adder is shown below.
//Define a CMOS Adder

module adder(sum,cout,a,b,cin);
Call my_xor module //Define input output and internal wire output
previous sum,cout;
input a,b,cin;
wire d,e,f,g
my_xor n1(f,a,b);
my_not n2(d,f);
my_not n3(e,cin);
my_not n4(g,b);
Call my_not module
my_not n5(sum,h);
previous
my_not n6(cout,i);
//Define instantiate CMOS switches cmos

(h,e,d,f);
cmos (h,cin,f,d);
cmos (i,g,d,f);
cmos (i,e,f,d);
endmodule
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Test Stimulus Code
We will test 1-bit full adder, using the stimulus is shown below.
//Define stimulus module

module stimulus;
Call adder //Define input output reg
module a,b,cin;
wire sum,cout;
adder n1(sum,cout,a,b,cin);
Show result
initial
$monitor($time," sum=%b cout=%b a=%b b=%b
cin=%b",sum,cout,a,b,cin);
initial
begin
Test all possible
#5 a=1'b0; b=1'b0; cin=1'b0;
combinations
#5 a=1'b0; b=1'b0; cin=1'b1;
#5 a=1'b0; b=1'b1; cin=1'b0;
#5 a=1'b0; b=1'b1; cin=1'b1;
#5 a=1'b1; b=1'b0; cin=1'b0;
#5 a=1'b1; b=1'b0; cin=1'b1;
#5 a=1'b1; b=1'b1; cin=1'b0;
#5 a=1'b1; b=1'b1; cin=1'b1; end
endmodule
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Simulation Result
Simulation result is shown below.
All possible
Combinations
Simulation Waveform
According to mathematical equation, we can get waveform is shown below.
sum = ( a + b + c in )
c ou t = ( a × b ) + cin × ( a x b )
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2 to 1 Multiplexer Design
The 2 to 1 multiplexer can be defined with CMOS switches. We will use the my_nor
gate declared before. The circuit diagram for the multiplexer is show below.
Verilog Code
The 2 to 1 multiplexer passes the input I0 to output if S=0 and passes I1 to OUT if
S =1. The switch level description for the 2 to 1 multiplexer is shown below.
Complement of s
module my_mux (out, s, i0, i1);

output out;
Equivalent to a input s, i0, i1;
not gate wire sbar ;
my_nor nt(sbar, s, s);
cmos (out, i0, sbar, s);

cmos (out, i1, s, sbar);
endmodule
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Test Stimulus Code
We will check 2 to 1 multiplexer as shown below.
module stimulus;
reg S, I0, I1;

wire OUT;
First combination my_mux m1(OUT, S, I0, I1);
initial
begin
I0 = 1'b1; I1 = 1'b0; S =
1'b0;
Second combination #5 S = 1'b1;
#5 I0 = 1'b0; I1 = 1'b1;
S = 1'b0;
#5 S = 1'b1;
end
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//check results initial
$monitor($time," OUT= %b, S= %b I0= %b, I1=
%b",OUT,S,I0,I1);
Endmodule
Simulation Result
When S=0, then OUT=I0, otherwise, when S=1, then OUT= I1.
Simulation waveform
The simulation is used to waveform check 2 to 1 multiplexer correctly.

Ouput I0 Output I1 Output I0
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Simple CMOS D-Flip-Flop Design
The diagram for a D Flip-Flop is show below. The switche C1 and C2 are CMOS
switches. Switch C1 is open if clk =1, and switch C2 is open if clk=0. Complement of
the clk is fed to the ncontrol input of C2.
Verilog Code
We are now ready to write the verilog description for the CMOS Flip-Flop. We
will use my_not module previous example.
module dff ( q, qbar, d, clk);

output q, qbar;
input d, clk;
wire e;
wire nclk;
Call my_not module my_not nt(nclk, clk);
cmos (e, d, clk, nclk);
cmos (e, q, nclk, clk);
my_not nt1(qbar, e);
my_not nt2(q, qbar); endmo
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Test Stimulus Code
The design is checked by the stimulus as shown below. The module stimulus
stimulates the D-Flip-Flop by applying a few input combinations and monitors the
result.
module stimulus;
reg D, CLK;
wire Q, QBAR;
//instantiate the CMOS flipflop dff
c1(Q, QBAR, D, CLK);
Flip-flop will load //test load and store using stimulus initial
data begin
//sequence 1
CLK = 1'b0;
D = 1'b1;
Flip-flop will
#5 CLK = 1'b1;
load data
#5 CLK = 1'b0;
//sequence 2
#5 D = 1'b0;
#5 CLK = 1'b1;
#5 D=1'b1;CLK = 1'b0;
end
//check output
initial
begin
$monitor($time," CLK = %b, D = %b, Q = %b,
QBAR = %b ", CLK, D, Q, QBAR);
end
endmodule
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Simulation Result
When clk =0, output keep previous value. Otherwise, clk=1 input value is loaded.
Simulation Waveform
When clk =1, output is changed.

Experiment No. 1 Inverter
AIM.
Write Verilog Code for inverter and Test Bench for verification, observe the waveform and
synthesize the code with technological library with given Constraints.
THEORY.
CMOS inverter, a logic gate which converts a high input to low and low to high. When the input
is high, the n- MOSFET on the bottom switches on, pulling the output to ground. The p-MOSFET on top
switches off. When the input is low, the gate-source voltage on the n-MOSFET is below its threshold, so
it switches off, and the p-MOSFET switches on to pull the output high.
Verilog code (data flow model):

module not_1(a,y);
input a;
output y;
assign y = ~ a;
endmodule
Verilog code (switch level model):

module inv (a,y);
input a;
output y;
supply1 vdd;
supply0 vss;
pmos p1 (y,vdd,a);
nmos n1 (y,vss,a);
endmodule
Test bench code:

module not_1_test;
reg a;
wire y;
not_1 n1(a,y);
initial
begin
a=0;
#10 a=1'b1;
#15 a=1'b0;
#10 a=1'b1;
#5 a=1'b1;
end
endmodule
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Simulation output waveform:
RTL view:
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Experiment: 2 Buffer
AIM.
Write Verilog Code for buffer and Test Bench for verification, observe the waveform and
THEORY.
A buffer is a CMOS circuit used to temporarily hold data while it is being used to move
from one place to another. Typically, the data is stored in a buffer as it is retrieved from an
input device or just before it is sent to an output device. It is used mainly when there is a delay
needed in sending a data
Verilog code (data flow model):
module buffer ( out, in);

output out;
input in;
wire a;
inv i1 (a,in);
inv i2 (out,a);
endmodule
Verilog code (switch level model):
module buffer (out,in);

input in;
output out;
supply1 vdd;
supply0 vss;
wire a;
inv i1 (in, a);
inv i2 (a, out);
endmodule
Test bench code:
module buf_test;
wire out ;
reg in ;
buffer b1( out, in);
initial
begin
in=0;
#10 in = 1'b0 ;
#10 in = 1'b1 ;
#10 in = 1'bx ;
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#10 in = 1'bz ;
end
endmodule
RTL view:
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Experiment: 3 Transmission gate
AIM.
Write Verilog Code for Transmission gate and Test Bench for verification, observe the
waveform and synthesize the code with technological library with given Constraints.
THEORY.
A transmission gate, or analog switch, is defined as an electronic element that will

selectively block or pass a signal level from the input to the output. This solid-state switch is
comprised of a pMOS transistor and nMOS transistor. The control gates are biased in a
complementary manner so that both transistors are either on or off. When the voltage on node A
is a Logic 1, the complementary Logic 0 is applied to node active-low A, allowing both
transistors to conduct and pass the signal at IN to OUT. When the voltage on node active-low A
is a Logic 0, the complementary Logic 1 is applied to node A, turning both transistors off and
forcing a high-impedance condition on both the IN and OUT nodes. This high-impedance
condition represents the third "state" (high, low, or high-Z).
Verilog code(data flow model):

module tg (y,a,ctrl);
input a,ctrl;
output y;
reg y;
always @ (a or ctrl)
begin
if (ctrl)
y=a;
else
y=1'bz;
end
endmodule
Verilog code(data flow model):
module tg (in,out,ctrl);
input in, ctrl;
output out;
wire ctrl_bar;
pmos p1 (in,ctrl_bar,out);
nmos n1 (in, ctrl, out);
inv i1 (ctrl,ctrl_bar);
endmodule
Testbench code:
module tg_test;
reg a,ctrl;
wire y;
tg t1 (y,a,ctrl);
initial
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begin
a=0; ctrl=0;
end
always
begin
#10 a= ~a;
#25 ctrl = ~ctrl;
end endmodule
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RTL view:
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Experiment: 4 Basic Gates/Universal Gates
AIM:
Write Verilog code for NAND, NOR, AND, OR, XOR & XNOR gate and test bench for
verification, observe the waveform and synthesis the code with technological library with give
constraints.
THEORY:
AND gate  The AND gate is a basic digital logic gate A HIGH output (1) results only if both
the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a LOW
output results. In another sense, the function of AND effectively finds the minimum between two binary
digits
OR Gate  The OR gate is a digital logic Gate a HIGH output (1) results if one or both
the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW output (0) results. In
another sense, the function of OR effectively finds the maximum between two binary digits.
NAND gate  The Negated AND, NOT AND or NAND gate is the opposite of the digital AND
gate, and behaves in a manner that corresponds to the opposite of AND gate. A LOW output results only
if both inputs to the gate are HIGH. If one or more inputs are LOW, a HIGH output results.
NOR gate  The NOR gate is a digital logic gate A HIGH output (1) results if both the
inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output (0) results. NOR
is the result of the negation of the OR operator.
XOR gate The XOR gate (sometimes EOR gate or EXOR gate) is a digital logic gate
that implements an exclusive or; that is , if any one of the input is HIGH then the output goes to
HIGH(1) and if both inputs are LOW or HIGH then output goes LOW(0).
XNOR gate  The XNOR gate (sometimes spelled "exnor" or "enor") is a digital logic
gate whose function is the inverse of the exclusive OR (XOR) gate. A HIGH output (1) results if
both of the inputs to the gate are the same. If one but not both inputs are HIGH (1), a LOW
output (0) results.
Verilog code for nand_gate (Data flow model):

module and_2(a,b,y);
input a,b;
output y;
assign y = ~(a & b);
endmodule
Verilog code for nand_gate (switch level model):

module nand_gate (a,b,y);
input a,b;
output y;
wire s1;
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supply1 vdd;
supply0 vss;
pmos p1 (y,vdd,a);
pmos p1 (y,vdd,b);
nmos n1 (s1,y,a);
nmos n2 (vss,s1,b);
endmodule
testbench code:
module and_2_test;
reg a,b;
wire y;
and_2 a1(a,b,y);
initial
begin
a=0;
b=0;
end
always
begin
#10 a=~ a;
#25 b= ~b;
end
endmodule
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RTL view:
Verilog code for nor_gate(data flow model):
module orgate (a,b,y);

input a,b;
output y;
assign y = ~(a | b);
endmodule
Verilog code for nor_gate (switch level model):

module nor_gate (a,b,y);
input a,b;
output y;
wire s1;
supply1 vdd;
supply0 vss;
nmos n1 (y,vdd,a);
nmos n2 (y,vdd,b);
pmos p1 (s1,y,a);
pmos p2 (vss,s1,b);
endmodule
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testbench code:
module orgate_test;
reg a,b;
wire y;
orgate o1(a,b,y);
initial
begin
a=0;
b=0;
end
always
begin
#10 a=~ a;
#25 b= ~b;
end
endmodule
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RTL view:
Verilog code for xor_gate(dataflow model)
module xor_2(a,b,y);
input a,b;
output y;
assign y = a ^ b;
endmodule
Verilog Code (Switch level model):
Module xor_2 (a,b,y);

Input a,b;
Output y;
Wire abar, bbar,x;
Pmos p1 (x,a,bbar);
Nmos n1 (x,bbar,abar);
Pmos p2 (x,b,abar);
Nmos n2 (x, b, a);
Inv i1 (y,x);
endmodule
testbench code:
module xor_2_test;
reg a,b;
wire y;
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xor_2 a1(a,b,y);
initial
begin
a=0;
b=0;
end
always
begin
#10 a=~ a;
#25 b= ~b;
end
endmodule
RTL view:
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Verilog code for xnor_gate:
module xnor_2(a,b,y);
input a,b;
output y;
assign y = ~(a ^ b);
endmodule
Verilog Code (Switch level model):
Module xnor_2 (a,b,y);

Input a,b;
Output y;
Wire abar, bbar,x;
Pmos p1 (x,abar,b);
Nmos n1 (x,b,a);
Pmos p2 (x,bbar,a);
Nmos n2 (x, bbar, abar);
Inv i1 (y,x);
endmodule
testbench code:
module xor_2_test;
reg a,b;
wire y;
xor_2 a1(a,b,y);
initial
begin
a=0;
b=0;
end
always
begin
#10 a=~ a;
#25 b= ~b;
end
endmodule
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RTL view:
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Experiment: 5 Full adder
Verilog code:
module fulladd(a,b,cin,s,c);
input a,b,cin;
output s,c;
assign s = (a^b)^cin ;
assign c = (a & b) || (b & c) || (a & c);
endmodule
testbench code:
module full_test;
reg a,b,cin;
wire s,c;
fulladd f1(a,b,cin,s,c);
initial
begin
a=0;
b=0;
cin=0;
end
always
begin
#5 a=~a;
#10 b = ~b;
#15 cin= ~cin;
end
endmodule
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RTL view:
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Experiment: 6 Parallel Adder
AIM:
Write Verilog Code for parallel adder and Test Bench for verification, observe the
THEORY:
Parallel adders are digital circuits that compute the addition of variable binary strings of
equivalent or different size in parallel
Verilog code:
module adder4 ( carryin,x,y,sum,carryout);

input carryin;
input [3:0] x,y;
output [3:0] sum;
output carryout;
fulladd stage0 (carryin, x[0],y[0],sum[0],c1);

fulladd stage1 (c1,x[1],y[1],sum[1],c2);
fulladd stage2 (c2,x[2],y[2],sum[2],c3);
fulladd stage3 (c3,x[3],y[3],sum[3],carryout);
endmodule
testbench code:
module adder4_t ;
reg [3:0] x,y;

reg carryin;
wire [3:0] sum;
wire carryout;
adder4 a1 ( carryin,x,y,sum,carryout);
initial
begin
x = 4'b0000; y= 4'b0000;carryin = 1'b0;

#20 x =4'b1111; y = 4'b1010;
#40 x =4'b1011; y =4'b0110;
#40 x =4'b1111; y=4'b1111;
end
endmodule

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RTL view:
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Experiment: 7 Flip Flops
AIM.
Write Verilog Code for RS flip flop and Test Bench for verification, observe the
THEORY.
The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset
when the R input high and S input is low. The Flip Flop is set when the S input is high and R
input is low. When both the inputs are high the output is in an indeterminate
state.
Verilog code for SR Flip flop:
module sr_ff(q,qbar,s,r,clk);
output q,qbar;
input clk,s,r;
reg tq;
always @(posedge clk or tq)

begin
if (s == 1'b0 && r == 1'b0)
tq <= tq;
else if (s == 1'b0 && r == 1'b1)
tq <= 1'b0;
else if (s == 1'b1 && r == 1'b0)
tq <= 1'b1;
else if (s == 1'b1 && r == 1'b1)
tq <= 1'bx;
end
assign q = tq;
assign qbar = ~tq;
endmodule
testbench:
module sr_ff_test;
reg clk,s,r;
wire q,qbar;
sr_ff sr1(q,qbar,s,r,clk);
initial
begin
clk = 1'b0;s=0;r=1'b1;
#5 s=0; r=1'b1;
#5 s=1'b1; r=0;
#5 s=0; r=0;
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#10 s=1'b1; r=1'b1;
#5 s=0; r=0;
end
always #5 clk = ~clk;

initial #100 $finish;
endmodule
RTL view:
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AIM.
Write Verilog Code for D flip flop and Test Bench for verification, observe the
THEORY.
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time. This is obtained by making the two inputs complement of each other
Verilog code for D Flip flop:
module d_ff(q,clk,rst,din);
output q;
input clk,din,rst;
reg q;
always @(posedge clk)

begin
if (rst)
q <= 1'b0;
else
q <= din;
end
endmodule
Testbench Code:
module d_ff_test;
reg clk, din, rst;

wire q;
d_ff df1 (q, clk, rst, din);
initial
begin
clk = 1'b0;rst=1'b1;din=0;
#10 rst=0;
#15 din=1'b1;
#22 din=0;
#11 din=1'b1;
#5 rst=1'b1;
end
always
#10 clk = ~clk;
endmodule
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RTL view:
Page 52 of 69
AIM.
Write Verilog Code for JK flip flop and Test Bench for verification, observe the
THEORY.
The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs
behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input
and the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When
the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their
previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When
both the inputs are high the output toggles continuously. This is called Race around condition
and this must be avoided.
Verilog code for JK Flip flop:
module jkff(jk,clk,q,q_bar);
input [0:1] jk;
input clk;
output q, q_bar;
reg q, q_bar;
always @ (posedge clk )
begin
case (jk)
2'd0 : q=q;
2'd1 : q=0;
2'd2 : q=1;
2'd3 : q=~q;
endcase
end
assign q_bar=~q;
endmodule
testbench code:
module jk_ff_test;
reg clk,rst,j,k;
wire q,qbar;
jk_ff inst(q,qbar,clk,rst,j,k);
initial
begin
clk = 1'b0;rst=1'b1; j=0;k=1’b1;
#10 rst=1'b0;
#10 j=1'b1; k=1'b0;
#10 j=1'b0; k=1'b0;
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#10 j=1'b0; k=1'b1;
#10 j=1'b1; k=1'b1;
end
endmodule
RTL view:
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AIM.
Write Verilog Code for T flip flop and Test Bench for verification, observe the waveform
and synthesize the code with technological library with given Constraints.
THEORY.
This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs
together. T Flip Flop is also called Toggle Flip Flop.
Verilog code for T- Flip flop:
module t_ff(q,qbar,clk,tin,rst);
output q,qbar;
input clk,tin,rst;
reg q;
begin
if(rst)
q <= 1'b0;
else if (tin)
q <= ~q;
end
assign qbar = ~q;
endmodule
testbench:
module t_ff_test;
reg clk,tin,rst;
wire q,qbar;
t_ff t1(q,qbar,clk,tin,rst);
initial
begin
clk = 1'b0;rst=1'b1;
#10 rst=1'b0;
#20 tin =1'b1;
#40 tin =1'b0;
#50 tin=1'b1;
end
endmodule
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RTL view:
Page 56 of 69
AIM.
Write Verilog Code for MS flip flop and Test Bench for verification, observe the
waveform and synthesize the code wth technological library with given constraints.
THEORY
A master-slave flip is constructed from two separate flip- flops. One circuit serves as a
master and the other as a slave. The logic diagram of an SR flip flop is shown in Figure. The
master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is
disabled by the inverter. The information at the external R and S inputs is transmitted to the
master flip flop when the pulse returns to 0, the master flip flop is disabled and the slave flip-flop
is enabled. The slave flip flop then goes to the same as the master flip flop.
Verilog code for JK Master Slave flips flop (Using Behavioral Model):
module ms_jkff(q,q_bar,clk,j,k);
output q,q_bar;
input clk,j,k;
reg tq,q,q_bar;
always @(clk)
begin
if (!clk)
begin
if (j==1'b0 && k==1'b1)
tq <= 1'b0;
else if (j==1'b1 && k==1'b0)
tq <= 1'b1;
else if (j==1'b1 && k==1'b1)
tq <= ~tq;
end
if (clk)
begin
q <= tq;
q_bar <= ~tq;
end
end
endmodule
Verilog code for JK Master Slave flips flop (Using structural Model):
module jkff_ms (jk,clk,q,q_bar);

input [0:1] jk;
input clk;
output q,q_bar;
wire q1, q1_bar,clk_bar;
assign clk=~clk_bar;
jkff j1 (jk[0], jk[1], clk, q1, q1_bar);
jkff j2 (q1, q1_bar, clk_bar, q, q_bar);
endmodule
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Test bench code:
module tb_ms_jkff;
reg clk,j,k;
wire q,q_bar;
ms_jkff inst(q,q_bar,clk,j,k);
initial
clk = 1'b0;
always #10
clk = ~clk;
initial
begin
j = 1'b0; k = 1'b0;
#60 j = 1'b0; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#20 j = 1'b1; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#5 j = 1'b0; #20 j = 1'b1;
#10 ;
end
endmodule
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RTL view:
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Experiment: 8 Serial Adder
AIM:
Write Verilog Code for serial adder and Test Bench for verification, observe the waveform and
THEORY:
The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by
bit. The serial full adder has three single-bit inputs for the numbers to be added and the carry in. There are
two single-bit outputs for the sum and carry out. The carry-in signal is the previously calculated carry-out
signal. The addition is performed by adding each bit, lowest to highest, one per clock cycle .
Verilog code for shift register:
module shiftrne ( R,L,E,w,clock,q);
parameter n=8;
input [n-1:0] R;
input L,E,w,clock;
output [n-1:0] q;
reg [n-1:0] q;
integer k;
always @(posedge clock)

if (L)
q <= R;
else if (E)
begin
for (k=n-1;k>0;k=k-1)
q[k-1] <= q[k];
q[n-1] <= w;
end
endmodule
Verilog code for serial adder:
module serial_adder ( A,B, reset, clock, sum);

input [7:0] A,B;
input reset,clock;
output [7:0] sum;
reg [3:0] count;
reg s,y,Y;
wire [7:0] qa,qb,sum;
wire run;
parameter G=0,H=1;
shiftrne shift_A (A,reset,1'b1,1'b0,clock,qa);

shiftrne shift_B (B,reset,1'b1,1'b0,clock,qb);
shiftrne shift_sum (8'b0,reset,run,s,clock,sum);
//adder fsm
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//output and next state combinational circuit
always @(qa or qb or y)
case (y)
G: begin
s = qa[0]^qb[0];
if (qa[0] & qb[0])
Y = H;
else
Y = G;
end
H: begin
s = qa[0] ~^qb[0];
if (~qa[0] & ~qb[0])
Y =G;
else
Y = H;
end
default : Y = G;
endcase
//sequential block
if (reset)
y <= G;
else
y <= Y;
//control the shifting process
Testbench code:
module serial_adder_t ;
reg [7:0] A,B;
reg reset,clock;
wire [7:0] sum ;
initial
clock = 1'b0;
always
#5 clock =~clock;
serial_adder s1 (A,B,reset,clock,sum);
initial
begin
reset = 1'b0;A = 8'b10101010; B = 8'b11111111;
#20 reset = 1'b1;
#20 reset = 1'b0;
#150 reset = 1'b1; A = 8'b11110000 ; B = 8'b11110011;
#20 reset = 1'b0;
end
initial
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$monitor ($time, " SUM = %d ", sum);
endmodule
RTL view:
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Experiment: 9 Counters (synchronous & Asynchronous)
AIM:
Write Verilog Code for counter and Test Bench for verification, observe the waveform and
THEORY:
A counter consists of a cascade of flip-flops connected so that the output of one flip-flop drives
the input of the next. The signals to be counted are fed into the first flip-flop of the chain. The output Q,
of any given flip-flop represents a binary digit or bit (value 0 or 1). The complete set of outputs (Q3, Q2,
Q1, Q0) gives the total number of pulses in binary arithmetic, hence the name Binary Counter.
Verilog code for synchronous counter:
module sync_count ( count,reset,clk);

input reset, clk;
output [3:0] count;
reg [3:0] count;
begin
if (reset)
count = 4'b0000;
else
count = count + 4'b0001;
end
endmodule
testbench code:
Testbench Program:
module sync_count_test ;
wire [3:0] count;
reg reset,clk;
sync_count m1 ( count,reset,clk);
initial
begin
clk = 1'b0;
reset=1'b1;
#15 reset=1'b0;
end
endmodule
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RTL view:
Verilog code for Asynchronous counter:
module async_count( clk, count );

input clk;
output[3:0] count;
reg[3:0] count;
initial
count = 4'b0;
always @( negedge clk )
count[0] <= ~count[0];
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always @( negedge count[0] )


endmodule
testbench code:
module async_count_test;
reg clk;
wire[3:0] count;
async_count async_count1 ( clk, count );
initial clk = 0;
endmodule
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RTL view:
Page 66 of 69
Experiment No.10 - Successive Approximation Register
AIM.
Write Verilog Code for Successive approximation register and Test Bench for verification,
observe the waveform and synthesize the code with technological library with given
Constraints.
THEORY.
A successive approximation ADC is a type of analog to- digital converter that converts a
continuous analog waveform into a discrete digital representation via a binary search through all
possible quantization levels before finally converging upon a digital output for each conversion.
VERILOG CODE.
module sar ( R,L,E,w,clock,q);

parameter n=8;
input [n-1:0] R;
input L,E,w,clock;
output [n-1:0] q;
reg [n-1:0] q;
integer k;
if (L)
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q <= R;
else if (E)
begin
for (k=n-1;k>0;k=k-1)
q[k-1] <= q[k];
q[n-1] <= w;
end
endmodule
TEST BENCH.
module sar_t;
reg [7:0] r;
reg l;
reg e;
reg w;
reg clk;
wire [7:0] q;
sar sf(.R(r),.L(l),.E(e),.w(w),.clock(clk),.q(q));
initial
begin
clk = 1'b0;
l = 1'b1;
w = 1'b0;
e = 1'b0;
#5 r = 8'b11110000;
#10 l = 1'b0;
e = 1'b1;
#10 w = 1'b0;
#10 w = 1'b1;
$finish;
end
endmodule
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SIMULATION OUTPUT WAVEFORM
RTL OUTPUT
Page 69 of 69
Analog Design
PART – B
Procedure:
Starting with Cadence tool
Right click on Desktop, open the terminal window and type the given below
(Note: Use the installed database)
1. Change the directory by entering by this command

cd cadence_ms_labs_613
csh
source cshrc
virtuoso &
2. Now, command interpreter window (CIW) will appear at the bottom of the screen.
3. Close the “What’s new” window & Keep opened CIW window.
4. Now, go to File Newlibrary
5. In the new library form give your “Name” & also verify that path to the library is set to
~/Cadence/cadence_ms_labs_613 and click ok.
6. In the next “technology file for new library” form, select option “Attach to an existing tech
file” and click ok.
7. Next “attach library to technology file” form will appear, select “gpdk180” from the cyclic
field and click ok.
8. After creating a new library you can verify it from the library manager.
9. Now Library manager window will appear, in that select your folder with “Name” in the
library column.
10. Go to FileNewCellview
11. Set up the new file form as follows
Library: your folder named with “Name” (Note: Don’t edit the library path)
Cell : Give the Name of your experiment, i.e, “example” (Note: only this you should edit)
View : Schematic
Type : schematic
12. After setting everything then click ok. Now schematic window screen will appear.
Note: The following steps you should keep it in your mind while doing your experiment
(i) Schematic creation
(ii) Symbol creating
(iii) Test the given circuit with the help of input sources and power supply’s.
13. After schematic window screen appears, create the instance (or) components by pressing the
letter “ i” in keyboard. (Note: In menu bar Createinstance)
14. Click on browse button in instance form, library manger window will get open, from this window
you can select the required components for to draw schematic diagram.
Note: The following instance will use to create schematic with suitable library
(i) Gpdk180 for MOS transistors
(ii) AnalogLib for vdd, vss, input source
15. Now you will update the library name, cell name, and the property values given in the table
below. (Note: umicro)
Library Name Cell Name/View Properties of Instance
Gpdk180 Pmos/Symbol For M0: Model name=pmos1,W=2u,L=180n

(or) spectre
Gpdk180 Nmos/Symbol For N0:Model name=nmos1, W=2u,L=180n

(or) spectre
16. After you select the instance, move your curser to the schematic window and click left to
place a component. (Note: After placed the instance, the same instance will be in tip of the
mouse until you press “esc” in keyboard)
17. If you place a component with the wrong parameter values, use the menu bar
EditpropertiesObjects command to change the parameters. Use EditMove command if
you place components in the wrong location. You can rotate components at the time you place
them, or use the EditRotate command after they are placed.
(Note: to edit the instance, select the instance the press ‘q’ in keyboard)
18. After entering components, click cancel in the add instance form or press “esc” with your
cursor in the schematic window.
19. Next, create pins for input, output, vdd, vss
20. In menu bar go to Create  Pin (or) press ‘p’ in keyboard., Add pin form will appear, then
type the following in the add pin form in the exact order leaving space between the pin names.
Pin Names Direction
Vin Input
Vout Output
(Note: make sure that the direction field is set to input/output/inputOutput when placing the
input/output/inout pin respectively)
21. Select Cancel from add pin form after placing the pins.
(Note: In the schematic window, In menu bar, go to WindowFit or press ‘f’ in keyboard)
22. After keep all the instances in the schematic window, next we have to interconnect the
connection with the help of wire.
23. In menu bar, go to createwire(narrow) (or) press ‘w’ in keyboard (or) wire(narrow) icon in
the schematic window.
24. In the schematic window, click on a pin of one of your components as the first point for your
wiring. A diamond shape will appear over the starting point of this wire.
25. Follow the prompts at the bottom of the design window and click left on the destination
point for your wire. A wire is routed between the source and destination points.
26. Complete the wiring as shown in figure and when done wiring press ‘esc’ key in the
schematic window to cancel wiring.
(Note: click on the starting point and drag the mouse, again click on the destination point)
27. After did the connections, now go to FileCheck and save (or) click “check and Save”icon in
28. Observe the CIW window output area for any errors. (Note: errors will highlight with yellow
colour box in the schematic window)
29. After Schematic is completed, next we have to create symbol from the schematic.
SYMBOL GENERATION
30. In the Schematic window, go to menu bar, CreateCellViewFrom Cell View.
31. The cell view From Cellview form appears. With the edit options functions active, you can
control the appearance of the symbol to generate.
32. Next, modify the symbol as follows:
Left pin: Specify the pin name, what you given in the left side of your schematic (e.g, vin,)
Right pin: specify the pin name, what you given in the right side of your schematic (e.g, Vout)
Top pin: specify the pin name, what you given in the top of your schematic (e.g, Vdd)
Bottom pin: specify the pin name, what you given in the bottom of your schematic (e.g,Vss)
Then click ok in the symbol generation option form.
33. A new window displays an automatically created symbol of schematic.
34. Check and save, close the symbol window.

BUILDING THE TEST DESIGN
35. Now, you will create schematic test circuit, In the library manager, go to
FileNewcellview (Note: select your “name” in the library column before create
cellview)
36.Next, setup the new file form as follows:
Library: your library “name”
Cell: example_test
View: schematic
Type: schematic, then click ok when done. A blank schematic window for the
example_test design appears.
37. Using the components list and properties/comments in this table. Build the
example_test schematic.
Library Name Cell name View name Properties/comments
Name Example Symbol Select the instance of your

symbol
analogLib Input sources (e.g, Symbol Select the source for your
vpulse,vsin,idc,etc..,) required design
analogLib Supply sources-vdd,vss Symbol Select the required source

(e.g, vdc,gnd)
(Note: Remember to set the values for supply sources, otherwise your circuit will have no
power)
38. Add the above components using Create – Instance or by pressing ‘I’ in keyboard
39. Click the wire (narrow) or press ‘w’ in keyboard to connect all the wiring in the
circuit.
40. Create output pin and place in the suitable place and click on the check and save icon
to save the design.
ANALOG SIMULATION WITH SPECTRE
In this section, we will run the simulation for example and plot the transient, DC
characteristics, AC analysis, noise analysis, parametric analysis etc..,
1. In the example_test schematic window, go to LaunchADE L (Note: The Virtuoso
Analog Design Environment (ADE) simulation window appears).
2. Next, In the ADE window, click the chooseAnalysis, the form will appear
3. Now setup for the various analyses (e.g, transient analysis, DC, AC etc..,)
4. After setup all the analyses click ok. Next go to outputTo be plotted Select on
schematic in the ADE window.
5. Follow the prompt at the bottom of the schematic window, click on output net (wire)
Vout, input net (wire) vin of the example. Press ESC with the cursor in the schematic
after selecting it.
6. Now, go to simulationNetlist and Run in the ADE window to start the simulation or
the icon, this will create the netlist as well as run the simulation.
7. When simulation finishes, the transient, DC, AC plots automatically will be popped up
along with log file.
(Note: if you try to close the ADE window, it will ask to save, click yes to save the
information else click No)
CREATING LAYOUT VIEW OF EXAMPLE

1. From the example schematic window, go to LaunchLayout XL. A startup option
form appears.
2. Select create new option. This gives a New cell view form
3. Check the cellname (example). Viewname (layout)
4. Click ok from the new cell view form.LSW and a blank layout window appear along
with schematic window.
5. Now, In the Layout window, go to connectivityGenerateAll from source in the

layout editor window. Generate Layout form appears. Click ok which imports the
schematic components in to the layout window automatically (e.g, pmos, nmos,
input sources, power supply, output sources)
6. Re arrange the components within the PR- Boundary (Not applicable in New version)
7. To re arrange the components, we have to move the component to the boundary,

for that first select the component which will highlight with pink colour, then press
‘s’ in the keyboard to move.(Note: If the boundary is not sufficient, you can extend
the horizontal and vertical line by using the key ‘s’ to stretch the line, it can be stretch
either in horizontal or vertical direction at a time)
8. After keeping the pMOS and nMOS in the boundary, re arrange the input pins,
output pins, vdd and vss.
9. To re arrange those pins, go to placepin placement, the pin placement form

window will appear now.(optional)
10. Now in this window, click on the vdd, vdd to create a VDD rails, VSS rails in vertical or
horizontal direction. Now click place as schematic in the same window, then click
ok.(optional)
11. Now all are in the boundary
12. Now press “shift+f” to view the pMOS and nMOS layout view
13. Now connect the P1_NWELL and M1_PSUB with the respective mos
transistors.(Note: To get Psub & Nsub substrates, go to createVia)
Note; In new version, in the schematic L editing, go to properties of pmos/nmos

device and change the body tie type as integrated/detached based on your design.
14. Next connect all the terminals with the help of wire(Metal), To create metal go to
createwire, now keep the mouse in any of the poly or metal, this will indicate the
connection to connect. Click source and leave in destination place, the metals will
routed successfully
15. To connect poly to metal, just click on the poly and drag the mouse, now do right
click select viaup, now you will get the contact, then again just do the click to place
the contact and drag to connect with metal (input pin).
16. After finishes all the metal connection, save your design
17. Now go to AssuraDRC, then click ok(Note: Design Rule Checker)
18. IF there is no error in the design you will get “no DRC error” in window.
19. Next, go to AssuraLVS, then click ok. (Note: Layout versus Schematic).
(Note: In the LVS debug form you can find the details of mismatches and you need to
correct all those mismatches and Re-run the LVS till you will be able to match the
schematic with layout)
20. If there is no error, you will get “layout & Schematic is matched” in the LVS window.
21. Next, go to AssuraRun RCX
22. Change the following in the Assura parasitic extraction form. Select output type
under setup tab of the form.
23. In the “Extraction” tab of the form, choose Extraction type “RC”, cap coupling mode
“coupled” and specify the reference node for extraction.
24. In the “Filtering” tab of the form, Enter power nets as vdd!, vss! And enter ground
nets as gnd!. And click ok in the assura parasitic extraction form when done.
25. When RCX completes, a dialog box appears, inform you that Assura RCX run
completed successfully. (New version has QRC instead of RCX)
26. Now, you can open the av_extracted view from the library manager and view the
parasitic.
27. CREATING THE CONFIGURATION VIEW- In this we will create a config view and with
this config view we will run the simulation with and without parasitic.
28. Now, go to library mangerFileNewcellview
29. In the create new file form, set the following, then click ok in create new file form.
30. The hierarchy editor form opens and a new configuration form opens in front of it. In
this click use template at the bottom of the new configuration form and select
spectre in the cyclic field and click ok. The global bindings list are located from the
template.
31. Change the top cell view to schematic and remove the default entry from the library
list field. Next, click ok in the new configuration form.
32. The hierarchy editor displays the hierarchy for this design using table format
33. Click the Tree view tab. The design hierarchy changes to tree format. The form
should look like this. And save the current configuration.
34. Close the hierarchy editor window. Fileclose window.
TO RUN THE CIRCUIT WITHOUT PARASITES
35. From the library manager open “example_test” config view. Open configuration or
top cellview form appears.
36. In the form, turn on the both cyclic buttons to YES and click ok.The example_test
schematic and example_test config window appears. Notice the window
banner of schematic also states config: “Name” example_test config
37. Now go to launchADE L from the schematic window.
38. Now you need to follow the same procedure for running the simulation. Executing
session-Load state, ADE window loads the previous state.
39. Click Netlist & Run icon to start the simulation, the simulation takes a few seconds
and then waveform window appears.
40. In the CIW, note the netlisting statistics in the circuit inventory section. This list
includes all nets, design devices, sources and loads. There are no parasitic
components. Also note down the circuit inventory section.
Binding Keys:
Key comments
W Wire
P Pin
I Instance
M Move
S Stretch
Shift+f To view the pmos &nMOS in layout
Del Delete the particular instance or object
Esc Escape
Q Properties of the object
Technology: 180nm
Digital Design (Cadence Tools Used) : Incisive simulator (nc launch), RTL Compiler (Sythesis)
Analog Design: IC616-Virtuoso (spectre), Virtuoso XL, Assura( DRC & LVS)
Tran Analysis:
EXPERIMENT NO.1
CMOS INVERTER
Aim:
Design an Inverter with given specifications, completing the design flow mentioned below:
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
e. Verify & Optimize for Time, Power and Area to the given Constraint.
Operation:
From Figure 1, a CMOS circuit is composed of two MOSFETs. The top FET (MP) is a
PMOS type device while the Bottom FET (MN) is an NMOS type. The body effect is not
present in either device since the body of each device is directly connected to the device’s
source. Both gates are connected to the input line. The output line connects to the drains of
both FETs.
Take a look at the VTC in Figure 2. The curve represents the output voltage taken from node
3. You can easily see that the CMOS circuit functions as an inverter by noting that when
VIN is five volts, VOUT is zero, and vice versa. Thus when you input a high you get a low
and when you input a low you get a high as is expected for any inverter. You might be
wondering what happens in the middle, transition area of the curve. You might also be
curious as to what modes of operation the MOSFETs are in. We will look at these issues
next.
Figu
re 2: Basic Voltage Transfer Characteristic
Figure 1: CMOS inverter

DC Analysis:
Figure 3 shows a more detailed VTC. Before we begin our analysis it is important to mention three
items.
The MOSFETS must be perfectly matched for optimum operation, that is, they must have the same
threshold voltage magnitude and conduction parameter. The drain current (ID) through the NMOS
device equals the drain current through the PMOS device at all times. MOSFET gates have a high
input impedance and we assume the circuit’s output sees no significant loading. VDD equals the
voltage across the PMOS plus the voltage across the NMOS by KVL.
Figure 3: VTC with Input Signal
Region I
First we focus our attention on region I. In this case when we apply an input voltage between 0 and
VTN. The PMOS device on since a low voltage is being applied to it. The NMOS is already negative
enough and has no use for more free electrons so it refuses to conduct and turns into a large
resistor. Since the NMOS device is on vacation, there is no current flow through either device. VDD
is available at the Vo terminal since no current is going through the PMOS device and thus no
voltage is being dropped across it.
 The PMOS device is forward biased (VSG > -VTP) and therefore on. This MOSFET is in the
linear region (VSD<=VSG+VTP=VDD-Vo+VTP).
 The NMOS device is cut off since the input voltage is below VTN (Vi=VGS<VTN).
 The power dissipation is zero.
Region II
Here we raise the input voltage above VTN. We find that the PMOS device remains in the linear
region since it still has adequate forward bias. The NMOS turns on and jumps immediately into
saturation since it still has a relatively large VDS across it.
 The PMOS device is in the linear region (VSD<=VSG+VTP).

 The NMOS device is in the saturation region (Vi=VDS>=VGS-VTN=Vo-VTN).
 Current now flows through both devices. Power dissipation is no longer zero.
 The maximum allowable input voltage at the low logic state (VIL) occurs in this region. VIL is
the value of Vi at the point where the slope of the VTC is -1. Put another way, VIL occurs at
(dVo/dVi)=-1.
Region III
In the middle of this region there exists a point where Vi=Vo. We label this point VM and identify it
as the gate threshold voltage. The voltage dropped across the NMOS device equals the voltage
dropped across the PMOS device when the input voltage is VM. For a very short time, both devices
see enough forward bias voltage to drive them to saturation.
 The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vo+VTP).

 The NMOS device is in the saturation region (VDS>=VGS-VTN=Vo-VTN).
 Power dissipation reaches a peak in this region, namely at where VM=Vi=Vo.
Region IV
Region IV occurs between an input voltages slightly higher than VM but lower than VDD-VTP. Now
the NMOS device is conducting in the linear region, dropping a low voltage across VDS. Since VDS is
relatively low, the PMOS device must pick up the tab and drop the rest of the voltage (VDD-VDS)
across its VSD junction. This, in turn, drives the PMOS into saturation. This region is effectively the
reverse of region II.
 The PMOS device is in the saturation region (VSD>=VSG+VTP=VDD-Vo+VTP).

 The NMOS device is forward biased (Vi=VGS > VTN) and therefore on. This MOSFET is in the
linear region (Vi=VDS<=VGS-VTN=Vo-VTN).
 The minimum allowable input voltage at the logic high state (VIH) occurs in this region. VIH
occurs at the point where the slope of the VTC is –1 (dVo/dVi)=-1.
Region V
The NMOS wants to conduct but its drain current is severely limited due to the PMOS device only
letting through a tiny leakage current. The PMOS is out to lunch since it is seeing a positive drive but
it is already positive enough and has no use for more. This drain current let through by the PMOS is
too small to matter in most practical cases so we let ID=0. With this information we can conclude
that VDS=Vo=0 V for the NMOS since no current is going through the device. We have, in effect,
sent in VDD and found the inverter’s output to be zero volts. For CMOS inverters, VOH=VDD. VOL
is defined to be the output voltage of the inverter at an input voltage of VOH. We have just proven
thatVOL=0.
 The PMOS device is cut off when the input is at VDD (VSG=0 V).
 The NMOS device is forward biased (Vi=VGS > VTN) and therefore on. This MOSFET is in the
linear region (Vi=VDS<=VGS-VTN).
 The total power dissipation is zero just as in region I.
Procedure:

cd cadence_ms_labs_613
csh
Source cshrc
Virtuoso
5. In the new library form give your “VLSI_LAB” & also verify that path to the library is set to
6. In the next “technology file for new library” form, select option “Attach to an existing
tech file” and click ok.
field and click ok.
library column.
Library: your folder named with “VLSI_LAB” (Note: Don’t edit the library path)
Cell : Inverter
View : Schematic
Type : schematic
Note: The following steps you should keep it in mind while doing your experiment
letter ‘I’ in keyboard. (Note: In menu bar Createinstance)
Gpdk180 pmos/Symbol For M0: Model name=pmos1,W=2u,L=180n

(or) spectre
Gpdk180 nmos/Symbol For N0:Model name=nmos1, W=2u,L=180n

(or) spectre
Pin Names Direction
Vin Input
Vout Output
23. In menu bar, go to createwire(narrow) (or) press ‘w’ in keyboard (or) wire(narrow) icon in
27. After did the connections, now go to FileCheck and save (or) click “check and Save” icon in
SYMBOL GENERATION
30. In the Schematic window, go to menu bar, CreateCellViewFrom Cell View.
Left pin: vin

Right pin: vout
Top pin: vdd
Bottom pin: vss
FileNewcellview (Note: select your “VLSI_LAB” in the library column before create
cellview)
36. Next, setup the new file form as follows:
Library: your library “VLSI_LAB”

Cell: inverter_test
View: schematic
inverter_test design appears.
inverter_test schematic.
Library Name Cell name View name Properties/comments
VLSI_LAB Inverter Symbol Select the instance of your

symbol
analogLib Vpulse Symbol V1=0, v2=1.8, pulse

width=10n, period=20n
analogLib Vdc, gnd Symbol Vdc=1.8
(Note: Remember to set the values for supply sources, otherwise your circuit will have
no power)
circuit.
to save the design.
1. In the inverter_test schematic window, go to LaunchADE L (Note: The Virtuoso

Transient analysis:
a. In the analysis section select tran

b. set the stop time as 200n
c. click at the moderate or enabled button at the bottom, and then click apply.
DC Analysis:
a. In the analysis section, select dc.

b. In the DC analysis section, turn on save DC operating point.
c. Turn on the component parameter.
d. Double click the select component, which takes you to the schematic window.
e. Select the input signal vpulse source in the test schematic window.
f. Select “DC Voltage” in the Select Component parameter form and click OK.
g. In the analysis form type start and stop voltages as 0 to 1.8 respectively.
h. Check the enable button and then click Apply.
Vout, input net (wire) vin of the example. Press ESC with the cursor in the schematic
after selecting it.
6. Now, go to simulationNetlist and run in the ADE window to start the simulation or
CREATING LAYOUT VIEW OF Inverter

form appears.
3. Check the inverter. Viewname (layout)


6. Re arrange the components within the PR- Boundary

the horizontal and vertical line by using the key ‘s’ to stretch the line, it can be
stretch either in horizontal or vertical direction at a time)
8. After keeping the pmos and nmos in the boundary, re arrange the input pins, output
pins, vdd and vss.(optionl)

window will appear now. .(optionl)
horizontal direction. Now click place as schematic in the same window, then click ok.
.(optionl)
Instead of above step follow the below
Note; In new version, in the schematic L editing, go to properties of pmos/nmos

device and change the body tie type as integrated/detached based on your design.
routed successfully
(Note: In the LVS debug form you can find the details of mismatches and you need
to correct all those mismatches and Re-run the LVS till you will be able to match the
completed successfully.
parasitic.
28. Now, go to library mangerFileNewCellview
template.
35. From the library manager open “inverter_test” config view. Open configuration or
top Cellview form appears.
36. In the form, turn on the both cyclic buttons to YES and click ok. The inverter_test
schematic and inverter_test config window appears. Notice the window
banner of schematic also states config: “VLSI_LAB” inverter_test config
EXPERIMENT No: 2
A SINGLE STAGE CMOS DIFFERENTIAL AMPLIFIER
Aim:
Design a single stage CMOS differential amplifier with given specifications, completing the
design flow mentioned below:
i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
Operation:
Procedure:

cd Cadence/cadence_ms_labs_613
csh
source cshrc
virtuoso
field and click ok.
library column.
Cell : differential_amplifier
View : Schematic
Type : schematic
Gpdk180 nmos/Symbol Model Name=nmos1(NM0, NM1);

(or) spectre W=3u ; L=1u;
Gpdk180 nmos/Symbol Model Name=nmos1(NM2, NM3);

(or) spectre W=4.5u ; L=1u;
Gpdk180 Pmos/Symbol Model Name=pmos1(PM0, PM1);

(or) spectre W=15u ; L=1u;

Pin Names Direction
Idc, Vin1, Vin2 Input
Vout Output
Vdd, vss Input
23. In menu bar, go to createwire (narrow) (or) press ‘w’ in keyboard (or) wire (narrow) icon in
SYMBOL GENERATION
30. In the Schematic window, go to menu bar, CreateCellviewFrom Cell View.
Left pin: vin1 vin2 Idc

Right pin: vout
Top pin: vdd
Bottom pin: vss
FileNewCellview (Note: select your “VLSI_LAB” in the library column before create
Cellview)

Cell: differential_amplifier_test
View: schematic
differential_amplifier_test design appears.
differential_test_test schematic.
Library Cell name View Properties/comments

Name name
VLSI_LAB Differential_amplifier Symbol Select the instance of your symbol
analogLib Vsin Symbol Define specifications as AC magnitude=1,

Amplitude=5m, Frequency=1K, offset
Voltage=0.
analogLib Vdc(vdd& vss), gnd Symbol Vdc=2.5 for vdd, vdc=-2.5 for vss
analogLib Idc Symbol Dc current=30u.
no power)
circuit.
to save the design.
1. In the differential_amplifier_test schematic window, go to LaunchADE L (Note: The

Virtuoso Analog Design Environment (ADE) simulation window appears).
Transient analysis:
a.In the analysis section select tran

b. set the stop time as 5m
DC Analysis:

e. Select the input signal Vsin in the test schematic window.
f. In the analysis form type start and stop voltages as -5 to 5 respectively.
g. Check the enable button and then click Apply.
AC Analysis:
a. In the Analysis section, select ac.

b. In the AC analysis section, turn on Frequency.
c. In the sweep range section select start and stop frequencies as 150 to 100M.
d. Select points per decade as 20.
e. Check the enable button and then click Apply.
Click ok in the choosing analysis form.
Vout, input net (wire) vin1 &vin2 of the differential_amplifier_test. Press ESC with the
cursor in the schematic after selecting it.
6. Now, go to simulationNetlist and Run in the ADE window to start the simulation or
CREATING LAYOUT VIEW OF Differential_amplifier
form appears.
3. Check the differential_amplifier. Viewname (layout)



window will appear now.
routed successfully
parasitic.
28. Now, go to library mangerFileNewcellview
template.
35. From the library manager open “differential_amplifier_test” config view. Open
configuration or top cellview form appears.
36. In the form, turn on the both cyclic buttons to YES and click ok.The
differential_amplifier_test schematic and differential_amplifier_test config
window appears. Notice the window banner of schematic also states config:
“VLSI_LAB” differential_amplifier_test config
EXPERIMENT No: 3
COMMON SOURCE AMPLIFIER
Aim:
Design the common source amplifier with given specifications, completing the design flow
mentioned below:
i) DC Analysis
ii) AC Analysis
c. Check for LVS
Operation:
Procedure:

csh
Source cshrc
Virtuoso
field and click ok.
library column.
Cell : common_source
View : Schematic
Type : schematic
Gpdk180 pmos/Symbol Model Name=pmos1; W=50u ; L=1u;

(or) spectre
Gpdk180 nmos/Symbol Model Name=nmos1; W=10u ; L=1u;

(or) spectre
Pin Names Direction
Vin, vbias Input
Vout Output
Vdd, vss input
SYMBOL GENERATION
Left pin: vin

Right pin: vout
Top pin: vdd
Bottom pin: vss vbias

Cellview)

Cell: common_source_test
View: schematic
common_source_test design appears.
common_source_test schematic.

Name name
VLSI_LAB Common_source Symbol Select the instance of your symbol
analogLib Vsin Symbol Define specifications as AC magnitude=1, DC

voltage=0, Amplitude=5m, Frequency=1K,
offset Voltage=0.
analogLib Vdc(vdd& vss), Symbol Vdc=2.5 for vdd, vdc=-2.5 for vss
gnd
analogLib Vdc (vbias) Symbol Vdc=2.5
no power)
circuit.
to save the design.
1. In the common_source_test schematic window, go to LaunchADE L (Note: The

Transient analysis:

DC Analysis:

AC Analysis:

Vout, input vin of the common_source_test. Press ESC with the cursor in the schematic
after selecting it.
CREATING LAYOUT VIEW OF common_source
form appears.
3. Check the common_source. Viewname (layout)



routed successfully
parasitic.
template.
35. From the library manager open “common_source_test” config view. Open
configuration or top Cellview form appears.
36. In the form, turn on the both cyclic buttons to YES and click ok. The
common_source_test schematic and common_source_test config window
appears. Notice the window banner of schematic also states config:
“VLSI_LAB” common_source_test config
\
EXPERIMENT No: 4
COMMON DRAIN AMPLIFIER
Aim:
Design the common drain amplifier with given specifications, completing the design flow
mentioned below:
i) DC Analysis
ii) AC Analysis
c. Check for LVS
Operation:
Procedure:

csh
Source cshrc
Virtuoso
field and click ok.
library column.
Cell : common_drain
View : Schematic
Type : schematic

(or) spectre

(or) spectre
Pin Names Direction
Vin, vbias Input
Vout Output
Vdd, vss input

SYMBOL GENERATION
Left pin: vin

Right pin: vout
Top pin: vdd
Bottom pin: vss vbias
Cellview)

Cell: common_drain_test
View: schematic
common_drain_test design appears.
common_drain_test schematic.

Name name
VLSI_LAB Common_drain Symbol Select the instance of your symbol

voltage=0, Amplitude=5m, Frequency=1K,
offset Voltage=0.
analogLib Vdc(vdd& vss), Symbol Vdc=2.5 for vdd, vdc=-2.5 for vss
gnd
analogLib Vdc (vbias) Symbol Vdc=2.5
no power)
circuit.
to save the design.
1. In the common_drain_test schematic window, go to LaunchADE L (Note: The

3. Now setup for the various analyses (e.g, transient analysis, DC, AC )
Transient analysis:

DC Analysis:

AC Analysis:

Vout, input vin of the common_source_test. Press ESC with the cursor in the schematic
after selecting it.
CREATING LAYOUT VIEW OF common_Drain
form appears.
3. Check the common_drain. Viewname (layout)



routed successfully
parasitic.
template.
35. From the library manager open “common_drain_test” config view. Open
configuration or top Cellview form appears.
36. In the form, turn on the both cyclic buttons to YES and click ok. The
common_drain_test schematic and common_drain_test config window
appears. Notice the window banner of schematic also states config:
“VLSI_LAB” common_drain_test config
EXPERIMENT No: 4
TWO STAGE OPERATIONAL AMPLIFIER
Aim:
Design an op-amp with given specification* using given differential amplifier & Common
source amplifier in library** and completing the design flow mentioned below:
i) DC Analysis
ii). AC Analysis
c. Check for LVS
Operation:
Procedure:

csh
Source cshrc
Virtuoso
field and click ok.
library column.
Cell : op-amp
View : Schematic
Type : schematic
VLSI_LAB Differential_amplifier symbol
VLSI_LAB Common_source Symbol

Pin Names Direction
Vinv, Vnoninv, Idc Input
Vout Output
Vdd, vss input
SYMBOL GENERATION
Left pin: Vinv Vnoninv

Right pin: vout
Top pin: vdd Idc
Bottom pin: vss
Cellview)

Cell: op-amp_test
View: schematic
op-amp_test design appears.
37. Using the components list and properties/comments in this table. Build the op-
amp_test schematic.

Name name
VLSI_LAB Op-amp Symbol Select the instance of your symbol

voltage=0, Amplitude=5u, Frequency=1K, offset
Voltage=0.
analogLib Vdc(vdd& Symbol Vdc=2.5 for vdd, vdc=-2.5 for vss

vss), gnd
no power)
circuit.
to save the design.
1. In the Op-amp_test schematic window, go to LaunchADE L (Note: The Virtuoso

Transient analysis:

DC Analysis:

AC Analysis:

Vout, input Vinv & Vnoninv of the op-amp_test. Press ESC with the cursor in the
schematic after selecting it.
CREATING LAYOUT VIEW OF Op-Amp
form appears.
3. Check the Op-amp. Viewname (layout)



routed successfully
parasitic.
template.
35. From the library manager open “Op-amp_test” config view. Open configuration or
36. In the form, turn on the both cyclic buttons to YES and click ok. The Op-amp_test
schematic and Op-amp_test config window appears. Notice the window
banner of schematic also states config: “VLSI_LAB” Op-amp_test config
EXPERIMENT No: 5
4 – BIT R-2R BASED DAC
Aim:
Design a 4 bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
i) DC Analysis
ii). AC Analysis
c. Check for LVS
Operation:
An R-2R Ladder is a simple and inexpensive way to perform digital-to-analog conversion,

using repetitive arrangements of precision resistor networks in a ladder-like configuration. A
string resistor ladder implements the non-repetitive reference network.
Network or circuit composed of a sequence of L networks connected in tandem. Circuit used

in digital to analog converters.
R-2R resistor ladder network (digital to analog conversion, or DAC). A basic R-2R resistor
ladder network is shown in Figure 1. Bit4 MSB (most significant bit) to Bit0 LSB (least
significant bit) are driven from digital logic gates. Ideally, the bits are switched between 0
volts (digital 0) and Vref (digital 1).
The R-2R network causes the digital bits to be weighted in their contribution to the output
voltage Vout. In this circuit 5 bits are shown, giving 32 possible outputs. Depending on
which bits are set to 1 and which to 0 the output voltage (out) will be a stepped value between
0 volts and (Vref minus the value of the minimum step, Bit0).
The actual value of Vref (and 0 volts) will depend on the type (technology) of the digital
logic gates used to drive Bit4-0.
For a digital value VAL, of a R-2R DAC of N bits of 0 V/Vref, the output voltage Vout is:
Vout = Vref × VAL / 2N
In the example shown, N = 5 and hence 2N = 32. With Vref = 3.3 V (typical CMOS logic 1
voltage), Vout will vary between 00000, VAL = 0 and 11111, VAL = 31.
Minimum (single step) VAL = 1, we have
Vout = 3.3 × 1 / 32 = 0.1 volts
Maximum output (11111 VAL = 31, we have
Vout = 3.3 × 31 / 25 = 3.2 volts
The R-2R ladder is inexpensive and relatively easy to manufacture since only two resistor
values are required (or 1, if R is made by placing a pair of 2R in parallel, or if 2R is made by
placing a pair of R in series). It is fast and has fixed output impedance R.
The R-2R ladder operates as a string of current dividers whose output accuracy is solely
dependent on how well each resistor is matched to the others. Small inaccuracies in the
higher significant bit resistors can entirely overwhelm the contribution of the less significant
bits.
Procedure:

csh
Source cshrc
Virtuoso
field and click ok.
library column.
Cell : R-2R-DAC
View : Schematic
Type : schematic
VLSI_LAB Op-amp symbol
Gpdk180 Polyres(spectre/symbol) R=2k
Gpdk180 Polyres R = 1k
(spectre/symbol)
Pin Names Direction
D0, D1, D2, D3 Input
Vout Output
Vdd, vss, Idc input
SYMBOL GENERATION
Left pin: Idc vdd vss

Right pin: vout
Top pin: D0 D1 D2 D3
Bottom pin:

Cellview)

Cell: R-2R-DAC_test
View: schematic
R-2R-DAC_test design appears.
37. Using the components list and properties/comments in this table. Build the R-2R-
DAC_test schematic.

Name name
VLSI_LAB R-2R-DAC Symbol Select the instance of your symbol
analogLib Vpulse Symbol For V0:V1=0, V2=2, Pulse width=5n, Period=10n

For V1:V1=0, V2=2, Pulse width=10n, Period=20n
analogLib Vdc(vdd& Symbol Vdc=2 for vdd, vdc=-2for vss

vss), gnd
no power)
circuit.
to save the design.
1. In the R-2R-DAC_test schematic window, go to LaunchADE L (Note: The Virtuoso

Transient analysis:

b. set the stop time as 300n

Vout, input Vinv & Vnoninv of the op-amp_test. Press ESC with the cursor in the
schematic after selecting it.
CREATING LAYOUT VIEW OF Op-Amp

form appears.
43. Check the Op-amp. Viewname (layout)

routed successfully
parasitic.
template.
75. From the library manager open “R-2R-DAC_test” config view. Open configuration or
76. In the form, turn on the both cyclic buttons to YES and click ok. The R-2R-DAC_test
schematic and R-2R-DAC_test config window appears. Notice the window
banner of schematic also states config: “VLSI_LAB” R-2R-DAC_test config
EXPERIMENT No: 6
SUCCESSIVE APPROXIMATION REGISTAR ADC (SAR-ADC)
Aim:
For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and
verify the functionality by completing ASIC Design FLOW.
Operation:
The basic algorithm used in the successive-approximation ADC conversion process can be
traced back to the 1500s. It is related to the solution of a useful mathematical puzzle—the
determination of an unknown weight by a minimal sequence of weighing operations
(Reference 1). In this problem, as stated, the object is to determine the least number of
weights which would serve to weigh an integral number of pounds from 1 lb to 40 lb using a
balance scale. One solution put forth by the mathematician Tartaglia in 1556, was to use the
binary series of weights 1 lb, 2 lb, 4 lb, 8 lb, 16 lb, and 32 lb (or 20, 21, 22, 23, 24, and 25). The
proposed weighing algorithm is the same one that is used in modern successive-
approximation ADCs. (It should be noted that this solution will actually measure unknown
weights up to 63 lb (26 – 1) rather than 40 lb as stated in the problem).* The binary algorithm,
using a balance scale, is shown in Figure 4 with an unknown weight of 45 lbs.
*Note that if ternary (base-3: 1,0,–1) logic is permitted, the problem can be solved in four
steps, with weights of 1, 3, 9, and 27 lbs applied on either side of the balance. Indeed, 40 lbs
is then maximum with these weights.
SAMBHRAM INSTITUTE OF TECHHNOLOGY
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINNERING
VLSI LAB – 15ECL77
VIVA VOICE QUESTIONS
1. What is threshold voltage?
2. What is the range of threshold voltage for PMOS & NMOS?
3. What is DC, Tran, AC analysis?
4. What is the advantage in transmission gate over nmos &pmos?
5. What is the demerit in transmission gate?
6. What is pass transistor?
7. What is common source amplifier?
8. What is common drain amplifier?
9. What are the different regions of operation in CMOS inverter?
10. What is the difference between verilog & vhdl?
11. What is switch level model?
12. What is differential amplifier?
13. What is slew rate?
14. What is CMRR?
15. What is op-amp?
16. What are the ideal conditions for an Op-amp?
17. Give the examples for high speed ADC?
18. Give the example for low speed ADC?
19. Give the example for medium speed ADC?
20. Which ADC will have feed back?
21. What is full scale value for DAC?
22. What Is DNL, INL, offset error, Gain error for ADC & DAC
23. What are the second order effects?
24. What is meant by technology?
25. What is lambda based rule?
26. What is DRC & LVS?
27. What is difference between serial adder & parallel adder?
28. What is difference between latch & flip-flop?
29. Conversion of flip flop, D to JK, D to T, etc..,
30. What is stick diagram?
31. What are the different types of contact used in layout?
32. What are the various layers in CMOS?
33. Give the fabrication flow of CMOS, PMOS, NMOS
34. What is the difference between combinational & sequential circuits?
35. Give the operation of serial adder
36. What is aspect ratio?
37. What is scaling?
38. What is submicron?
39. Draw the transfer characteristic curve for cmos inverter, nMOS, and pMOS?
40. What is the use of VLSI?
41. What is the use of HDL?
42. Write the syntax for case?
43. What is the difference between always & initial?
44. What is the difference between reg & wire, parameter & generic?
45. What are the different data types in HDL?
46. What are the operators in HDL?
47. Which operator is having highest priority?
48. What are the tools used in Cadence?
49. What is meant by simulation & elaboration?
50. What is synthesizing?
51. What is sensitivity list?
52. What is the difference between procedure & function, task & function?
53. What is the difference between signal & variable?
54. What is latch-up?
55. How do you avoid latch up?
56. What is rising time, falling time, propagation delay?
57. What is the difference between MOSFET & BJT?
58. Given only two XOR gates one must function as buffer and another as inverter.
59. What is ASIC & FPGA?
60. What is setup & Hold time?
61. What is delta simulation time?
62. What is semi custom &full custom design?
63. What are the fast adders?

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DEPARTMENT OF ELECTRONICS AND COMMUNICTION ENGINEERING

M.S.PALYA, BANGALORE – 560097.

VLSI LAB MANUAL

Professor, Department of ECE

Analog Design Digital Design Analog and Mixed

VLSI LAB MANUAL Page 2 of 69

Digital design & Analog Design

NO.OF PRACTICAL HRS/WEEK: 03 EXAM HOURS: 03

TOTAL NO.OF PRACTICAL HRS: 42 EXAM MARKS: 60

ASIC-DIGITAL DESIGN FLOW

(iii). Transmission Gate

(IV). Basic/Universal gates

(vi). Serial & Parallel adder

(vii). 4-bit counter [synchronous and Asynchronous counter]

(viii).Successive approximation registers [SAR]

*An approximation constraint should be given

* Appropriate specification should be given

1. In the desktop, right click and go to terminal window

4. nclaunch window will open now..

Here it shows the Module

11.Now go to tools click simulate

Click the Run

RTL Compiler procedure:

set_attr lib_search_path /root/Cadence/rclabs/library  this is for to set up the library path

read_hdl {fulladdder.v parallel_adder.v}

nmos n1(out , data , control ) ; => nmos na (drain, source, gate)

cmos c1(out , data , ncontrol , pcontrol ) ;

tran t1( inout1, inout2 ) ;

The symbols for these switches are shown below.

Basic Design Example

CMOS NOR Gate Design

module my_nor(out, A, B);

my_nor n1(OUT, A, B);

The output of the simulation is shown below.

According truth table, when input contains 1, then output is 0.

1-Bit Full Adder Design

module my_not(out, in);

//Instantiate the CMOS switches cmos

//Define a CMOS Adder

//Define instantiate CMOS switches cmos

//Define stimulus module

Simulation result is shown below.

According to mathematical equation, we can get waveform is shown below.

module my_mux (out, s, i0, i1);

cmos (out, i0, sbar, s);

We will check 2 to 1 multiplexer as shown below.

reg S, I0, I1;

$monitor($time," OUT= %b, S= %b I0= %b, I1=

The simulation is used to waveform check 2 to 1 multiplexer correctly.

module dff ( q, qbar, d, clk);

When clk =1, output is changed.

Verilog code (data flow model):

Verilog code (switch level model):

Test bench code:

Verilog code (data flow model):

module buffer ( out, in);

Verilog code (switch level model):

module buffer (out,in);

Test bench code:

Simulation output waveform:

A transmission gate, or analog switch, is defined as an electronic element that will

Verilog code(data flow model):

Verilog code(data flow model):

Simulation output waveform: