VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY

INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

DIGITAL LOGIC DESIGN LABORATORY

COURSE ID: IT099IU

INSTRUCTOR: M. ENG NGUYEN HOANG AN

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Lab 2 Reviews
In the second Lab, you were studying:
 The operation of combinational logic circuits with their respective truth table
and circuit designs.
 The operation of those combinational ICs such as: 4-bit comparator, 8-bit
comparator, parity generator and checker.
 The practice of building the above circuits using SimullDE program.
 Practice building up the above circuit using Laboratory equipments.
Reminding
 Submit your Lab report and simulation files for Lab 2 on Blackboard.
 Late submission will be receiving penalty of 20% per day of late submission.
 VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY
INTERNATIONAL UNIVERSITY
SCHOOL OF ELECTRICAL ENGINEERING

LAB 3
MSI COMBINATIONAL LOGIC (cont.)
LABORATORY

INSTRUCTOR: M. ENG NGUYEN HOANG AN 3

 II Discussion of Fundamentals
1. Half Adder and Full Adder

a. Half Adder:
 The Half Adder is a type of
combinational logic circuit that adds
two of the 1-bit binary digits. It
generates carry and sum of both the
inputs.

 But you cannot forward the carry that

you obtain in one addition into another
addition. It is because of the absence
of any logic gate to process it. Thus, Figure 1: Truth table of a Half - Adder
it’s called the Half Adder circuit.
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 II Discussion of Fundamentals
1. Half Adder and Full Adder

b. Full Adder:
 The Full Adder is also a type of
combinational logic that adds three of the
1-bit binary digits for performing an
addition operation. It generates a sum of
all three inputs along with a carry value.

 Just like the Half Adder, the Full Ladder is

a combinational type of logic circuit-
meaning, it has no storage element. But it
has additional logic gates. Thus, it adds
the previous carry to generate the
complete output. Thus, it’s called the Full Figure 2: Truth table of a Full - Adder
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Adder circuit.
Parameter Half Adder Full Adder
Basics The Half Adder is a type of The Full Adder is also a type of
combinational logic circuit that adds combinational logic that adds three of
two of the 1-bit binary digits. It the 1-bit binary digits for performing
generates carry and sum of both the an addition operation. It generates a
inputs. sum of all three inputs along with a
carry value.

Adding the Previous Carry The Half Adder does not add the carry The Full Adder, along with its current
obtained from the previous addition inputs A and B, also adds the previous
to the next one. carry.

Hardware Architecture A Half Adder consists of only one AND A Full Adder consists of one OR gate
gate and EX-OR gate. and two EX-OR and AND gates.

Total Inputs There are two inputs in a Half Adder- There are a total of three inputs in a
A and B. Full Adder- A. B. C-in.

Usage The Half Adder is good for digital The Full Adder comes into play in
measuring devices, computers, various digital processors, the addition
calculators, and many more. of multiple bits, and many more.
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 II Discussion of Fundamentals
2. 8-to-3 Priority Encoder (Interrupt sorter) – 74HC148

 The Priority Encoder solves the problems of having multiple inputs by allocating a priority
level to each input. The priority encoders output corresponds to the currently active input
which has the highest priority, all other inputs with a lower priority will be ignored.
Input Output
EI D0 D1 D2 D3 D4 D5 D6 D7 GS A2 A1 A0 E0
1 X X X X X X X X          
0 1 1 1 1 1 1 1 1          
0 X X X X X X X 0          
0 X X X X X X 0 1          
0 X X X X X 0 1 1          
0 X X X X 0 1 1 1          
0 X X X 0 1 1 1 1          
0 X X 0 1 1 1 1 1           Figure 3: Truth table of 8-to-3
0 X 0 1 1 1 1 1 1          
0 0 1 1 1 1 1 1 1           bit Encoder 74LS148 7
 II Discussion of Fundamentals
2. 8-to-3 Priority Encoder (Interrupt sorter) – 74HC148

 EI (Active low): when it is de-asserted, all outputs

are driven to logic ‘1', and when it is asserted, the
encoder outputs can be driven by the inputs
 EO: can be used to distinguish between no inputs
asserted and the 0th input asserted.
 GS: is asserted whenever EIN is asserted along
with any other input signal, and it is used to form
Figure 4: Encoder 8-to-3
the most significant bit of the encoded output IC 74LS148
data element 8
 II Discussion of Fundamentals
3. 2-to-4 Decoder/Demultiplexer – 74HC139

 The name “Decoder” means to translate

Inputs
or decode coded information from one Outputs
Control Data
format into another, so a digital decoder G B A Y0 Y1 Y2 Y3
0 0 0        
transforms a set of digital input signals
0 0 1        
into an equivalent decimal code at its 0 1 0        
0 1 1        
output. A decoder is a combinational 1 X X        
circuit that converts binary information
Figure 5: Truth table of Decoder
from n input lines to a maximum of 2-to-4 IC 74LS139
unique output lines. 9
 II Discussion of Fundamentals
3. 2-to-4 Decoder/Demultiplexer – 74HC139

 G: is the Enable bin (Active LOW).

 A, B: 2 inputs
 Y0, Y1, Y2, Y3: 4 outputs, in which:
 Y0 = G.A’.B’
 Y1 = G.A.B’
 Y2 = G.A’.B
Figure 6: Decoder 2-to-4
 Y3 = G.A.B
IC 74LS139

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 II Discussion of Fundamentals
3. 3-to-8 Decoder/Demultiplexer – 74HC138
INPUT OUTPUT
E3 E2 E1 C B A Y0 Y1 Y2 Y 3 Y4 Y5 Y6 Y7
1 0 0 0 0 0                
1 0 0 0 0 1                
1 0 0 0 1 0                
1 0 0 0 1 1                
1 0 0 1 0 0                
1 0 0 1 0 1                
1 0 0 1 1 0                
1 0 0 1 1 1                
0 X X X X X                
X 1 X X X X                
X X 1 X X X                

Figure 7: Truth table of Decoder

3-to-8 IC 74LS138 11
 II Discussion of Fundamentals
3. 2-to-4 Decoder/Demultiplexer – 74HC139

 E1, E2 (Active LOW),

E3 (Active HIGH): the
Enable bins.
 A, B, C: 3 inputs
 Y0 to Y7: 8 outputs:
 Y0 = C’.B’.A’  Y4 = C.B’.A’
Figure 7: Decoder 3-to-8
 Y1 = C’.B’.A  Y5 = C.B’.A
IC 74LS138
 Y2 = C’.B.A’  Y6 = C.B.A’
 Y3 = C’.B.A  Y7 = C.B.A 12
3. Lab report

• Use SimullDE Software to conduct the experiment

• Follow the instruction procedure
• Capture the simulation circuits and output waveforms, attach them into the lab report
• Conclude about the experiments
• Submit via Blackboard before the day of the next Lab
• Plagiarism violation: similarity score must be less than 30%.
• Note: Remember to follow the Template for LAB report
• Instruction: Put your simulation files for each problems and the report (PDF format)
in a folder named as:
• DLDLab_Name1st_Name2nd_Lab#
• Then compress as *.rar or *.zip file and submit via Blackboard.

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