Digital Electronic Technology

Lecture 3: Combinational Logic

Jingfei He
Spring 2020
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We Can Now Build Logic Circuits
Now, we understand the workings of the basic logic gates

What is our next step?

Build some of the logic structures that are important

components of the microarchitecture of a computer!

A logic circuit is composed of:

 Inputs functional spec
inputs outputs
 Outputs
timing spec
Functional specification (describes relationship between
inputs and outputs)

Timing specification (describes the delay between inputs

changing and outputs responding)
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Types of Logic Circuits

functional spec
inputs outputs
timing spec

Combinational Logic
 Memoryless
 Outputs are strictly dependent on the combination of input values that are
being applied to circuit right now
 In some books called Combinatorial Logic
Later we will learn: Sequential Logic
 Has memory
Structure stores history  Can ”store” data values
 Outputs are determined by previous (historical) and current values of inputs

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Gate Propagation Delay

Propagation delay is the time for a change on an input

of a gate to propagate to the output.
Delay is usually measured at the 50% point with
respect to the H and L output voltage levels.
High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are
defined with respect to the output, not the input.
An HL input transition causes:
 an LH output transition if the gate inverts and
 an HL output transition if the gate does not invert.

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Propagation Delay (continued)

Propagation delays measured at the midpoint between the L and

H values

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Combinational Logic Circuits

1. Analysis of combination logic circuits

2. Design of combination logic circuits

3. Combinational building blocks

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Analysis of combination logic circuits

1. Obtain the output Boolean functions from a logic diagram

2. Simplify functional formulas using K-maps or Boolean algebra

3. Truth table

4. Describe its function

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Analysis of combination logic circuits
Example 1: Analyze the function of the logical circuit diagram
（ 1 ） Boolean
functions
F  AB • BC • AC
AB
 AB  BC  AC
（ 2 ） Truth table
BC
Truth table
A B C F
0 0 0 0
0 0 1 0 AC
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1 8
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Analysis of combination logic circuits
Example 1: Analyze the function of the logical circuit diagram
（ 3 ） Analysis Truth table
Most of the input variables are 1 A B C F
—— Output F =1; 0 0 0 0
0 0 1 0
0 1 0 0
Most of the input variables are 0 0 1 1 1
—— Output F =0; 1 0 0 0
1 0 1 1
1 1 0 1
Conclusion: a voting circuit. 1 1 1 1

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Analysis of combination logic circuits
Example 2: Analyze the function of the logical circuit diagram

（ 1 ） Boolean G3  B3
functions G  B  B
 2 3 2

G1  B2  B1

G0  B1  B0
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Binary code Gray code
B3B2B1B0 G3 G 2 G 1 G0
G 3  B3 0 0 0 0 0 0 0 0
G  B3  B 2 0 0 0 1 0 0 0 1
 2
 0 0 1 0 0 0 1 1
G1  B 2  B1 0 0 1 1 0 0 1 0

G 0  B1  B0 0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
（ 2 ） Truth table 0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
（ 3 ） Analysis 1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
Binary code to Gray code 1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
conversion circuit. 1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
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Design of combination logic circuits

1. Specification
 Write a specification for the circuit if one is not already
available
2. Formulation
 Derive a truth table or initial Boolean equations that define the
required relationships between the inputs and outputs, if not
in the specification
3. Optimization
 Apply K-map and other optimizations
 Draw a logic diagram for the resulting circuit using ANDs,
ORs, and inverters
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Example 1: Design of half adder

（ 1 ） Truth table Input Output

A B S C
（ 2 ） Output function 0 0 0 0
S  AB  AB  A  B 0 1 1 0
1 0 1 0
C  AB 1 1 0 1

（ 3 ） Logic diagram
（ 4 ） Logic Symbol


CO
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Example 2: Design of Full adder
This type of adder is a little more difficult to implement than a half-adder. The
main difference between a half-adder and a full-adder is that the full-adder has
three inputs and two outputs. The first two inputs are A and B and the third input
is an input carry designated as CIN
Truth table for full adder
Input Output Logic Symbol
Ai Bi Ci Si Ci+1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1 Do it yourself
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Example 3
Input Output
Convert 8421BCD code to the Excess-3 BCD code 8421 BCD Excess-3 BCD
（ 1 ） Truth table B 3 B 2 B1 B0 E 3 E 2 E 1 E0
0 0 0 0 0 0 0 1 1
（ 2 ） K-maps 1 0 0 0 1 0 1 0 0
E3 E2 2 0 0 1 0 0 1 0 1
B1B0 B1B0 3 0 0 1 1 0 1 1 0
B3B2 00 01 11 10 B3B2 00 01 11 10
4 0 1 0 0 0 1 1 1
00 00 1 1 1 5 0 1 0 1 1 0 0 0
01 1 1 1 01 1
6 0 1 1 0 1 0 0 1
11     11     7 0 1 1 1 1 0 1 0
10 1 1   10 1   8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
B1B0 1E 0E
B1B0 10 1 0 1 0 Φ Φ Φ Φ
B3B2 00 01 11 10 B3B2 00 01 11 10 11 1 0 1 1 Φ Φ Φ Φ
00 1 1 00 1 1 12 1 1 0 0 Φ Φ Φ Φ
01 1 1 01 1 1 13 1 1 0 1 Φ Φ Φ Φ
11     11     14 1 1 1 0 Φ Φ Φ Φ
10 1 10 1 15 1 1 1 1 Φ Φ Φ Φ
    15
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Example 3

（ 2 ） K-maps

（ 3 ） Expression
E3 B1B0
E2
B1B0
B3B2 00 01 11 10 B3B2 00 01 11 10
00 00
E 3  B3  B 2 B0  B2 B1 01 01 1
1 1 1
1 1 1
E 2  B2 B0  B2 B1  B2 B1 B0 11     11    
10 1 1   10 1  

E1  B1 B0  B1B0 B1B0
E1 B1B0 E0
B3B2 00 01 11 10 B3B2 00 01 11 10
00 1 00 1
E 0  B0 1 1
01 1 1 01 1 1
11     11    
10 1   10 1  
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Example 3
E3  B3  B2 B0  B2 B1
E2  B 2 B0  B 2 B1  B2 B1 B 0
（ 3 ） Expression
E1  B1 B 0  B1B0
E0  B 0
Expression
How to implement this circuit with a NAND gate?
transformation

E3  B3  B2 B0  B2 B1  B 3  B2 B 0  B2 B1

E2  B 2 B0  B 2 B1  B2 B1 B 0  B 2 B0  B 2 B1  B2 B1 B 0

E1  B1 B 0  B1B0  B1 B 0  B1B0
E0  B 0
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Example 3

（ 4 ）电路图 E  B 3  B B  B B
3 2 0 2 1

E2  B 2 B0  B 2 B1  B2 B1 B 0
Excess-3 BCD
E1  B1 B 0  B B
1 0

E0  B 0

8421BCD

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Combinational Building Blocks

Combinational logic is often grouped into larger building blocks to build more
complex systems

Hides the unnecessary gate-level details to emphasize the function of the

building block

We now look at:

 Half adder & Full adder
 Encoders & Decoders
 Multiplexers & Demultiplexers
 PLA (Programmable Logic Array)

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Binary Adders

Addition is important function in computer system

What does an adder have to do?
 Add binary digits
 Generate carry if necessary
 Consider carry from previous digit
Binary adders operate bit-wise
 A 16-bit adder uses 16 one-bit adders
Binary adders come in two flavors
 Half adder : adds two bits and generate result and carry
 Full adder : also considers carry input
 Two half adders make one full adder
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Binary Half Adder

Specification:
 Design a circuit that adds two bits and generates the sum and a carry
Outputs:
 Two inputs: x, y
 Two output: S (sum), C (carry)
 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10

The S output represents the least significant bit of the sum.

The C output represents the most significant bit of the sum or (a carry).

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Implementation of Half Adder

 the flexibility for implementation  S = x'y+xy'

 S=x  y  C = xy
 S = (x+y)(x'+y')
 S' = xy+x'y'
 S = (C+x'y')'
X Half S
Y C
 C = xy = (x'+y')' Adder

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Full-Adder
Specification:
 A combinational circuit that forms the arit
hmetic sum of three bits and generates a
sum and a carry
Inputs:
 Three inputs: x,y,z
 Two outputs: S, C
Truth table:

X Y

C
Full Z
Adder
S

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Implementation of Full Adder

S=x’y’z+ x’yz’ + xyz’ + xyz C= xy + xz + yz

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Alternative Implementation of Full Adder

S = z (x  y)= z’(xy’+x’y) + z(xy’+x’y)’

= z’(xy’+x’y) + z(xy+x’y’)
=xy’z’+x’yz’+ xyz +x’y’z
C = x y + (x  y) z
=z(xy’ + x’y) + xy= xy’z+ x’yz+ xy
= xy + xz + yz

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Binary Adder

A binary adder is a digital circuit that produces the arithmetic sum

of two binary numbers.
A binary adder can be implemented using multiple full adders (FA)
.

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Example: Add 2 binary numbers

A = 1011
B = 0011

Subscript i: 3 2 1 0
Input carry 0 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi
Sum 1 1 1 0 Si
Carry 0 0 1 1 Ci+1

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Example:4-bit binary adder

4-bit Ripple Carry Adder C 1110

A 0101
B 0111
S 1100

Classical example of standard components

 Would require truth table with 29 entries!

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Carry Propagation

 In any combinational circuit, the signal must propagate through the gates before the correct o
utput is available in the output terminals.
 Total propagation time = the propagation delay of a typical gateX the number of gate levels
 The longest propagation delay time in a binary adder is the time it takes the carry to propagat
e through the full adders. This is because each bit of the sum output depends on the value of
the input carry. This makes the binary adder very slow.

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n-bit Carry Ripple Adders

In the expression of the sum Cj must be generated by the full adder at the
lower position j-1.
The propagation delay in each full adder to produce the carry is equal to
two gate delays = 2
Since the generation of the sum requires the propagation of the carry from
the lowest position to the highest position ,the total propagation delay of
the adder is approximately:
Total Propagation delay = 2n

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4-bit Carry Ripple Adder
Inputs to be added

Adds two 4-bit numbers: X3 X2 X1 X0 Y3 Y2 Y1 Y0

X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0 4-bit
C4 Cout Adder Cin C0 =0
producing the sum S = S3 S2 S1 S0,
Cout = C4 from the most significant
position j=3 S 3 S2 S 1 S 0
Total Propagation delay = 2n = 8
Sum Output
or 8 gate delays
Data inputs to be added

X3 Y3 X2 Y2 X1 Y1 X0 Y0

Full
C4 Cout Cin C3 Cout Full Cin C2 Cout Full Cin C1
Cout
Full
C C0 =0
Adder Adder Adder Adder in

S3 S2 S1 S0
Sum output
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Larger Adders
 Example: 16-bit adder using 4, 4-bit adders
 Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a
16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant
position.
Data inputs to be added X (X0 to X15) , Y (Y0 to Y15)
X3 X2 X1 X0 Y3 Y2 Y1 Y0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 X3 X2 X1 X0 Y3 Y2 Y1 Y0

C16 4-bit C C12 4-bit C C8 4-bit C C4 4-bit C

Cout C Cout Cout C0=0
Adder in out
Adder in Adder in Adder in

S 3 S 2 S1 S 0 S 3 S 2 S1 S 0 S 3 S 2 S1 S0 S 3 S 2 S1 S 0

Sum output S (S0 to S15)

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder

= 4 x 2 n = 4 x 8 = 32 
or 32 gate delays

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Binary Multiplication

Multiplication is achieved by adding a list of shifted multiplicands

according to the digits of the multiplier.
Ex. (unsigned)
11 1011 multiplicand (4 bits)
X 13 X 1101 multiplier (4 bits)
-------- -------------------
33 1011
11 0000
______ 1011
143 1011
---------------------
10001111 Product (8 bits)

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Binary Multiplier

Partial products – AND operations

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Decoders
Decoder : selects one output bas
ed on binary input
 Converts n-bit code into 2n outputs, o
nly one being active for any combinat
ion of inputs
 Selects output x if input is binary repr
esentation of x
Applications
 Binary-to-octal decoder
 Memory address selection
 Selection of any kind
 Can be used to construct arbitrary lo
gic function

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Decoder Example: Seven-Segment Decoders
/Bl D C B A a b c d e f g
A seven segment decoder 0 x x x x 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1 1 1 1 0
has 4-bit BCD input and 1 0 0 0 1 0 1 1 0 0 0 0
1 0 0 1 0 1 1 0 1 1 0 1
the seven segment display 1 0 0 1 1 1 1 1 1 0 0 1
1 0 1 0 0 0 1 1 0 0 1 1
code as its output: 1 0 1 0 1 1 0 1 1 0 1 1
In minimizing the circuits 1 0 1 1 0 0 0 1 1 1 1 1

-- don’t care inputs --

1 0 1 1 1 1 1 1 0 0 0 0
for the segment outputs all 1 1 0 0 0 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 0 0 1 1
non-decimal input 1 1 0 1 0 0 0 0 1 1 0 1
1 1 0 1 1 0 0 1 1 0 0 1
combinations 1 1 1 0 0 0 1 0 0 0 1 1
(1010, 1011, 1100,1101, 1110, 1 1 1 0 1 1 0 0 1 0 1 1
1 1 1 1 0 0 0 0 1 1 1 1
1111) are taken as don’t-cares 1 1 1 1 1 0 0 0 0 0 0 0

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Truth Table

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3 to 8 Decoder Circuit
When is output 0 chosen?
 If x’ y’ z’
When is output 1 chosen?
 If x’ y’ z
… and so on …
Circuit for line decoder
 Sequence of minterms
 Combine variables to minterms

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Advanced Decoder

Additional feature: Enable input

 Circuit generates output only if Enable is selected (E=0)
 If disabled (E=1), no output line is picked
Example:
 2-to-4 line decoder with Enable
 NAND implementation

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2-to-4 Line Decoder with Enable Input

Truth table for NAND decoder

Complemented outputs and Enable

If active low outputs, then use NAND gates!

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Larger Decoders
 Enable bit can be used for buildin
g larger decoders
 w = 0 activates upper decoder (bit
s D7…D0)
 w = 1 activates lower decoder (bit
s D15…D8)
 Effect: w adds one input bit
 n=3→4
 Can we use new decoder to get
a 5-to-32 line decoder?
 No!
 4-to-16 line decoder does not hav
e Enable

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Implementing Functions Using Decoders
Example: Full adder
S(x, y, z) =  (1,2,4,7)
C(x, y, z) =  (3,5,6,7)

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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Standard MSI Binary Decoders Example
74138 (3-to-8 decoder)

(a) Logic circuit.

(b) Package pin configuration.
(c) Function table.

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Decoders/Demultiplexers

Decoder: single data input, n control inputs, 2n

outputs 3:8 Decoder:
O0 = E  S2  S1  S0
control inputs (called select S) represent Binary
index of output to which the input is connected O1 = E  S2  S1  S0
data input usually called "enable" (E or EN) O2 = E  S2  S1  S0

2:4 Decoder:
1:2 Decoder:
O0 = E  S; O1 = E  S
O3 = E  S2  S1  S0
O4 = E  S2  S1  S0
O0 = E  S1  S0
O5 = E  S2  S1  S0
O1 = E  S1  S0
O6 = E  S2  S1  S0
O2 = E  S1  S0
O7 = E  S2  S1  S0
O3 = E  S1  S0

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Decoders Application

Ex ： Implementing logic functionsF  AB  BC  AC

with decoders and gates
F  A' BC  AB ' C  ABC ' ABC  m3  m5  m6  m7
 (m3 ' m5 ' m6 ' m7 ' )'
BIN/OCT F 0
'
A0 0
C 0 F 1
'
A1 0 1
B 1 G
7
F 2
'
2
A A2 2 F 3
'
3
F 4
'
S 3
'
& EN
4
F 5
' &
S ' 5 F
2
F 6
'
S 6
F
1
'
1 7
7

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Decoders/Demultiplexers

E E
Output0 Output0
Select Select
Output1 Output1

1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable
Alternative Implementations
E E
Output0 Output0

Output1 Output1

Output2 Output2

Output3 Output3

Select0 Select1 Select0 Select1

2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable
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Enabling

Enable signals permit or prevent something from

occurring (a control signal)
 State is described as either:
Active - ON or Enabled
Passive - OFF or Disabled
 Polarity of control state can be:
Active high - schematic symbol doesn’t have bubble
Active low - Schematic symbol has bubble

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Encoders
Encoder: translates 2n input lines into n output lines
 Input: 2n lines
 Output: n bits
 Output is binary coding of input that is 1
Truth table (n=3):

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8-to-3 binary encoder
For an 8-to-3 binary encoder with inputs D0-D7 the logic expressions of the
outputs X,Y,Z are:
Z = D 1 + D 3 + D5 + D7
Y = D 2 + D 3 + D6 + D7
X = D4 + D5 + D6 +D7
 At any one time, only one input line has a value of 1.
D0
D1 X = D4 + D5 + D6 + D7
D2
D3 Y = D2 + D3 + D6 + D7

D4
D5
D6 Z = D1 + D3 + D5 + D7
D7
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Priority Encoder
 Priority encoder
 Like encoder, with additional functionality:
if multiple inputs are 1, give priority to one of the bits
 Example: 4-to-1 priority encoder with priority given to one bit
 Which bit has highest priority?
 D3

Valid bit

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K-Map of a Priority Encoder

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4-input Priority Encoder

x = D2 + D3
y = D3 + D1 D2’
V = D0 + D1 + D2 + D3

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Multiplexers
select binary information from one of many input lines and direct it to a single
output line
2n input lines, n selection lines and one output line
e.g.: 2-to-1-line multiplexer

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4-to-1-line multiplexer

Inputs Inputs
I0 0 I0
I1 4:1
1 MUX I1
I2 Y Output I2 mux Y
2
I3
3S S I3
1 0

select S1 S0
select

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Alternative Circuit for 4-to-1-line multiplexer

I0

I1
Y
I2

I3

0 1 2 3
2-to-4
Decoder

S1 S0

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Larger Multiplexers

Larger multiplexers can be constructed from smaller ones.

An 8-to-1 multiplexer can be constructed from smaller multiplexers as
shown:

I0
S2 S1 S0 Y
I1 4:1
I2 MUX 0 0 0 I0
0 0 1 I1
I3
2:1 0 1 0 I2
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX 1 1 0 I6
S2
I7 1 1 1 I7

S1 S0

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Larger Multiplexers

A 16-to-1 multiplexer can be constructed from five 4-to-1 multiplexers:

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Multiplexer
What if we want to select m
ore than one bit?
Example: choose one of tw
o 4-bit numbers
“Quadruple2-to-1 line multi
plexer”
Select chooses input
Enable bit sets output to 0 if
1

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Standard MSI Multiplexer Example

74151A 8-to-1 multiplexer.

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Boolean function implementation
MUX: a decoder + an OR gate
2n-to-1 MUX can implement any Boolean function of n input varia
ble
a better solution: implement any Boolean function of n+1 input vari
able
 n of these variables: the selection lines
 the remaining variable: the inputs

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Truth table

S0
4:1MUX S1 S0 F
0
S1 1 0 0 D0 F  S 1 ' S 0 ' D0
D0 0 F  S 1 ' S 0 D1
D1 1
0 1 D1
D2 F  S 1 S 0 ' D2
2 1 0 D2
D3 3 F  S 1 S 0 D3
1 1 D3

F  S 1 ' S 0 ' D0  S 1 ' S 0 D1  S 1 S 0 ' D2  S 1 S 0 D3

3
  mi Di
i 0

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2. 八选一数据选择器

F  S 2 ' S 1 ' S 0 ' D0  S 2 ' S 1 ' S 0 D1  S 2 ' S 1 S 0 ' D2  S 2 ' S 1 S 0 D3  S 2 S 1 ' S 0 ' D4
8:1MUX
 S 2 S 1 ' S 0 D5  S 2 S 1 S 0 ' D 6  S 2 S 1 S 0 D 7 S0 0
S1 1
S2 2
D0 0
D1 1 F
D2 2
D3 3
D4 4
D5 5
D6
D7 6
7

F  S 1 ' S 0 ' D0  S 1 ' S 0 D1  S 1 S 0 ' D 2  S 1 S 0 D3

4:1 Mux
7

8:1 Mux 𝐹 = ෍ 𝑚𝑖 𝐷𝑖
𝑖=0
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Example I
 an example: F(A,B,C)=Σ(1,2,6,7)

8:1MUX
Sz 0 0
Sy 1 1
Sx 2 2
D
00 0
D
11 1 F
D
12 2
D
03
3
D
0
4 4
D5
0
5
D
16
D
17
6
7

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Example I
 an example: F(A,B,C)=Σ(1,2,6,7)

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Procedure
Procedure:
 assign an ordering sequence of the input variable
 the rightmost variable (D) will be used for the input lines
 assign the remaining n-1 variables to the selection lines w.r.t. their correspo
nding sequence
 construct the truth table
 consider a pair of consecutive minterms starting from m0
 determine the input lines

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Example II
 an example: F(A,B,C,D)=Σ(1,3,4,11,12,13,14,15)

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Example: a single 74151A 8-to-1 mux
Implement the function F(x1,x2,x3,x4) = (0,1,2,3,4,9,13,14,15) using
a single 74151A 8-to-1 MUX and an inverter.
 We choose the three most significant inputs x1,x2,x3 as mux select lines.
 Construct truth table.
 Determine multiplexer Data input line Di values.

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Example: 4-variable Function Using 8-to-1 mux

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Demultiplexers

Digital switches to connect data from one input source to one of n outputs.
Usually implemented by using n-to-2n binary decoders where the decoder’s
enable line is used for data input of the demultiplexer.

2X4
Select Decoder
s bits b bits lines One of
Demux

One of n outputs
Select four 1-bit
One of n b bits outputs
Data
Data
Sources Input
Input . Enable
selected data (1bit)
.
b bits
1-bit 4-output demultiplexer using
a 2x4 binary decoder.
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1-to-4 Demultiplexer
Outputs

Y0 = D.S1'.S0' S1 So Y0 Y1 Y2 Y3
0 0 D 0 0 0
Y1 = D.S1'.S0
Data D demux
0 1 0 D 0 0
Y2 = D.S1.S0' 1 0 0 0 D 0
1 1 0 0 0 D
Y3 = D.S1.S0

S1 S0
select

Y0 = D.S1'.S0'
2x4
S1 Decoder Y1 = D.S1'.S0
S0 Y2 = D.S1.S0'
E Y3 = D.S1.S0

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Mux-Demux Application Example

This enables sharing a single communication line among a

number of devices.
At any time, only one source and one destination can use
the communication line.

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The Programmable Logic Array (PLA)

The below logic structure is a very common building block for implementing
any collection of logic functions one wishes to
A
X
 An array of AND gates B
followed by an array of OR C
gates Connections
Y

 How do we determine the

number of AND gates? Z
 Remember SOP: the
number of possible minterms
 For an n-input logic function, we need a PLA with 2n n-input AND gates
 How do we determine the number of OR gates? The number
of output columns in the truth table

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The Programmable Logic Array (PLA)
How do we implement a logic function?
 Connect the output of an AND gate to the input of an OR gate if
the corresponding minterm is included in the SOP
 This is a simple programmable A
X
logic B

 Programming a PLA: we C
Y
program the connections from Connections
AND gate outputs to OR gate
inputs to implement a desired Z

logic function

 Have you seen any other type of programmable logic?

 Yes! An FPGA…
 An FPGA uses more advanced structures, learn more in EDA course.
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Implementing a Full Adder Using a PLA
A
X
B

C This input should not be

Y connected to any outputs We do not need
Connections
this output

Z ai
X
bi

ci
ci+1
Truth table of a full adder
ai bi carryi carryi+1 Si
0 0 0 0 0
si
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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Logical (Functional) Completeness

Any logic function we wish to implement could be accomplished with a PLA

 PLA consists of only AND gates, OR gates, and inverters
 We just have to program connections based on SOP of the intended logic function

The set of gates {AND, OR, NOT} is logically complete because we can build
a circuit to carry out the specification of any truth table we wish, without using
any other kind of gate

NAND is also logically complete. So is NOR.

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