Electrical Engineering Department – ITU

EE233L: Digital Logic Design Lab

Course Instructor: Mr Hussnain Riaz Dated: 06 – 09 – 2023

Lab Engineer: Muhammad Kashif Semester: Fall 2023

Batch: BSEE 22

LAB 2: Illustration of Boolean Simplification and its Advantages in

Digital Logic Design

Name Roll Number Lab Marks

Abdullah Maqsood BSEE22057

Checked on: __________________________

Signature: __________________________
 Illustration of Boolean Simplification and its Advantages in Digital
Logic Design
2.1. Introduction
This lab aims to introduce students to the general properties of Boolean algebra. Students will use these properties to
simplify Boolean expressions/functions. Boolean function simplification is required in combinational logic circuits to
reduce the number of gates being used.

2.2. Objectives
This lab will enable students to achieve the following:
 Apply Boolean algebra properties in simplification of Boolean expressions
 Demonstrate the advantage of using Boolean simplification in terms of reduction of circuit components (wires and
gates)
 Design logic circuits that have one of AND and OR gates eliminated using De Morgan’s laws

2.3. Conduct of Lab

1. This lab experiment has to be performed using the logic trainer in Embedded Lab.
1. Bring printout of this lab manual when you come to perform the lab.
2. You can work and get evaluated in groups of two. However, manual submission has to be separate.
3. If there is difficulty in understanding any aspect of the lab, please seek help from the lab engineer or the TA.
4. If a lab task contains an instruction to show working to lab engineer, make sure that the lab engineer evaluates and
marks on your manual for that task. If your manual is unmarked for this task, it can result in marks deduction.
5. Complete the lab within the allocated time. Late submissions will be marked zero.
6. At the end of the lab, submit solved manual to the lab engineer.

2.4. Theory and Background

2.4.1. Boolean algebra properties

Some Boolean algebra properties are listed below:
 A+1=1 (Annulment)
 A+0= A (Identity)
 A .1= A (Identity)
 A .0=0 (Annulment)
 A+ A= A (Redundancy)
 A . A= A (Redundancy)
 A+ AB= A (Redundancy)
 A .( A+ B)= A (Redundancy)
 ( A ) =A (Complement)
 A+ A=1 (Complement)
 A . A=0 (Complement)
 A+ B=B+ A (Commutative)
 A . B=B . A (Commutative)
 ( A+ B )= A . B (De Morgan’s Theorem of OR operation)
 ( A . B)= A +B (De Morgan’s Theorem of AND operation)
 A .(B+C)=A . B+ A . C (Distributive)
 A+ B .C=( A+ B).( A +C) (Distributive)
Boolean expressions can be simplified using the above properties. This simplification brings about the reduction of logic
gates being used to implement a certain function.

2.5. Parts and Equipment

1. Digital logic trainer
2. 7408: Quad 2-input AND gate IC
3. 7432: Quad 2-input OR gate IC
4. 7404: Hex inverter
5. Connecting wires

2.6. Lab Tasks

2.6.1. Task 1: Boolean simplification [Marks: 9]

1. F= A . C+ A . B . C+ A .C
The above Boolean function can be simplified further. However, in order to see the advantage of simplification and
verify its correctness, we will first need to work out the truth table of this function, and then carry out the
simplification and compare the simplified circuit output with the non-simplified one.
2. Complete the following truth table for each term of the non-simplified function F. [2]
Table 2.1: Truth table of F

A B C A.C A.B.C A.C A . C+ A . B . C+ A .C

0 0 0 1 0 0 1
0 0 1 0 0 0 0
0 1 0 1 0 0 1
0 1 1 0 0 0 0
1 0 0 0 0 1 1
1 0 1 0 0 0 0
1 1 0 0 0 1 1
1 1 1 0 1 0 1
3. Draw the logic diagram for the non-simplified function here: [1.5]

4. Now simplify the function F in the space below using Boolean algebra properties. Against each step, mention the
Boolean algebra property that has been used to reach the current step from the previous one. [2.5]

5. Draw the logic diagram for the simplified expression of F: [1]

6. Give answer to question 1 of Section 2.6.3.. Analysis.
7. Now, using the logic gate ICs, build the simplified expression logic circuit and note down the output of the circuit for
all possible combinations of A, B and C in Table 2 .2. Show working circuit to the lab engineer to obtain credit.
[2]
8. Give answer to question 2 of Analysis.
Table 2.2: Truth table of the simplified expression of F

A B
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
C F (Simplified expression)
1 1
0 0
1 1
0 0
1 1
0 0
1 1
0 1

2.6.2. Task 2: Eliminating AND from logic circuits [Marks: 6]

1. The De Morgan’s laws can be used to completely rid any Boolean logic function of either the AND or the OR
operation. Consider the following expression:
G= X .Y + X . Z 6
2. This expression has one 2-input OR operation and two 2-input AND operations. Compute the output of this expression
for all possible combinations theoretically and fill its truth table below: [1]
Table 2.3: Truth table of G

X Y Z G
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
3. Now use De Morgan’s laws to derive a logical equivalent expression of this function that uses only “OR” and “NOT”
operations. Also mention the Boolean algebra property used at each step. [2]

4. Build the logic circuit of the AND-eliminated expression of last step and check for all possible combinations of X, Y
and Z. Show working circuit to the lab engineer and note down output observations in the form of a truth table in
Table 2 .4: [3]
Table 2.4: Truth table of OR-eliminated circuit

X Y Z Output of AND-eliminated circuit

0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
5. Give answers to questions 3 and 4 of Analysis.
0 0
1 0
0 0
1 0
0 1
1 0
0 1
1 1

2.6.3. Analysis [Marks: 5]

1. Comment on the reduction in the number of gates and connections in the logic diagram of step 5 as compared to that
of step 3. Also, given the type of ICs that you are provided for this lab, assess the reduction in the number of ICs used
by both circuits. [2]

In the step 3, there were many gates but when we reduced the number of gates, it was easier to solve but it had the
same effect as that of step 3 many gates.
We were provided with 7404, 7408 and 7432 ICs

2. State whether the output obtained in Table 2 .2 corresponds to the one derived in Table 2 .1. [1]
 Yes, the output obtained In table in Table 2 .2 corresponds to the one derived in Table 2 .1. All the outcomes are
same

3. State whether the output obtained in Table 2 .4 from this circuit is the same as in Table 2 .3 or different. What does
the comparison of both outputs tell you about the logical equivalence of both expressions? [1]

the output obtained in Table 2 .4 from this circuit is the same as in Table 2 .3. By comparing the both outputs,
we will come to know that the logical equivalence expression has the same outputs and results as that of large
expression

4. What advantage does the elimination of AND gate offer here? Is it in terms of the reduction of gates and
interconnections as in the case of simplification? [1]

By eliminating the AND gate, we reduce gates and by reduction of gates, it becomes very easier to find its output
as it gets very simple.
 Assessment Rubric

Does not meet

Exceeds expectation Meets expectation
Performance expectation Marks
(5-4) (3-2)
(1)
1. Realization of Selects relevant equipment Needs guidance to select Incapable of selecting
Experiment to the experiment, develops relevant equipment to the relevant equipment to
setup diagrams of experiment and to develop conduct the experiment,
equipment connections equipment connection or equipment connection or
or wiring. wiring diagrams. wiring diagrams.
2. Teamwork Actively engages and Cooperates with other Distracts or discourages
cooperates with other group group members in a other group members
Members in an effective reasonable manner. from conducting the
manner.
experiment.
3. Conducting Does proper calibration of Calibrates equipment, Unable to calibrate
Experiment equipment, carefully examines equipment appropriate equipment,
examines equipment moving parts, and operates and equipment operation
moving parts, and ensures the equipment with minor is substantially wrong.
smooth operation and error.
process.
4. Laboratory Respectfully and carefully Observes safety rules and Disregards safety rules
Safety Rules observes safety rules and procedures with minor and procedures.
procedures deviation.

5. Data Plans data collection to
Collection achieve experimental
objectives, and conducts an
orderly and a complete data
collection.
6. Data Analysis Accurately conducts simple
computations and statistical
analysis using collected
data; correlates
experimental results to
known theoretical values;
accounts for measurement
errors and parameters that
affect experimental results.
7. Computer Use Uses computer to collect
and analyze data
effectively.
Plans data collection to
achieve experimental
objectives, and collects
complete data with minor
error.
Conducts simple
computations and statistical
analysis using collected
data with minor error;
reasonably correlates
experimental results to
known theoretical values;
attempts to account for
measurement errors and
parameters that affect
experimental results.
Uses computer to collect
and analyze data with
minor error.
Does not know how to
plan data collection to
achieve experimental
goals; data collected is
incomplete and contain
errors.
Unable to conduct simple
statistical analysis on
collected data; no attempt
to correlate experimental
results with known
theoretical values;
incapable of explaining
measurement errors or
parameters that affect the
experimental results.
Does not know how to use
computer to collect and
analyze data.

Total