Chapter 4: Basics of Digital Electronics

Topics to be covered: Logic Gates, realization of logic circuits, Half and Full Adders, Flip-
Flops, Registers and Counters, A/D and D/A Conversion.

LOGIC GATES

Digital electronics deals with the manipulation of numbers. This is achieved by representing
numbers in a digital form and using logic operations to provide the processing needed. To
achieve this there is a large variety of different types of logic gate and digital circuit building
blocks that can be employed.

A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels. The logic state of a terminal can change
often, as the circuit processes data. In most logic gates, the low state is approximately zero volts
(0 V), while the high state is approximately five volts positive (+5 V).

There are seven basic logic gates: AND, OR, NOT, NAND, NOR, Ex-OR and Ex-NOR.

1. NOT: The NOT gate is possibly the simplest type of logic gate. It takes a single input
and inverts it. Using this logic gate or logic circuit, a logic "1" becomes logic "0" and a
logic "0" becomes logic "1".

Truth Table
A B
0 1
1 0

2. AND / NAND: The AND and NAND logic gates are normally viewed together because
the output of one is the inverse of the other. The basic function of this type of logic gate
is the same. AND gate, produces an output of "1" only when both inputs are "1",
otherwise it produces a "0". The NAND type of logic gate produces the inverse of this.

Truth Table
A B C
0 0 0
1 0 0
0 1 0
1 1 1

Logic AND gate symbol

 Truth Table
A B C
0 0 1
1 0 1
0 1 1
1 1 0

Logic NAND gate symbol

3. OR / NOR: OR gates and NOR gates are another form of logic gate that form one of the
basic building blocks of digital technology. The OR gate gives a logical "1" when one of
the either inputs (or both inputs) is high.

Similarly the NOR gate is the inverse of this and goes low, "0" when one or the either
inputs (or both inputs) is high.
Truth Table
A B C
0 0 0
1 0 1
0 1 1
1 1 1

Logic OR gate symbol

Truth Table
A B C
0 0 1
1 0 0
0 1 0
1 1 0

Logic NOR gate symbol

 4. Exclusive OR / Exclusive NOR: An exclusive OR (or) exclusive NOR type of logic
gate is used where an output change is only required when one of the either input is high
or low and not both.

Truth Table
A B C
0 0 0
1 0 1
0 1 1
1 1 0

Logic Exclusive OR gate circuit symbol

Truth Table
A B C
0 0 1
1 0 0
0 1 0
1 1 1

Logic Exclusive NOR gate circuit symbol

Half Adder and Full Adder Circuits

An adder is a digital logic circuit in electronics that implements addition of numbers. In many
computers and other types of processors, adders are used to calculate addresses, similar
operations and table indices in the ALU and also in other parts of the processors. These can be
built for many numerical representations like excess-3 or binary coded decimal. Adders are
classified into two types: half adder and full adder. The half adder circuit has two inputs: A and
B, which add two input digits and generate a carry and sum. The full adder circuit has three
inputs: A, B and Cin, which add the three inputs and generate a Carry (Cout) and Sum (S).

Half Adder
Half Adder is the adder which adds two inputs and produces two outputs. The two inputs are A
and B and the output carry is designated as COut and the normal output is designated as S which
is Sum.
Half Adder Truth Table
Inputs Outputs

A B Sum Cout

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logical Expression for SUM:

Sum = A’ B + A B’
= (A B)

Logical Expression for Cout:

Cout = AB

Logic Circuit for Half Adder

Full Adder
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as Cin. The output carry is designated as COut and
the normal output is designated as S which is Sum.
A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another.

Full Adder Truth Table:

Logical Expression for SUM:

Sum = A’ B’ Cin + A’ B Cin’ + A B’ Cin’+ A B Cin
= Cin (A’ B’ + A B) + Cin’(A’ B + A B’)
= Cin (A B)

Logical Expression for Cout:

Cout = A’ B Cin + A B’ Cin + A B Cin ’+ A B Cin
= Cin (A’ B + A B’) + A B (Cin + Cin ’)
= Cin (A B) + A B
 Logic Circuit for Full adder

Combinational and Sequential Circuits

Combinational Circuit – Combinational circuits are defined as the time independent circuits
which do not depends upon previous inputs to generate any output are termed as combinational
circuits.

Block Diagram

1. Elementary building blocks: Logic gates

2. In this output depends only upon present input.
3. Speed is fast.
4. Easy to design.
5. There is no feedback between input and output.
6. This is time independent.
7. Used for arithmetic as well as boolean operations.
8. Combinational circuits don’t have capability to store any state.
9. As combinational circuits don’t have clock, they don’t require triggering.
10. These circuits do not have any memory element.

Examples – Encoder, Decoder, Multiplexer, De-multiplexer

Sequential Circuit- Sequential circuits are those which are dependent on clock cycles and
depend on present as well as past inputs to generate any output.

Block Diagram –

1. Elementary building blocks: Flip-flops

2. In this output depends upon present as well as past input.
3. Speed is slow.
4. Design is not easy as compared to combinational circuits.
5. There exists a feedback path between input and output.
6. This is time dependent.
7. Mainly used for storing data.
8. Sequential circuits have capability to store any state or to retain earlier state.
9. As sequential circuits are clock dependent they need triggering.
10. These circuits have memory element.
Examples – Flip-flops, Counters

Flip-Flops

Flip flops are actually an application of logic gates. A flip flop is an electronic circuit with two
stable states that can be used to store binary data. The stored data can be changed by applying
varying inputs. Flip flops can also be considered as the most basic idea of a Random Access
Memory [RAM]. When a certain input value is given to them, they will be remembered and
executed, if the logic gates are designed correctly. A higher application of flip flops is helpful in
designing better electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback circuit.
As a memory relies on the feedback concept, flip flops can be used to design it.
There are mainly four types of flip flops that are used in electronic circuits. They are

1. Set-Reset Flip Flop [SR Flip Flop]

2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop

S-R Flip Flop

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND
gates. These flip flops are also called S-R Latch.

S-R Latch using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are
also two outputs, Q and Q’. The diagram and truth table is shown below.

From the diagram it is evident that the flip flop has mainly four states. They are

S=1, R=0—Q=1, Q’=0 This state is also called the SET state.

S=0, R=1—Q=0, Q’=1 This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the value of S.

S=0, R=0—Q & Q’ = Memory

If both the values of S and R are switched to 0, then the circuit remembers the value of S and R
in their previous state.

S=1, R=1—Q=0, Q’=0 [Invalid]

This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be
compliments of each other. Normally, this state must be avoided
S-R Latch using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.

S-R flip flop with NAND gate has four states. They are

S=1, R=0—Q=0, Q’=1 This state is also called the SET state.

S=0, R=1—Q=1, Q’=0 This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the compliment value of S.

S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values of both Q
and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must be
avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the value of S and R
in their previous state.

Clocked S-R Flip Flop

It is also called a Gated S-R flip flop. The problems with S-R flip flops using NOR and NAND
gates is the invalid state. This problem can be overcome by using a bi-stable SR flip-flop that can
change outputs when certain invalid states are met, regardless of the condition of either the Set or
the Reset inputs. For this, a clocked S-R flip flop is designed by adding two NAND gates to a
basic NAND Gate flip flop. The circuit diagram and truth table is shown below.
 Clk S R Qn+1
0 X X Qn (Memory)
1 0 0 Qn (Memory)
1 0 1 0
1 1 0 1
1 1 1 Invalid
In this circuit, the output is changed (i.e. the stored data is changed) only when you give an
active clock signal. Otherwise, even if the S or R is active the data will not change.

D Flip Flop
D flip flop is actually a slight modification of the clocked SR flip-flop. From the figure you can
see that the D input is connected to the S input and the complement of the D input is connected
to the R input. The D input is passed on to the flip flop when the value of CP is ‘1’.

The circuit diagram and truth table is given below.

Clock D Qn+1
0 X Qn (Memory)
1 0 0
1 1 1

In a D flip flop, the output can be only changed at the clock edge, and if the input changes at
other times, the output will be unaffected.
The change of state of the output is dependent on the rising edge of the clock. The output (Q) is
same as the input and can only change at the rising edge of the clock.
J-K Flip-flop

A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is
that the intermediate state is more refined and precise than that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.
So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.

The input condition of J=K=1, gives an output inverting the output state. However, the outputs
are same when one tests the circuit practically.

Clk J K Qn+1
0 X X Qn (Memory)
1 0 0 Qn (Memory)
1 0 1 0
1 0 1 1
1 1 1 Qn (Compliment of Qn)

T Flip Flop

A T flip flops is like JK flip-flop. These are basically single input version of JK flip flops. This
modified form of JK flip-flop is obtained by connecting both inputs J and K together. This flip-
flop has only one input along with the clock input.
These flip-flops are called T flip-flops because of their ability to complement its state (i.e.)
Toggle, hence the name Toggle flip-flop.

Truth Table

Clk T Q n+1
0 X Qn(Memory)
1 0 Qn(Memory) as J=0 & K=0
1 1 Qn (Compliment of Qn) Toggling state
as J=1 & K=1

Applications of Flip-Flops: Flip-flops are basic building blocks for

1. Counters
2. Frequency Dividers
3. Shift Registers
4. Storage Registers

Counters:

Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on design. They are designed with the
help of flip flops.

Counter Classification: Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter universal clock is not used, only first flip flop is driven by main clock
and the clock input of rest of the counters is driven by output of previous flip flops. This can be
understood by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the falling edge of clock pulse is
encountered, Q1 is changing when falling edge of Q0 is encountered (because Q0 is clock pulse
for second flip flop), Q2 is changing when falling edge of Q1 is encountered (because Q1 is clock
pulse for third flip flop) Q3 is changing when falling edge of Q2 is encountered (because Q2 is
clock pulse for fourth flip flop). In this way ripples are generated through Q0, Q1, Q2, Q3 hence it
is also called RIPPLE counter.
2. Synchronous Counter
Synchronous counter has one global clock which drives each flip flop so output changes in
parallel. The one advantage of synchronous counter over asynchronous counter is, it can operate
on higher frequency than asynchronous counter as it does not have cumulative delay because of
same clock is given to each flip flop.

From circuit diagram we see that

Q0 bit gives response to each falling edge of clock
Q1 is dependent on Q0,
Q2 is dependent on Q1 and Q0,
Q3 is dependent on Q2, Q1 and Q0.
Shift Registers
Shift Registers are sequential logic circuits, capable of storage and transfer of data. They are
made up of Flip Flops which are connected in such a way that the output of one flip flop could
serve as the input of the other flip-flop, depending on the type of shift registers being created.

Types of Shift Registers:

Shift registers are categorized into types majorly by their mode of operation, either serial or
parallel. There are four (4) basic types of shift registers:

1. Serial in – Serial out Shift Register (SISO)

2. Serial in – Parallel out shift Register (SIPO)
3. Parallel in – Parallel out Shift Register (PIPO)
4. Parallel in – Serial out Shift Register (PISO)

1. Serial in - Serial out Shift Registers

Serial in – Serial out shift registers are shift registers that streams in data serially (one bit per
clock cycle) and streams out data too in the same way, one after the other.

1. At the first clock pulse, the data at “data in” will be present at the Stage A output.
2. After the second pulse stage A data is transferred to stage B output, and data at “data
in” is transferred to stage A output.
3. After the third clock pulse, stage C is replaced by stage B output; stage B is replaced
by stage A output; and stage A is replaced by data present at “data in”.
4. After the fourth clock, the data which was first present at “data in” is at stage D output.
5. The “first in” data is “first out” as it is shifted from “data in” to “data out”.

2. Serial in – Parallel out Shift Register

These types of shift registers are used for the conversion of data from serial to parallel. The data
comes in one after the other per clock cycle and can either be shifted or replaced or be read off
at each output. This means when the data is read in, each read in bit becomes available
simultaneously on their respective output line (QA to QD for the 4-bit shift register shown below).
3. Parallel in – Serial out Shift Register

For this type of shift register, the data is supplied in parallel, for example consider the 4-bit shift
register shown below.

This register can be used to store and shift a 4-bit word, with the write/shift (WS) control input
controlling the mode of operation of the shift register. When the WS control line is low (Write
Mode), data can be written and clocked in via DA to DD. To shift the data out serially, the WS
control line is brought HIGH (Shift mode), the register then shifts the data out on clock input.

4. Parallel in – Parallel out shift register

For parallel in – parallel out shift register, the output data across the parallel outputs appear
simultaneously as the input data is fed in.

The input data at each of the input pins from DA to DD are read in at the same time when the
device is clocked and at the same time, the data read in from each of the inputs is passed out at
the corresponding output (from QA to QD).
Analog to Digital Converter

Analog to digital converter is a converter which converts the analog (continuously variable)
signal to digital signal. This is an electronic integrated circuit which directly converts the
continuous form of signal to discrete form. It can be expressed as A/D or A-to-D or A-D or
ADC. The input (analog) to this system can have any value in a range and are directly measured.
But for output (digital) of an N-bit A/D converter, it should have only 2N discrete values.

ADC Process
There are mainly two steps involved in the process of analog to digital conversion. They are

1.Sampling and Holding

2.Quantizing and Encoding
The whole ADC conversion process is shown in figure below

Sampling and Holding

In the process of Sample and hold (S/H), the continuous signal will gets sampled and freeze
(hold) the value at a steady level for a particular period of time. It is done to remove variations in
input signal which can alter the conversion process and thereby increases the accuracy. The
minimum sampling rate has to be two times the maximum data frequency of the input signal.

Quantizing and Encoding

Before understanding quantizing, we need to first understand the term Resolution used in ADC.
It is the smallest variation in analog signal that will result in a variation in the digital output. This
actually represents the quantization error.

Where, V → Reference voltage range

2N → Number of states
N → Number of bits in digital output
Quantizing: It is the process in which the reference signal is partitioned into several discrete
quanta and then the input signal is matched with the correct quantum.
Encoding: Here; for each quantum, a unique digital code will be assigned and after that the input
signal is allocated with this digital code. The process of quantizing and encoding is demonstrated
in the table below.

From the above table we can observe that only one digital value is used to represent the whole
range of voltage in an interval. Thus, an error will occur and it is called quantization error. This
is the noise introduced by the process of quantization. Here the maximum quantization error is

Types of Analog to Digital Converter

1. Successive Approximation ADC: This converter compares the input signal with the
output of an internal DAC at each successive step. It is the most expensive type.
2. Dual Slope ADC: It have high accuracy but very slow in operation.
3. Pipeline ADC: It is same as that of two step Flash ADC.
4. Delta-Sigma ADC: It has high resolution but slow due to over sampling.
5. Flash ADC: It is the fastest ADC but very expensive.
6. Other: Staircase ramp, Voltage-to-Frequency, Switched capacitor, tracking, Charge
balancing, and resolver.

Application of ADC: ADCs are used in Computers, Cell phones, Microcontrollers, Digital
signal processing, Digital storage oscilloscopes, Scientific instruments etc.
Digital to Analog Converter (DAC)
Digital to Analog Converter (DAC) is a device that transforms digital data into an analog signal.
A DAC can reconstruct sampled data into an analog signal with precision. The digital data may
be produced from a microprocessor, Application Specific Integrated Circuit (ASIC), or Field
Programmable Gate Array (FPGA), but ultimately the data requires the conversion to an analog
signal in order to interact with the real world.

DAC using Weighted Resistors method

Figure below shows the schematic diagram of a DAC using weighted resistors. The basic
operation of DAC is the ability to add inputs that will ultimately correspond to the contributions
of the various bits of the digital input.

In the voltage domain, that is if the input signals are voltages, the addition of the binary bits can
be achieved using the inverting summing amplifier shown in the above figure.

The input resistors of the op-amp have their resistance values weighted in a binary format. When
the logic circuit receives binary 1, the switch connects the resistor to the reference voltage. When
the logic circuit receives binary 0, the switch connects the resistor to ground. All the digital input
bits are simultaneously applied to the DAC.
The DAC generates analog output voltage corresponding to the given digital data signal. For the
DAC the given digital voltage is b3 b2 b1 b0 where each bit is a binary value (0 or 1).
The output voltage produced at output side is
V0=R0/R (b3+b2/2+b1/4+b0/8) Vref