Lab 13 : Binary Counter Systems:

Slide 2 Three stage ripple counter.

Slide 3 Down Counters.

Slide 4 Up/Down Counters.

Slide 5 Altera 4count Symbol.

Lab 13 : Three Stage Ripple counter :
JK flip flops connected in the toggle mode can be connected together to create a binary
counter system. Start with one JK flip flop, apply a clock waveform and sketch the Q
output response. Assume PRE and Clr has been disabled (=1) on all flip flops.

Input
1 J Qa 1 J Qb 1 J Qc
>Clk >Clk >Clk
1 K Qa 1 K Qb 1 K Qc

0 1 2 3 4 5 6 7 In Qc Qb Qa
0 0 0 0

1 0 0 1

2 0 1 0
Qa Qa will toggle on each negative edge of the input clock.
3 0 1 1
Connect
Qb will toggle
a second
on each
stagenegative
to output
edge
Qa.of Qa.
4 1 0 0
Qb
5 1 0 1
Connect
Qc will toggle
a thirdonstage
eachto
negative
output edge
Qb. of Qb.
6 1 1 0
Qc
7 1 1 1
Label the input clock pulses from 0 to 7 and place the counter response in a table.
The table is called a COUNT state table. The counter is called a MOD 8 counter because it has 8 different count
states. The counter restarts at 0, 0, 0 after clock input 7. MOD is short for the word MODULUS.
Connect the flip flop outputs to 3 LED’s and you will see a binary count sequence from 0 … to … 7.
The speed at which the counter counts is controlled by the input clock. 1 PPS input clock will display the 0
to 7 count sequence on the LED’s in 8 seconds. Each count state would last 1 sec. If the clock input was
Slide #2 1000 PPS then all 3 LED’s would appear to be constantly on at the same time. A count cycle would take
8milliSec. Too fast to be visible on the 3 LED’s.
Lab 13: Down Counters :
To make a counter count backwards all you need to do is to connect the Q to the Clk of the
next flip flop.

Input
1 J Qa 1 J Qb 1 J Qc
>Clk >Clk >Clk
1 K Qa 1 K Qb 1 K Qc

In Qc Qb Qa
Qa toggles
0 on0every 0 0
negative edge of the input
clock. 1 1 1 1

Qa 2 1 1 0
Qb toggles on every
negative
3 edge1of Qa.
0 1

Qa
Qb A negative
4 edge1 on0 Qa0is the
same as the positive edge
Qa. 5 0 1 1
Qc toggles
6 on0every1 0
Qc negative edge of Qb. Which
is the same
7 as0the0positive
1
edge of Qb.
If you place the count states in a table you can see the down count
sequence.

Slide #3
Lab 13: Up/Down Counter :
This system combines the features of both an up and a down counter. The system has a
count direction control input to select up counting or down counting.

1
0 Qa•1
0 1
0 Qb•1
0
1 J Qa 1 J Qb 1 J Qc
>Clk >Clk >Clk
K Qa 0 K Qb 0 K Qc
1 1 1
0
1 Qa•1 0
1 Qb•1
0
1
Up/Down

When the control input is low, the top AND gates will pass the logic levels from the Q
outputs.

The bottom AND gates output 0. The OR gate outputs a Q•1+0 = Q. This connects Q to
clock and the counter counts up or forward.
When the control input is high, the bottom AND gates pass the logic levels from the Q
outputs.
The top AND gates output 0. The OR gate outputs a Q•1+0 = Q. This connects Q to
clock and the counter counts down or backwards.

Slide #4
Lab 13: Altera 4Count Symbol:
The Altera 4count symbol is a 4-bit counter system. Apply a pulse waveform to the positive
edge triggered clock input and it counts from 0 to 15.
Synchronous Load: LDN and ABCD and Clock:
LDN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D on positive edge of clock.
Step
Step 15
3
4
1::
2 LDN=1 disables the load feature. Clock is used for counting.
Assert
Place
Disable4load
Enable
Apply number
up The animation will demonstrate how to load the number 6 into the counter.
4count
and
at inputs
place
load
counting
down
clock and
number at 10 LDN
clear
counting
pulses
inputs 0 A Asynchronous Load: SETN and ABCD:
inputs 1 B QA SETN=0 loads a number into Qa, Qb, Qc, Qd from A, B, C, D
6 1 C QB
immediately. The clock is not required.
0 D QC
CIN QD SETN =1 disables the load feature. Clock is used for counting.
0
1 DNUP COUT The animation will demonstrate how to load the number 6 into
Step 2: 0 1 SETN 1 1
0 0 1
0 1
0 the counter.
Assert
Assert 01 CLRN
SETN
CLRN CLK Asynchronous Clear: CLRN:
CLRN=0 resets (clears) Qa=Qb=Qc=Qd =0. Clock not required
Step 2: CLRN =1 disables the clear feature. Clock is used for counting.
Assert Clock
Count Direction: DNUP:
DNUP=0 Counter counts forward or up (0,1,2…). DNUP=1 Counter counts backwards or down (15,14,13…).
The animation will demonstrate an up count sequence to 4 and then a down count sequence back to 0. The count sequence can be
reversed at any time.
CIN and COUT:
Carry in and Carry out are used to cascade counter symbols.
Cascading will be explained in an upcoming lab.

Altera Default Values:

Altera connects LDN, SETN, CLRN, DNUP and CIN to 1 if they are left unconnected in a drawing. These are
called default values. The default values will make the counter count down and disable the loading and
Slide #5 clearing functions.