Sequential Circuits and Flip Flops

6
Sequential Logic and Flip Flops

6.1 Introduction :
Sequential circuits are those circuits whose present output depends on present input as well as previous
output. These circuits have feedback from output of circuit. These circuits include memory elements.
Note : Examples of sequential circuits
(i) Flip Flops (ii) Counters
(iii) Registers (iv) RAM
6.2 Difference between combinational & sequential circuits
Present output of combinational circuits depend only on present input and not on previous output. They do not
contain any feed back or memory element whereas present output of sequential circuit depends on present
input and previous output. They have feed back and memory elements.
Examples of Combinational circuits :
(i) Code Converters (ii) Adder
(iii) Subtractors (iv) Comparator
(v) Encoder (vi) MUX
(vii) Decoder (viii) DEMUX
(xi) ROM (x) PLA
Examples of sequential circuit :
(i) Flips Flops (ii) Counters
(iii) Registers
6.3 Types of sequential circuits
A. Synchronous Sequential circuits :
The sequential circuits whose behaviour can be described at discrete instants of time are called synchronous
sequential circuit. Memory elements are affected only at discrete instants of time.
B . Asynchronous Sequential circuit :
The sequential circuits whose behaviour depends on sequence in which the input signals change are referred
as asynchronous sequential circuits. Their output is affected only when input changes. Asynchronous sequential
circuits are also called combinational circuits with feedback.
Note : Synchronous circuits are faster than asychrounous circuits
6.4 Flip-Flops
Flip-Flop is a basic digital memory circuit or one bit memory cell. It acts as a bistable multivibrator. It has two
stable stage states 0 and 1. If circuit is in one state then it continues to remain in that state. This property is
called as memory. Since this information is locked or latched, therefore, Flip-Flop also called as latch.
Note : The Flip-Flop which has number input is called as latch.
* Flip-Flop may be level or edge triggered. While latch is level trigger always
Flip-Flop is one bit storage memory device.
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Flip Flos & Sequential Circuits DIGITAL ELECTRONICS 2
6.4.1 Basic Latches

A) S-R Flip-Flop Using NOR
S 1 –
(Set) Q
0
1
1 0 Q
R
(Reset)
S R Qn  1
0 0 Qn
0 1 0
1 0 1
1 1 X
B) S-R Using NAND

–
S
Q
–
– Q
R
S R Qn + 1
0 0 X
0 1 0
1 0 1
1 1 Qn
6.4.2 Clocked SR flip-flop

(a) Logic diagram (Using NAND gates) :
S
Q
CLK
–
Q
R
Using NAND gates
S
Q
CLK
–
Q
R
Using NOR gates
(b) Truth Table :
Inputs Output
Sn R n Q n +1
0 0 Qn
0 1 0
1 0 1
1 1 X
X  Indeterminate
Logic symbol of clocked S-R Flip Flop :
S Q
–
R Q
(c) State Table/characteristic Table:
Q n So R o Q n  1
0 0 0 0 0 (Q n )
1 0 0 1 0
2 0 1 0 1
3 0 1 1 d
4 1 0 0 1(Q n )
5 1 0 1 0
6 1 1 0 1
7 1 1 1 d
(d) State equation / characteristics equation :

SR Qn + 1
Q 00 01 11 10
0 1 3 2
0 d 1
4 5 7 6
1 1 d 1
Note : Don’t include ‘d’ in reducing k-map because these states are not allowed.
Qn + 1 = SR  Qn R  (S  Qn ) R
Qn + 1 = (S  Q n ) R
(e) Excitation Table : (derived from state table)
Q n Qn  1 S R
0 0 0 d
0 1 1 0
1 0 0 1
1 1 d 0
(f) State Diagram/Transition Diagram :
S = 1, R = 0
S=0 S 0 1 R S=d
R=d R=0
R = 1, S = 0
(g) Signal Waveform :
CLK
1 2 3 4 5 6
t
(h) S-R Flip-Flip as Toggle switch :
S Q
CLK SRFF
–
R Q
6.4.3 D-Flip-Flop /Delay Flip-Flop/Data transfer Flip-Flop

(a) Logic circuit
D
Q
CLK
–
Q
D S Q
CLK
–
R Q
Using SR Flip-Flop
(b) Symbol :
Symbol
D Q
CLK
–
Q
D J Q
CLK
–
K Q
(c) Truth Table :
CLK D Q n +1
0 X Qn
1 0 0
1 1 1
(d) State Table /characteristic Table :
Q n D Qn  1
0 0 0
0 1 1
1 0 0
1 1 1
(e) State equation / characteristic equation :
D Qn + 1
Qn 0 1
0 1
0 1
2 3
1 1
Qn + 1 = D
Note : Next state is independent of previous state and depend only on present input.
(f) Excitation Table :
Q n Q n+1 D
0 0 0
0 1 1
1 0 0
1 1 1
(g) State Diagram :
D
D 0 1 D
D
Note : Positive level triggered D – Flip-Flip is used as Transparent Latch or Delay Device.
(h) Wave form :
CLK
* Difference between Latch and Flip-Flop :

When Flip-Flop is level triggered it is called a Latch. Positive level triggered D-Flip-Flop is called Transparent
Latch.
6.4.4 J-K Flip-Flop
(a) (i) Using S-R FF :
S
AND
J
Q
CLK
–
Q
K R
AND SR-FF
JQ
S Q Q
J
K KQ –
R Q Q
S = JQ, R  KQ
(i) Using NAND gates only :
J
Q
CLK
–
Q
K
(b) Symbol :
J Q
CLK
–
K Q
(c) Truth Table :
J K Qn  1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
(d) State Table/characteristic Table :
Qn J K Qn  1
0 0 0 0 0
1 0 0 1 0
2 0 1 0 1
3 0 1 1 1
4 1 0 0 1
5 1 0 1 0
6 1 1 0 1
7 1 1 1 0
(e) State equation / characteristics equation :
JK Qn+1
Qn 00 01 11 10
0 1 3 2
0 1 1
4 5 7 6
1 1 1
Qn + 1 = Qn J  Qn K
Q n Qn  1 J K
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0
(g) State Diagram :
J
J 0 1 K
K
Note : i) D flip flop is delay filp flop, D stands for delay in transfer of data.
ii) D flip flop transfers the data of input at the output when clock signal is reached. During this process it
introduces a delay that is why D flip flop is called as delay flip flop.
iii) Level triggered D flip flop is called as transparent latch.
D-flip flop As a Transparent Latch :
In D-flip flop the output Q will follow D input (transperently) as long as enable line is high when enable signal
goes to low the output Q (is latched) to the value that D was just high before high to low transition of enable
line.
6.4.5 T – Flip-Flop : (T stands for trigger or toggle)

(a) Using NAND gates :
T J
Q
CLK
–
Q
K
(b) Symbol :
T J Q
CLK
–
K Q
T Q
CLK
–
Q
(c) Truth Table :
T Qn  1
0 Qn
1 Qn
(d) State table / characteristic Table :
Qn T Q n  1
0 0 0 0
1 0 1 1
2 1 0 1
3 1 1 0
(e) State equation / characteristic equation :
T Qn + 1
Qn 0 1
0 1
0 1
2 3
1 1
Qn + 1 = Qn T  Qn T  Qn  T
Qn Qn  1 T
0 0 0
0 1 1
1 0 1
1 1 0
(g) State Diagram :
T=1
T=0 0 1 T=0
T=1
(h) Waveform :
T T Q Q
CLK
CLK
Note : T – Flip-Flop is divide by two device.

The frequecy of Q is half of frequency of CLK.
Therefore it is generally used in counters.
Excitation Table of all Flip - Flops :
Qn Qn  1 S R J K D T
0 0 0 d 0 d 0 0
0 1 1 0 1 d 1 1
1 0 0 1 d 1 0 1
1 1 d 0 d 0 1 0
6.5 Triggering of Flip-Flops

i) Level Triggering :
Triggering
level
1
(a)Positive level Triggering 0
(b)Negative level Triggering 1
0
Triggering
level
(ii) Edge Triggering
(a)Positive edge Triggering

(b)Negative edge Triggering
RC differentiator circuit is used for edge triggering
C
T R
Note : RC < < T

6.4 Asynchronous inputs in Flip-Flops : (Preset and clear)
(A) SR –Flip Flop :
Present PR
PR
S
Q
S Q
CLK CLK
– R –
Q Q
R
CLR
CLR
(B) JK
PR
PR
J Q
J Q
CLK CLK
– –
K Q K Q
CLR
CLR
Note : SR, JK, D and T are called synchronous inputs

6.6 Asynchronous Input in Flip-Flops
PR and CLR are called Asynchronous inputs because these inputs can be used to clear or preset the flip-flops
6.7 Race - around condition
In level triggered flip-flop at J = K = 1 if transportation delay of Flip-Flop is less than clock pulse, then output
of Flip-Flop toggles continuously and it becomes difficult to tell the state of flip-flop at the end of clock pulse.
This condition is refered as race around condition. The race around condition can be avoided if tp < t < T,
where tp is pulse width, t is delay in flip-flop and T is time period of clock.
t
tp
0 T
This can be achieved by following two methods :

i) By using Edge Triggering
Edge Triggering can be done by differentiating clock pulses using RC differentiator before they are applied to
Flip-Flop.
R T
T
RC << T
ii) By using Master-Slave Flip-Flop
6.8 Master-Slave Flip-flop or Pulse Triggered Flip-Flop
(a) JK master slave Flip-Flop
Note : Master slave Flip-Flop is called pulse triggered Flip-Flop.
J
CLK
Master Slave
Master FF is triggered when CLK = 1 and slave

Flip-Flop is triggered when CLK = 0 and slave copies the master.
The information from inputs is transferred to master flip-flop at positive / leading edge of clock pulse and
slave F-F remains disabled. A negative / trailing edge information is transferred at output of slave and master
remain disabled. Thus output of master-slave flip-flop changes only at the end of clock pulse and race around
condition never occurs. The slave just copies the master. Since output of master-slave changes only after
arrival of complete pulse, that’s why it is also called pulse triggerred flip-flop.
Note : The major restriction in master slave flip-flop is that input should not change when clock pulse is high
because that will be immediately transferred into master flip flop.
Note : There are three basic types of master slave
Flip-Flops – JK, SR and D.
Note : Master and slave are not edge triggered but level triggered.
6.9 Flip-Flop Conversions
A Q
Combination Given
circuit Flip-Flop
B Q
Inputs of required
Flip-Flop
D S Q
i) D using SR
–
R Q
D J Q
ii) D using JK
–
K Q
iii) D using T
iv) SR using D
v) SR using JK
vi) SR using T
vii) JK using D
viii) JK using SR
ix) JK using T
x) T using SR
xi) T using JK
xii) T using D
Transition Tables of Flip-Flops :
Qn Qn  1 S R J K D T
0 0 0 d 0 d 0 0
0 1 1 0 1 d 1 1
1 0 0 1 d 1 0 1
1 1 d 0 d 0 1 0
Example : 1
J-K using S.R :
Solution :
Steps find S and R as function of J, K, Qn and Q n by using transition table and K-maps.
Qn  Present State
Qn Qn + 1 S R
0 0 0 d
Excitation table of SR  0 1 1 0
1 0 0 1
1 1 d 0
Truth Table :
Qn J 0 K 0 Q n  1 S0 R 0
0 0 0 0 0 0 d
1 0 0 1 0 0 d
2 0 1 0 1 1 0
3 0 1 1 1 1 0
4 1 0 0 1 d 0
5 1 0 1 0 0 1
6 1 1 0 1 d 0
7 1 1 1 0 0 1
K -maps :
JnKn S JnKn R
Qn 00 01 11 10 Qn 00 01 11 10
0 1 3 2 0 1 3 2
0 1 1 0 d d
4 5 7 6 4 5 7 6
1 d d 1 1 1
S = Qn J n R = Qn Kn
Realization :
S
Q
J
CLK
K
Q
R
Example : 2
T Flip Flop using SR.
Solution :
Excitation table of SR
Q n Q n 1 S R
0 0 0 d
0 1 1 0
1 0 0 1
1 1 d 0
Exacitation table for realization :
Qn T Qn  1 S R
0 0 0 0 0 d
1 0 1 1 1 0
2 1 0 1 d 0
3 1 1 0 0 1
K-maps :
T S T R
Qn 0 1 Qn 0 1
0 1 0 1
0 1 0 d
2 3 2 3
1 d 1 1
–
S = Qn T R = Qn T
S = Qn T R = Qn T
Realization :
S Q
R Q
Example : 3
D using JK
Solution :
D J Q
CLK
–
K Q
Example : 4
D using SR
D S Q
–
R Q
Example : 5
JK using D Flip-Flop :
Solution :
Excitation table of D
Q n Qn  1 D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation Table for conversion :
Qn J K Qn  1 D
0 0 0 0 0 0
1 0 0 1 0 0
2 0 1 0 1 1
3 0 1 1 1 1
4 1 0 0 1 1
5 1 0 1 0 0
6 1 1 0 1 1
7 1 1 1 0 0
K map
JK D
Qn 00 01 11 10
0 1 3 2
0 1 1
4 5 7 6
1 1 1
D = Q n J  Q n K [same as state equation of JK Flip-Flop]

Realization :
J
D Q
K
–
Q
6.10 Applications of Flip-Flops

i) Bounce elimination switch (To avoid chattering)
ii) Registers
iii) Counters
iv) Random access memory (RAM)
v) Latch
vi) Frequency Devision
Note : Each flip-flop divide the frequency by 2.
Divide by 23 circuit :
‘1’ ‘1’ ‘1’
CLK 1 2 3
For divide by 2 n , no. of flip- flops required = n

GATE Practice Questions
1. The output Qn + 1 of a J-K flip-flop for the input J = 1, K = 1

(a) O (b) 1
(c) Q n (d) Qn
GATE(IN/1994/1M)
1. Ans.(d)
The characteristic equation of a J-K flip-flop is given by
Q n+1 = J Q n  K Qn
when, J = 1 and K = 1,
 Q n+1 = 1 Q n  1.Q n = Qn + 0 = Qn
(Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Ch-7 Page-266 Table 7.9 Page 268)
2. In the circuit shown in Fig., when inputs A = B = 0 the possible logic states of C and D are
A
C
B D
(a) C = 0, D = 1 or C = 1, D = 0
(b) C = 1, D = 1 or C = 0, D = 0
(c) C = 1, D = 0
(d) C = 0, D = 1
GATE(IN/2001/2M)
2. Ans.(a)
A
C
D
B
The circuit shown is eqvivalent to NOR based SR Flip Flop
R
Q
Q
S
when S = 0, R = 0 the flip flop simply remains in its present state

Thus when A = B = 0, then C = 0, D = 1 or C = 1, D = 0
Refer Digital Circuits and Design by S.Salivahanan, 2nd edition Page-257, (7.3.1)
3. The correct cyclic sequence of the output (Q0Q1) for the JK master-slave flip-flop circuit shown in figure
when the input clock is applied is
J0 Q0 J1 Q1
Y
Clock
C1 C1
K0 Q0 K1 Q1
1 1
(a) 00, 01, 10, 11, 00, 01, ......

(b) 00, 10, 01, 00, 10, 01, ......
(c) 00, 01, 10, 00, 01, 10, ......
(d) 00, 11, 00, 11, 00, 11, ......
GATE(IN/2003/2M)
3. Ans. (d)
J0 Q0 J1 Q1 Y
Clock
K0 Q0 K1 Q1
1 1
Let initially Q1 = 0 So, Q1 = 1, and J1 = Q0 = 0
CLK Qo,n Jo,n= Q1,n K0,n Q0,n+1 J1,n K1,n Q1,n+1 = Y
1 1 1 1 1 1 1 1
2 1 0 1 0 0 1 0
3 0 1 1 1 1 1 1
4 1 0 1 0 0 1 0
5 0 1 1 1 1 1 1
Thus correct sequence of output of given master slave flip-flop is

D0D1 : 00,11,00,11,00,11.........
4. The two NAND gates before the latch circuit shown in figure are used to
Clock
Set
Reset
(a) act as buffers

(b) operate the latch faster
(c) avoid racing problem
(d) invert the latching action
GATE(IN/2004/1M)
4. Ans.(d)
Clock
Set
Q
Q
Reset
Bubbled input OR gates are equivalent to NAND gates. So we can redrauthe circuit as shown below
Clock
Set
Q
Reset Q
This circuit is a clocked SR Flip Flop. The truth table of SR flip-flop is given as,
Set Reset Output Q n 1

0 0 Qn
0 1 0
1 0 1
1 1 ?
If we draw the circuit as
Set
Q
Q
Reset
Truth table of S-R latch,
Set Re set Output Q(n 1)

0 0 ?
0 1 0
1 0 1
1 1 Qn
Hence the two NAND gates before the latch circuit shown are used to invert the latching action.
Refer Modern Digital Electronics by R.P. Jain, 3nd edition, Page 240, 7.3
Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Page 258 (7.3.2)
5. In the digital circuit shown in the flip-flops have set time of 5 ns and a worst case delay of 15 ns. The AND
gate has a delay of 5 ns. Maximum possible clock rate for the circuit to operate faithfully is
Clock
J Q J Q
0 J Q
C1 C1
Cl
K Q K Q
K Q
1
(a) 21 MHz (b) 22 MHz
(c) 25 MHz (d) 30 MHz
GATE(IN/2004/2M)
5. Ans.(c)
Clock
FF1 FF2 FF3

J Q J Q 0 J Q
Cl C1 Cl
K Q K Q K Q
Given,
Set time of flip-flops = 5 ns
Time delay of each flip-flop = 15 ns
Time delay of AND gate = 5 ns
After application of clock signal the output Q of FF1 changes its state after 15 ns because of delay of flip-flop.
The output of FF1 is connected at the clock of FF2, so the output of FF2 changes its state after 30 ns of
application of clock signal. The outputs of FF1 and FF2 are connected at the input of AND gate, so the output
of AND gate changes its state after 5 ms of change of state of output of FF2. Total delay between change of
state of AND gate and application of clock signal is 35 ns. As set time of flop flops is 5 ns so the clock signal
should be kept high at least for 5 more seconds after application of the input of the flip flop. The input K of FF3
appears after 35 seconds of application of clock signal so the clock signal should be kept high atleast for 40 ns.
Therefore, minimum clock period for the circuit to operate faithfully is 40 ns.
Tclock  40 ns
Maximum rate of clock or clock frequency,
1
fclock 
40  109
fclock  25 MHz
6. A sequential circuit is shown in the figure below. Let the state of the circuit be encoded as QAQB. The notation
X  Y implies that state Y is reachable from state X in a finite number of clock transitions
QA Q
_ _ B
Q Q Q
Q
CLK TA CLK TB
CLK
Identify the INCORRECT statement.
(a) 01  00 (b) 11  01
(c) 01  111 (d) 01  10
GATE(IN/2007/2M)
6. Ans.(c)
QA Q
_ _ B
Q Q Q
Q
CLK TA CLK TB
CLK
From the circuit diagram shown,
TA = QA + QB, TB = Q A + QB
The excitation table of T flip flop,
Qn T Qn 1
0 0 0
0 1 1
1 0 1
1 1 0
The opration of the above circuit is explained in the following table,
Pr esent State In puts Next State

Q A,n Q B,n TA TB Q A,n 1 Q B,n 1
0 1 1 1 1 0
1 0 1 0 0 0
0 0 0 1 0 1
1 1 1 1 0 0
Case-1 : 01  00
From table 01  10 00
Hence state 00 is reachable from state 01 in 2 clock pulses
Case-2 : 11  01
From table : 11  00  01
Hence state 01 is reachable from state 11 in 2 clock pulses
Case-3 : 01  11
From table : 01 10  00  01
Thus we can not reach state 11 from state 01 in given circuit.
Case-4 : 01 10
From table : 01  10
Thus state 10 is reachable from 01 in a single clock pulse.
So, option (c) incorrect statement.
Refer Digital Circuits and Design by S.Salivahanan, 2nd edition Page-329,(8.15.6)
7. In the figure shown, the initial of Q is 0. The output is observed after the application of each clock pulse. The
output sequence at Q is
1
J Q
CLOCK CLK
K Q
(a) 0000... (b) 1010...

(c) 1111... (d) 1000...
GATE(IN/2009/1M)
7. Ans.(c)
1
J Q
CLK
K Q
Truth table of J-K flip-flop is given as,
J K Q n 1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
From circuit, J = 1, K = Q
State table of the circuit can be given as,
CLOCK Pr esent Next state

J 1 K  Q
PULSE state output
0 0 1 1 0
1 0 1 1 1
2 1 1 0 1
3 1 1 0 1
4 1 1 0 1
: : : : 1
Thus output sequence at Q is 1111......

(Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Ch-7 Page 268 Table 7.10)
8. Consider the given circuit.

A
CLK
In this circuit, the race around

(a) does not occure
(b) occurs when CLK = 0
(c) occurs when CLK = 1 and A = B = 1

(d) occurs when CLK = 1 and A = B = 0
GATE(IN/2012/1M)
8. Ans.(a)
CLK
Given circuit is a SR flip-flop in which race around condition is not observed. Race aound condition is charac-
teristic of JK flip-flop when J = K = 1.
9. The state transition diagram for the logic circuit shown is
2:1 MUX
D Q X1
Y
CLK Q X0
select
A
A= 1 A= 0
A= 1
(a) Q = 0 Q=1
A= 0
A= 0 A= 0
A= 1
(b) Q = 0 Q=1
A= 1
A= 0 A= 1
A= 0
(c) Q = 0 Q=1
A= 1
A= 1 A= 1
A= 0
(d) Q = 0 Q=1
A= 0
GATE(IN/2012/2M)
9. Ans.(d)
2:1 MUX
D Q X1
Y
CLK Q X0
select
Truth table of MUX:
Select input MUX output

A Y
0 X0
1 X1
Output of MUX can be given as,
Y = X o A  X1A
From given circuit,
X1 = Q, X0 = Q , D = Y
 Y = QA  QA
Input of flip-flop, D = Y
Truth table of complete circuit,
Qn A X1 X0 Y D Q n 1
0 0 0 1 1 1 1
0 1 0 1 0 0 0
1 0 1 0 0 0 0
1 1 1 0 1 1 1
State transition table of the circuit can be derived from above table as under,
A Q n 1
0 Qn
1 Qn
State transition diagram of the circuit can be drawn as under,

A= 1 A= 1
A= 0
Q=0 Q=1
A= 0
10. The digital circuit shown below uses two negative edge–triggered D–flip–flops. Assuming initial condition of
Q1 and Q0 as zero, the Q1Q0 of this circuit is
Q1 Q0
D1 D0
D-Flip-flop D-Flip-flop
clock
(a) 00,01,10,11,00.... (b) 00,01,11,10,00....
(c) 00,11,10,01,00.... (d) 00,01,11,11,00....
GATE(IN/2013/2M)
10. Ans.(b)
Q1 Q0
D1 D0
D-Flip-flop D-Flip-flop
clock
Truth table of D-Flip flop,

D Q
0 0
1 1
State table of the given circuit can be given as under,
Clock D1  Qo Do  Q1 Q1 Q1 Qo Qo
0   0 1 0 1
1 0 1 0 1 1 0
2 1 1 1 0 1 0
3 1 0 1 0 0 1
4 0 0 0 1 0 1
Thus the states of the cicuit Q1Q0 are 00,01,11,10,00.......

1. An R-S latch is a
(a) combinatorial circuit
(b) synchronous sequental circuit
(c) one bit memory element
(d) one clock delay element
GATE(EC/1995/1M)
1. Ans.(c)
S
Set Q
R Q
Reset
An R-S latch is a one bit memory element which can store one bit (either Q = 0 or Q =1) at a time.
Refer Modern Digital Electronics by R.P. Jain, 3rd edition ch-7, Page-239, (7.2)
2. In a J–K flip-flip we have J = Q and K = 1. (figure). Assuming the flip flop was initially cleared and then
clocked for 6 pulses, the sequence at the Q output will be
Q
J Q
1 K CLK Q
(a) 010000 (b) 011001

(c) 010010 (d) 010101
GATE(EC/1995/2M)
2. Ans.(d)
Q
J Q
1 K CLK Q
J = Q
K = 1
CLK Present state Next state

J K
PULSE (Q n ) (Q n 1 )
0 0 1 1
1 0 1 1 1
2 1 0 1 0
3 0 1 1 1
4 1 0 1 0
5 0 1 1 1
6 1 0 1 0
. . . . .
: : : : :
The sequence at the Q output is 010101

[(Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Ch-7 Page 268,7.6.1 Table-7.10)]
3. In figure A = 1 and B = 1, the input B is now replaced by a sequence 101010......., the outputs X and Y will be
A X
B Y
(a) fixed at 0 and 1, respectively
(b) X = 1010 ....... while Y = 0101 .........
(c) X = 1010 ........ and Y = 1010 .........
(d) fixed at 1 and 0, respectively
GATE(EC/1998/2M)
3. Ans.(a)
A
1 X
2 Y
B
Above circuit is SR latch with NAND gates with A = S, B = R , X = Q and Y = Q . Truth table of the SR latch
is given as,
NAND Latch
S  A R  B Qn 1  X Qn 1  Y
0 0 1 1
0 1 1 0
1 0 0 1
1 1 Qn Qn
When input A of the circuit is 1 and B chages in the sequence 101010........ the outputs X and Y will hold the
current state initially then it remains at (0,1) after the instant when B becomes 0. The outputs for given
sequence of inputs can be given as under,
A B x y
1 1  
1 0 0 1
1 1 0 1
1 0 0 1
1 1 0 1
: : : :
: : : :
At every instant when inputs A and B change from (1,0) to (1,1) the output X and Y remain in hold state at (0,1).
Refer Modern Digital Electronics by R.P. Jain, 3nd edition, Page 240( 7.3)
4. A sequential circuit using D Flip-Flop and logic gates is shown in Fig., where X and Y are the input and Z is the
output. The circuit is
X
D Q Z
Y CLK
Q Z
(a) S – R Flip-Flop with inputs X = R and Y= S

(b) S – R Flip-Flop with inputs X = S and Y=R
(c) J – K Flip-Flop with inputs X = J and Y = K
(d) J – K Flip-Flop with inputs X = K and Y=J
GATE(EC/2000/2M)
4. Ans.(d)
X
D Q Z
CLK
Y Z
Q
From the given circuit

D = XZ  YZ
The truth table for the given circuit can be drawn as follows
Table - 1
Pr evious State Next state
Y X D Operation
(Q n 1 ) (Q n 1 )
0 0 Qn Z  Qn No change Qn
0 1 Qn 0 Reset 0
1 0 Qn 1 Set 1
1 1 Qn Z  Qn Toggle Qn
The truth table of J-K flip flop is shown below
Table - 2
CLK J K Q n 1 Action
1 0 0 Qn No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Qn Toggle
By comparing the truth tables 1 and 2, we conclude that the given circuit is J-K flip flop with inputs X = K
and Y = J.
[(Refer Digital Circuits and Design by S.Salivahanan, 2nd edition Ch-7, Pg. 284, 7.11.5)]
5. The digital block in figure is realized using two positive edge triggered D-flip-flops. Assume that for t < t0, Q1 =
Q2 = 0. The circuit in the digital block is given by:
X Digital Y
block
t0 t1 t2 t3 t0 t1 t2 t3 t4
(a)
1 D1 Q1 1 D2 Q2 Y
X
Q1 Q2
(b)
1 D1 Q1 1 D2 Q2 Y
X
Q1 Q2
(c)
1 D1 Q1 D2 Q2 Y
X
Q1 Q2
(d)
1 D1 Q1 D2 Q2 Y
X
Q1 Q2
GATE(EC/2001/2M)
5. Ans.(c)
circuit (a)
1 D1 Q1 1 D2 Q2 Y
X Q1 Q2
X
t0 t1 t2 t3 t4
Q1
t0
Q2
t1
Both the flip Flops are positive edge triggered. So, the change in Q1 occurs on positive going edge of X change
in Q2 occurs on positive going edge of Q1
Circuit (b)
1 D1 Q1 1 D2 Q2 Y
X Q1 Q2
X
t0 t1 t2 t3
Q1
Q2
Both the Flip Flops are negative edge triggered. change in Q1 occurs on negative going edge of X and change
in Q2 occurs on negative going edge of Q1
Circuit (c)
1 D1 Q1 D2 Q2 Y
X Q1 Q2
From this figure we observe that both the flip flops are positive edge triggered.
Hence change in states Q1 and Q2 occur only on the positive going edge of wave form of X because clocks of
both flip flops are connected to X.
X
t0 t1 t2 t3
D1
1
Q1 1
Now the important points is that the changed in Q1 from 0 to 1 occurs after a time to from time that is
equal to propagation delay time of first flip flop.
Redrawing the wave forms, we get
X
t0 t1 t2 t3
D1 1
Q1
0
st
t0
Q1  D 2
Q2
Initially Q2= 0 At point to, D2 = Q1  1

Hence Q2 becomes 1 after a propagation delay of FF-2. Again at t1, D2 = Q1  0
Hence Q2 becomes Zero after a propagation delay
Circuit (d)
1 D1 Q1 D2 Q2 Y
X Q1 Q2
Here both the flip flops are negative edge triggered.
X
t0 t1 t2 t3
D1 1
Q1
t0
Q1  D 2
Q2 t1
Refer : Modern Digital Electronics by R.P Jain 3nd Edition, Ch-7, Page-246 (7.5)
6. A master-slave flip-flop has the characteristic that

(a) change in the input immediately reflected in the output
(b) change in the output occurs when the state of the master is affected
(c) change in the output occurs when the state of the slave is affected
(d) both the master and the slave states are affected at the same time
GATE(EC/2004/1M)
6. Ans.(c)
A master slave flip flop has the characteristic that change in output occurs when the state of the slave is
affected.
[(Refer Digital Circuits and Design by S.Salivahanan, 2ndedition / Ch-7,Page 276, 7.10.2)]
7. The present output Qn of an edge triggered JK

flip-flop is logic 0. If J = 1, then Qn + 1
(a) cannot be determined
(b) will be logic 0
(c) will be logic 1
(d) will race around
GATE(EC/2005/2M)
7. Ans.(c)
The state table for J-K flip flop is given as,
PS Inputs NS
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Hence Qn+1 will be logic 1 when J = 1 and Qn = 0.

[(Refer Digital Circuits and Design by S.Salivahanan, Ch-7/ Page-268 Table 7.10)]
8. The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the
sequence indicated below:
X =0, Y = 1; X = 0, Y = 0; X = 1, Y = 1.
The corresponding stable P, Q outputs will be
X P
Y Q
(a) P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or
P = 0, Q = 1,
(b) P = 1, Q = 0; P = 0, Q = 1 or P= 0, Q =1;
P = 0, Q = 1
(c) P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or
P = 0, Q = 1
(d) P =1, Q = 0; P = 1, Q =1; P = 1, Q = 1
GATE(EC/2007/2M)
8. Ans.(d)
X P
Y Q
Above circuit is SR latch with NAND gates with X = S, Y = R , P = Q and Q = Q . Truth table of the SR latch
is given as,
NAND Latch
S  X R  Y Q n 1  P Q n 1  Q
0 0 1 1
0 1 1 0
1 0 0 1
1 1 Qn Qn
When inputs X and Y are changed from (0,1) to (0,0) to (1,1) the outputs can be obtained using above truth table
as under, :
X Y P Q
0 1 1 0
0 0 1 1
1 1 Qn Qn
When inputs X and Y of the latch are change from (0,0) to (1,1) the output holds the previous state which is
(1,1) for the given sequence. So, for the given sequence of inputs the states of output P and Q are (1,0), (1,1)
and (1,1).
Refer Digital Logic & Computer Design M.Morris Mano, Pg 205
9. For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate
delays to be negligible.
1
0 CLK
1 D Q
0
Q
Which of the following statement is true

(a) Q goes to 1 at the CLK transition and stays
at 1
(b) Q goes to 0 at the CLK transition and stays at 0
(c) Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
(d) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1.
GATE(EC/2008/2M)
9. Ans.(c)
NOR latch
1
0 CLK
D S
1 Q
0
Q
R
The output stage of the given circuit is a NOR latch whose turth table is as given below,
NOR Latch
S R Q n 1 Qn 1
0 0 Qn Qn
0 1 0 1
1 0 1 0
1 1 0 0
Case-1: When CLK = 1 and D = 0

Then, D  1
The figure reduces to,
0
Q
Q
0
It is clear from truth table of NOR latch that if S = R = 0 the latch remains in hold state.
Case -2: When CLK changes from 1 to 0 and D =0
The figure reduces to
1
Q
Q
0
Q = 1 Q  0
Q = 1
It is clear from truth table of NOR latch that if S = 1and R = 0 the latch gives Q = 0 and Q = 1.
Thus, Q goes to 1 at the CLK transition
Case -3: When CLK = 0 and D changes from 0 to 1
The figure reduces to,
0
Q
Q
1
Q = 1 Q  0
It is clear from truth table of NOR latch that if S = 0and R = 1 the latch gives Q = 1 and Q = 0.
Thus, Q goes to 0 when D goes to 1.
Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, page-78, 3.3
10. For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is T.
1 J0 Q0 1 J1 Q1
CLK
1 K0 1 K1
CLK
1
0
T t
t1
Which of the following waveforms correctly represents the output at Q1 ?
1
(a) 0
2T
t 1  T
(b) 0
4T
t 1  2 T
(c) 0
2T
t 1 2T
(d) 0
4T
t 1  T
GATE(EC/2008/2M)
10. Ans.(b)
1 Jo Q0 1 J1 Q1
CLK
1 Ko 1 K1
Delay of one flip-flop = T

Delay of two flip-flops = 2T
Truth table of JK flip-flop,
J K Q n 1
0 0 Qn
0 1 0
1 0 1
1 1 Qn
Output of flip-flop is complemented when J = K = 1.

Delay between Q1 and CLK = 2T
So, Q1 appears at instant = t1 + 2T
As each flip-flop is positive edge triggered so each output of flip-flop changes its state only at positive edge of
CLK. Each flip-flop performs divide by 2 operation. So frequency of Q0 is half of input CLK and frequency of
Q1 is half of Q0 and one fourth of CLK. The waveforms of CLK, Q0 and Q1 can be drawn as under.
CLK
t1 T t
Q0
2T
t1 t
Q1
t1 t
4T
Thus waveform of Q1 is as in option ‘b’.
11. Refer to the NAND and NOR latches shown in the figure. The inputs (P1,P2) for both the latches are first
made (0,1) and then, after a few seconds, made (1,1). The corresponding stable outputs (Q1,Q2) are
P1
Q1
P2
Q2
P1
Q1
P2 Q2
(a) NAND first (0,1) then (0,1) NOR : first (1,0) then (0,0)
(b) NAND first (1,0) then (1,0) NOR : first (1,0) then (1,0)
(c) NAND first (1,0) then (1,0) NOR : (1,0) then (0,0)
(d) NAND first (1,0) then (1,1) NOR : first (0,1) then (0,1)
GATE(EC/2009/2M)
11. Ans.(c)
P1= S P1= S
1 Q1 = Q 1 Q1 = Q
2 Q2 = Q 2 Q2 = Q
P 2= R P 2= R
NAND GATE LATCH NOR GATE LATCH
Given latches are S-R latches. For the NAND latch, S = P1 , R = P2, Q = Q1 & Q = Q2 and for the NOR latch,
S = P1 , R = P2, Q = Q2 & Q = Q1
Truth table of NAND and NOR latches are as follows,
NAND Latch NOR Latch
S  P1 R  P2 Q n 1  Q1 Qn 1  Q 2 S  P1 R  P2 Q n 1  Q2 Qn 1  Q1
0 0 1 1 0 0 Qn Qn
0 1 1 0 0 1 0 1
1 0 0 1 1 0 1 0
1 1 Qn Qn 1 1 0 0
It is observed from above tables that output of NAND latch (Q1,Q2) is (1, 0) and that of NOR latch (Q1,Q2) is
(1,0) when inputs (P1,P2) are (0,1). When the input is chaged from (0,1) to (1,1) the output of NOR latch
becomes (0,0) and NAND latch holds the previous state at (1,0).
CLK

(a) does not occurs
GATE(EC/2012/1M)
12. Ans.(a)
CLK
2:1 MUX
D Q X1
Y
CLK Q X0
select
A= 1 A= 0
A= 1
(a)
Q=0 Q=1
A= 0
A= 0 A= 0
A= 1
(b)
Q=0 Q=1
A= 1
A= 0 A= 1
A= 0
(c)
Q=0 Q=1
A= 1
A= 1 A= 1
A= 0
(d)
Q=0 Q=1
A= 0
GATE(EC/2012/2M)
13. Ans.(d)
2:1 MUX
D Q X1
Y
CLK Q X0
select
Truth table of MUX:

A Y
0 X0
1 X1
Y = X o A  X1A
From given circuit,
X1 = Q, X0 = Q , D = Y
 Y = QA  QA
Input of flip-flop,D = Y
Qn A X1 X0 Y D Q n 1
0 0 0 1 1 1 1
0 1 0 1 0 0 0
1 0 1 0 0 0 0
1 1 1 0 1 1 1
A Q n 1
0 Qn
1 Qn
A= 1 A= 1
A= 0
Q=0 Q=1
A= 0
1. For a flip-flop formed from two NAND gates as shown in figure the unusable state corresponds to
X
0
(a) X = 0, Y = 0 (b) X = 0, Y = 1
(c) X = 1, Y = 0 (d) X = 1, Y = 1
GATE(EE/1999/2M)
1. Ans.(a)
X Q
Y Q
Above circuit is SR latch with NAND gates with X = S, Y = R . Truth table of the SR latch is given as,
NAND Latch
X S Y R Q n 1
0 0 Q n  Q n  1 Invalid state
0 1 1 Set state
1 0 0 Reset state
1 1 Qn Hold State
Thus the unusable state occurs when X = 0 and Y = 0.

Refer Modern Digital Electronics by R.P. Jain, 3nd edition, Page 240, 7.3
2. The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 kHz. The
frequency of the signal available at Q is
D Q
Q
CLK
10 kHz
(a) 10 kHz (b) 2.5 kHz
(c) 20 kHz (d) 5 kHz
GATE(EE/2002/1M)
2. Ans.(d)
D Q
CLK Q
10 kHz
The state table for D flip flop is shown below,
CLK Q n D Q n 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
For the given logic circuit, D = Q . Let initially the state of D flip flip Q = 0 then D = 1.
Then the state table for the given circuit becomes as under,
CLK D  Qn Q n 1 Qn 1
1 1 1 0
2 0 0 1
3 1 1 0
4 0 0 1
5 1 1 0
. . . .
. . . .
This is a positive edge triggered flip flop so output chages its state at positive edge of clock pulse. The waveform
of ouput becomes as under,
CLK
input
Thus the frequency of the signal available at Q is half of the frequency of the clock signal
 he frequency at Q is 5 kHz
[(Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Ch-7 Page 287, 7.12.3)]
3. An X-Y flip flop, whose Characteristic Table is given below is to be implemented using a J-K flip flop
X Y Q n 1
0 0 1
0 1 Qn
1 0 Qn
1 1 0
This can be done by making

(a) J  X, K  Y (b) J  X , K  Y
(c) J  Y, K  X (d) J  Y , K  X
GATE(EE/2003/2M)
3. Ans.(d)
We have to implement XY Flip-Flop using JK Flip Flop.
The state table of XY Flip Flop can be drawn as shown,
Qn X Y Q n 1
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
The state table for JK Flip Flop is shown below
Qn J K Q n 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Using state table the state table of JK Flip Flop the excitation table can be obtained as under,
Qn Q n 1 J K
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0
Using the excitation table of JK Flip Flop the next state codes, can be augmented in PS-NS table of XY Flip
Flop as shown below
Qn X Y Q n 1 J K
0 0 0 1 1 d
0 0 1 0 0 d
0 1 0 1 1 d
0 1 1 0 0 d
1 0 0 1 d 0
1 0 1 1 d 0
1 1 0 0 d 1
1 1 1 0 d 1
Excitation map for input J :

XY
Qn 00 01 11 10
0 1 1
1 d d d d
J = Y
Excitation map for input K:
XY
Qn 00 01 11 10
0 d d d d
1 1 1
K = X
Hence X-Y Flip Flop can be implemented using a J-K Flip Flop by making
J = Y,K=X
(Refer Digital Circuits and Design by S.Salivahanan, 2nd edition Ch-7, Pg. 278, 7.11.1)
4. The digital circuit shown in figure generates a modified clock pulse at the output. Choose the correct output
waveform from the options given below.
PR =1
1 J Q
O/P
CLK
1 K Q
CLR =1
CLK
(a)
(b)
(c)
(d)
GATE(EE/2004/2M)
4. Ans.(b,d)
PR =1
1 J Q
O/P
CLK
1 K Q
CLR =1
Truth Table of Truth Table of JK

AND gates. flip flop :
Q CLK O / P J K Q n 1
0 0 0 0 0 Qn
0 1 0 0 1 0
1 0 0 1 0 1
1 1 1 1 1 Qn
It is observed that output of AND gate is zero when one of the input is zero. So output of AND gate is zero
when clock signal is zero irrespective of state of Q. And output of gate is Q when clock signal is at logic ‘1’.
Initially the clock signal is at logic ‘0’ so the output of AND gate is zero. The output Q of JK flip flop toggles
at negative edge of each clock pulse when J = K = 1. The waveforms of CLK, Q and O/P are as under,
Case - I : When initial state Q = 0
CLK
O/P
Case - II : When initial state Q = 1
CLK
O/P
5. The digital circuit shown in figure works as a
D Q
X
CLK Q
(a) JK flip-flop (b) Clocked RS flip-flop

(c) T flip-flop (d) Ring counter
GATE(EE/2005/1M)
5. Ans.(c)
X D Q
CLK Q
From the circuit diagram, D = X Q

Let Qn denotes the present state and Qn+1 denotes the next state of D flip flop then state table of the circuit can
be drawn as under,
Qn X D Q n 1
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
Now if taken X as input of the circuit then we can redraw the table again as
Qn X Q n 1
0 0 0
0 1 1
1 0 1
1 1 0
The above table represents a T flip flop. Hence the digital circuit works as T flip flop.
Refer Digital Circuits and Design by S.Salivahanan, 2nd edition, Page-277(7.11)
6. Select the circuit which will produce the given output Q for the input signals X1 and X2 given in figure.
X1
t
X2
t
Q t
X1 X1
Q Q
(a) (b)
X2 X2
X1 X1
Q Q
(c) (d)
X2 X2
GATE(EE/2005/2M)
6. Ans.(*)
1
X1
0
1
X2
0
1
Q
0
t
Fram given wafeform of input and output signals the truth table of the circuit can be drawn as under
X2 X1 Q
0 1 1
0 0 1
1 0 0
Circuit 1 :
X1
Q
Truth table of the circuit
X2 X1 Q
0 1 0
1 0 1
X2
Truth lable of circuit 1 does not match with truth table of waveforms.
Circuit 2 :
X1
Q Truth table of the circuit
X2 X1 Q
0 1 1
0 0 0or1
X2 1 0 1
Truth table of circuit 2 does not match with truth table of waveforms
Circuit 3 :
X1 Q Truth table of the circuit
X2 X1 Q
0 1 1
0 0 0
X2 1 1 0 0
Truth table of circuit does not match with truth table of waveform.
Circuit 4 :
X1 Q Truth table of the circuit
X2 X1 Q
0 1 0or1
0 0 0
X2 1 1 0 0
Truth table of circuit does not match with truth table of waveform.
So, none of the options produces the desired output

A
CLK
B
(a) does not occure

GATE(EE/2012/1M)
7. Ans.(a)
A
CLK
2:1 MUX
D Q X1
Y
CLK Q X0select
A= 1 A= 0
A= 1
(a) Q = 0 Q=1
A= 0
A= 0 A= 0
A= 1
(b) Q = 0 Q=1
A= 1
A= 0 A= 1
A= 0
(c) Q = 0 Q=1
A= 1
A= 1 A= 1
A= 0
(d) Q = 0 Q=1
A= 0
GATE(EE/2012/2M)
8. Ans.(d)
2:1 MUX
D Q X1
Y
CLK Q X0
select
Truth table of MUX:

A Y
0 X0
1 X1
Y = X o A  X1A
From given circuit,
X 1 = Q, X0 = Q , D = Y
 Y = QA  QA
Input of flip-flop ,D = Y
Qn A X1 X 0 Y D Q n 1
0 0 0 1 1 1 1
0 1 0 1 0 0 0
1 0 1 0 0 0 0
1 1 1 0 1 1 1
A Q n 1
0 Qn
1 Qn
A= 1 A= 1
A= 0
Q=0 Q=1
A= 0
9. The clock frequency applied to the digital circuit shown in the figure is 1 kHz. If the initial state of the output Q
of the flip – flop is ‘0’, then the frequency of the output waveform Q in kHz is
(a) 0.25 (b) 0.5
(c) 1 (d) 2
GATE(EE/2013/2M)
9. Ans.(b)
R
X
T Q Q
S
CLK
Q Q
Initial condition of output, Q = 0

Given flip-flop is a negative edge triggered toggle flip-flop. So output Q toggles at every negative edge of clock
when T = 1.
Truth table of XOR gate,
A B R
0 0 0
0 1 1
1 0 1
1 1 0
Truth table of XNOR gate
A B S
0 0 1
0 1 0
1 0 0
1 1 1
Truth table of NAND gate,
R S X
0 0 1
0 1 1
1 0 1
1 1 0
Using above truth tables of XOR, XNOR and NAND gates the truth table of circuit can be drawn as under,
Clk Q Q R S X  T
0 0 1 1 0 1
1 1 0 1 0 1
2 0 1 1 0 1
3 1 0 1 0 1
4 0 1 1 0 1
     
It is observed from truth table that input X of flip-flop is alway ‘1’. So output of flip-flop toggles at every
negative edge of clock input. The waveforms of Q, Q , X, R, S and CLK can be drawn as shown below,,
1
CLK
0 t
1
Q
0 t
Q 1
0 t
R 1
0 t
S 1
0 t
T=X 1
0 t
It is observed from waveforms that the frequency of output is half of frequency of clock signal. If the fre-
quency of clock is 1kHz then frequency of Q is 0.5 kHz.
16. Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of 1 MHz are
applied as shown. The frequency (in kHz) of the wave form at Q3 is______
1 1 1 J2 1 1
J4 Q4 J3 Q3 Q2 J1 Q1 J0 Q0
clk clk clk clk clk
1 K4 1 K2 K2 1 K1 K0
1 1
GATE(EC-I/2014/1M)
16. Ans.: 62.4 to 62.6
42. The digital logic shown in the figure satisfies the given state diagram when Q1 is connected to input A of the
XOR gate.
A
D1 Q1 D2 Q2
CLK Q1 S Q2
s=0
s=1
00 01
s=0 s=1
s=1 s=0
10 11
s=1
s=0
Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state
diagram ?
(a) input A is connected to Q2
(b) Input A is connected to Q2
(c) Input A is connected to Q1 and S is complemented
(d) Input A is connected to Q1
GATE(EC-I/2014/2M)
42. Ans.(d)
41. The outputs of the two flilp-flops Q1-Q2 in the figure shown are initialized to 0, 0. The sequence generated at
Q1 upon aplication of clock signal is
Q1
J1 Q1 J2 Q2
K1 Q1 K2 Q2
CLK
(a) 01110... (b) 01010....

(c) 00110... (d) 01100....
GATE(EC-II/2014/2M)
41. Ans.(d)
40. In the circuit shown, choose the correct timing diagram of the output(y) from the given waveforms W1, W2,
W3 and W4
x1 D Q
FF1
Clk Q
Output(y)
x2 D Q
FF2
Q
Clk
X1
X2
W1
W2
W3
W4
(a) W 1 (b) W 2
(c) W 3 (d) W 4
GATE(EC-II/2014/2M)
40. Ans.(c)
15. The circuit shown in the figure is a
D
Q Q
D Latch D Latch
En En
Q Q
ClK
(a) Toggle flip flop

(b) JK flip Flop
(c) SR Latch
(d) master- Slave D Flip Flop
GATE(EC-III/2014/1M)
Ans (d)
51. A JK flip flop can be implemented by T flip-flops. Identify the correct implementation
J T Qn
(a)
Clk
K T flip-flop –
Qn
J T
Qn
(b)
Clk
K T flip-flop –
Qn
J T
Qn
(c)
Clk
K T flip-flop –
Qn
J T Qn
(d) Clk
K T flip-flop –
Qn
GATE(EE-II/2014/2M)
51. Ans. (b)
21. A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where X is the don’t
care condition,k and Q is the output representing the state.
0X/1, 10/1
11/0 Q=0 Q=1 0X/1, 10/1
11/0
The logic gate represented by the state diagram is
(a) XOR (b) OR
(c) AND (d) NAND
GATE(EE-III/2014/1M)
21. Ans ()
48. An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are
provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch
can be made functional by changing.
Q
Set
5V
Q
Reset
(a) NOR gates to NAND gates

(b) inverters to buffers
(c) NOR gates to NAND gates and inverters to buffers
(d) 5 V to ground
GATE(EE-III/2015/2M)
Ans. (d)
46. A three bit pseudo random number generator is shown. Initially the value of output Y  Y2Y1Y0 is set to 111.
The value of output Y after three clock cycles is
Y2 Y1 Y0
D2 Q2 D1 Q1 D0 Q0
CLK
(a) 000 (b) 001

(c) 010 (d) 100
GATE(EC-III/2015/2M)
Ans. (d)
47. The figure shows a digital circuit constructed using negative edge triggered J-K flip flops. Assume a starting
state of Q2 Q1 Q0 = 000. This state Q2 Q1 Q0 = 000 will repeat after ........ number of cycles of the clock
CLK.
1
J0 Q0 J1 Q1 J2 Q2
CLK Clock Clock Clock
1 K 1
K0 Q0 1 Q1 K2 Q2
1
GATE(EE-I/2015/2M)
Ans. 6
47. In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q1 Q0 = 00. The
state (Q1 Q0), immediately after the 333rd clock pulse is
Q0 Q1
J0 Q0 J1 Q1
K0 Q0 K1 Q1
CLK
(a) 00 (b) 01
(c) 10 (d) 11
GATE(EE-II/2015/2M)
Ans. (b)
36. The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller
than the delay of the JK flip-flop. The next state of the system is
CLK
(a) 00 (b) 01
(c) 11 (d) 10
GATE(EE-I/2016/2M)
Ans. (c)
17. Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R = 10 k and the
supply voltage is 5 V. The D flip-flops D1, D2, D3, D4 and D5 are initialized with logic values 0, 1, 0, 1 and 0,
respectively. The clock has a 30% duty cycle.
D Q D Q D Q D Q D Q R=
D1 D2 D3 D4 D5 10k
Clock
The average power dissipated (in mW) in the resistor R is .............
GATE(EC-II/2016/1M)
Ans. 1.45:1.55
44. The state transition diagram for a finite state machine with states A, B and C, and binary inputs X, Y and Z, is
shown in the figure.
X = 0 , Y = 0, Z= 0
Y =1
A B Y =1
Y= 0 , Z = 0
Y= 1 ,
X=0 , Z =1 X=1 ,
Z =1
Z =1
X =1 , Y = 0 Y= 0 , Z = 1
Z=0
Which one of the following statements is correct?
(a) Transitions from State A are ambiguously defined.

(b) Transitions from State B are ambiguously defined.
(c) Transitions from State C are ambiguously defined.
(d) All of the state transitions are defined unambiguously.
GATE(EC-II/2016/2M)
Ans. (c)
15. In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input
condition is: P = Q = ‘0’. If the input condition is changed simultaneously to
P = Q = ‘1’, the outputs X and Y are
P
X
Y
Q
(A) X = ‘1’ , Y = ‘1’

(B) either X = ‘1’, Y = ‘0’ or X = ‘0’, Y = ‘1’
(C) either X = ‘1’, Y = ]1’ or X = ‘0’, Y = ‘0’
(D) X = ‘0’, Y = ‘0’
GATE(EC-I/2017/1M)
15. Ans. : B
17. Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero
propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period
delayed version of CLK1. The duty cycle at the output latch in percentage is ___________.
TCIK CLK1 D Q
CLK1 D-Latch
CLK2 CK
CLK2
TCIK/5
GATE(EC-I/2017/1M)
17. Ans. : 29.9 to 30.1

46. A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the
figure below. The four possible states of the FSM are QA QB 00, 01, 10 and 11.
QA QB
D Q D Q
A B
CK Q CK Q
XIN
CLK
Assume that X1N is held at a constant logic level throughout the operation of the FSM. When the FSM is
initialized to the state QAQB = 00 and clocked, after a few clock cycles, it starts cycling through
(A) all of the four possible states if X1N = 1

(B) three of the four possible states if X1N = 0
(C) only two of the four possible states if X1N = 1
(D) only two of the four possible states if X1N = 0
GATE(EC-I/2017/2M)
46. Ans. : D
43. The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is
shown in the figure. The FSM has an input „In. and an output „Out.. The initial state of the FSM is S0.
If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1
is ________.
In = 0
00 Out = 0
S0
In = 1
In = 0 Out = 0
In = 1
Out = 0 Out = 0 01
S1 In = 0
Out = 0
In = 1
10 Out = 0
S2 In = 1
In = 0 Out = 1
Out = 0
11
S3
GATE(EC-II/2017/2M)
43. Ans. : 4
49. For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions QAQBQC = QA
QB QC = 100
D Q D Q D Q
Q Q Q
[MSB] QA QB QC
clock
Z
[MSB] QA Q B Q C
D Q D Q D Q
Q Q Q
The minimum number of clock cycles after which the output Z would again become zero is ________.
GATE(EE-II/2017/2M)
49. Ans. : 6
43. The two inputs A and B are connected to an
R-S latch via two AND gates as shown in the figure. If A =1 and B = 0, the output QQ is
A
S Q
Q
Q
R Q
B
R-L Latch
(A) 00 (B) 10
(C) 01 (D) 11
GATE(IN/2017/2M)
43. Ans. : B
19. A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle,
GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for 75
seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this
FSM is a clock of 5 second period.
The minimum number of flip-flops required to implement this FSM is _______.
GATE(EC/2018/1M)
19. Ans.(5 to 5)
46. In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data Din using
clock CK. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit
and clock periods are equal and the value of T/TCK = 0.15, where the parameters T and TCK are shown
in the figure. Assume that the Flip-Flop and the XOR gate are ideal.
X
Din D Q
CLK
CK
TCK
CK
Din
T T T
If the probability of input data bit (Din) transition in each clock period is 0.3, the average value (in volts,
accurate to two decimal places) of the voltage at node X, is _______.
GATE(EC/2018/2M)
46. Ans.(0.82 to 0.86)
12. The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with
outputs X and Y. If the initial state of the output is X = 0 and Y = 0 just before the arrival of the first clock
pulse, the state of the output just before the arrival of the second clock pulse is
1 J Q 1 J Q
CLK CLK
K K X Y
1 1
Output
(a) X = 0, Y = 0 (c) X = 1, Y = 0
(b) X = 0, Y = 1 (d) X = 1, Y = 1
GATE(IN/2019/1M)
12. Ans.(d)
1 J1 Q1 1 J2 Q2
CLK CLK
K1 K2 X Y
1 1
FF1 FF2
Initial state, Q1 = 0 & Q2 = 0.

The output of JK flip-flop toggle at arrival of each clock pulse when J = K = 1. The given flip-flops are
positive edge triggered so the output of flip-flops toggle at positive edge of clock pulse. So, the waveforms of
CLK, Q1 and Q2 signals of above circuit can be drawn as under,
1
CLK
0
1
Y = Q1 1 0
0
1
X = Q2 1 1
0
It is seen from the above waveforms that the state of FFs just before arrival of second clock pulse is,
X = 1, Y = 1
39. The state transition diagram for the circuit shown is
D Q 1
Q 0
CLK A
(a)
A= 0 A= 0
A=1
Q=0 Q=1
A=1
(b)
A= 0
A= 0
A= 1
Q=0 Q=1
A= 1
(c)
A= 0
A= 0
A= 1
Q=0 Q=1
A= 1
(d)
A= 1 A= 0
A=0
Q=0 Q=1
A=1
GATE(EC/2019/2M)
39. Ans.(c)
D Q 1
MUX
Y
Q 0
CLK A
Output of MUX,
Y = AQ  AQ
Output of NAND gate,
D = QY
Truth table of the circuit,
A Qn Y D Qn 1
0 0 1 1 1
0 1 0 1 1
1 0 0 1 1
1 1 1 0 0
State transition diagram of the given circuit can be drawn as under,
A= 0
A= 0
A= 1
Q=0 Q=1
A= 1
Flip Flops & Sequential Circuits DIGITAL ELECTRONICS [64]
15. A sequence detector is designed to detect precisely 3 digital inputs, with overlapping sequences detectable. For
the sequence (1, 0, 1) and input data (1,1, 0,1,0,0,1,1,0,1,0,1,1,0), what is the output of this detector?
(a) 1,1,0,0,0,0,1,1,0,1,0,0
(b) 0,1,0,0,0,0,0,1,0,1,0,0
(c) 0,1,0,0,0,0,0,1,0,1,1,0
(d) 0,1,0,0,0,0,0,0,1,0,0,0
GATE(EE/2020/1M)
15. Ans(b)
40. Two T-flip flops are interconnected as shown in the figure. The present state of the flip flops are : A = 1, B = 1.
The input x is given as 1, 0, 1 in the next three clock cycles. The decimal equivalent of (ABy)2 with A being
the MSB and y being the LSB, after the 3rd clock cycle is ________.
TA A y
clk
TB B
clk
clk
GATE(IN/2020/2M)
40. Ans.(7 to 7)
39. The state diagram of a sequence detector is shown below. State S0 is the initial state of the sequence detector.
If the output is 1, then
0/0
1/0 0/0
S0 S1 S2 S3
0/0 1/0 0/0
1/0
S4
1/0
0/1
1/0
(a) the sequence 01010 is detected
(b) the sequence 01011 is detected
(d) the sequence 01110 is detected
(c) the sequence 01001 is detected
GATE(EC/2020/2M)
39. Ans(a)
50. For the components in the sequential circuit shown below, tpd is the propagation delay, tsetup is the setup time,
and thold is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given
circuit can operate reliably, is _______ MHz.
Flip Flops & Sequential Circuits DIGITAL ELECTRONICS [65]
Flip Flop1
tpd = 2 ns Ipd = 2 ns
tpd = 3 ns
tsetup = 5 ns
thold = 1 ns
Clk
IN
Flip Flop2
tpd = 8 ns
tsetup = 4 ns
thold = 3 ns
GATE(EC/2020/2M)
50. Ans(76 to 78)

Sequential Circuits and Flip Flops

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6

Sequential Logic and Flip Flops

6.4.1 Basic Latches

B) S-R Using NAND

6.4.2 Clocked SR flip-flop

(b) Truth Table :

(d) State equation / characteristics equation :

(h) S-R Flip-Flip as Toggle switch :

6.4.3 D-Flip-Flop /Delay Flip-Flop/Data transfer Flip-Flop

(c) Truth Table :

(d) State Table /characteristic Table :

* Difference between Latch and Flip-Flop :

(d) State Table/characteristic Table :

6.4.5 T – Flip-Flop : (T stands for trigger or toggle)

(c) Truth Table :

Note : T – Flip-Flop is divide by two device.

6.5 Triggering of Flip-Flops

(a)Positive edge Triggering

Note : RC < < T

Note : SR, JK, D and T are called synchronous inputs

This can be achieved by following two methods :

Master FF is triggered when CLK = 1 and slave

D = Q n J  Q n K [same as state equation of JK Flip-Flop]

6.10 Applications of Flip-Flops

For divide by 2 n , no. of flip- flops required = n

GATE Practice Questions

1. The output Qn + 1 of a J-K flip-flop for the input J = 1, K = 1

The circuit shown is eqvivalent to NOR based SR Flip Flop

when S = 0, R = 0 the flip flop simply remains in its present state

(a) 00, 01, 10, 11, 00, 01, ......

Let initially Q1 = 0 So, Q1 = 1, and J1 = Q0 = 0

CLK Qo,n Jo,n= Q1,n K0,n Q0,n+1 J1,n K1,n Q1,n+1 = Y

Thus correct sequence of output of given master slave flip-flop is

(a) act as buffers

Set Reset Output Q n 1

If we draw the circuit as

Truth table of S-R latch,

Set Re set Output Q(n 1)

FF1 FF2 FF3

The opration of the above circuit is explained in the following table,

Pr esent State In puts Next State

(a) 0000... (b) 1010...

Truth table of J-K flip-flop is given as,

CLOCK Pr esent Next state

Thus output sequence at Q is 1111......

8. Consider the given circuit.

In this circuit, the race around

(c) occurs when CLK = 1 and A = B = 1

9. The state transition diagram for the logic circuit shown is

Truth table of MUX:

Select input MUX output

State transition diagram of the circuit can be drawn as under,

Q1 and Q0 as zero, the Q1Q0 of this circuit is

Truth table of D-Flip flop,

Thus the states of the cicuit Q1Q0 are 00,01,11,10,00.......

(a) 010000 (b) 011001

CLK Present state Next state

The sequence at the Q output is 010101

(a) S – R Flip-Flop with inputs X = R and Y= S

From the given circuit

Initially Q2= 0 At point to, D2 = Q1  1

Here both the flip flops are negative edge triggered.