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The Differential Amplifier

Asst. Prof. MONTREE SIRIPRUCHYANUN, D. Eng.

Dept. of Teacher Training in Electrical Engineering,
Faculty of Technical Education
King Mongkut’s Institute of Technology North Bangkok
http://www.te.kmitnb.ac.th/msn
mts@kmitnb.ac.th

BJT Differential Pair

• Differential pair circuits are one of the most

VCC
widely used circuit building blocks. The
input stage of every op amp is a differential αI/2 αI/2
amplifier RC RC
• Basic Characteristics
– Two matched transistors with emitters VCC-αIRC/2 VCC-αIRC/2
shorted together and connected to a
current source
I/2 I/2
– Devices must always be in active mode
– Amplifies the difference between the
two input voltages, but there is also a vCM
common mode amplification in the non- I vCM - 0.7
ideal case

• Let’s first qualitatively understand how this

circuit works.
– NOTE: This qualitative analysis also
applies for MOSFET differential pair
circuits

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Case 1

• Assume the inputs are shorted together to a common

VCC
voltage, vCM, called the common mode voltage
αI/2 αI/2
– equal currents flow through Q1 and Q2
– emitter voltages equal and at vCM-0.7 in order RC RC
for the devices to be in active mode
VCC-αIRC/2 VCC-αIRC/2
– collector currents are equal and so collector Q1 Q2
voltages are also equal for equal load resistors
– difference between collector voltages = 0 I/2 I/2

• What happens when we vary vCM?

vCM I vCM - 0.7
– As long as devices are in active mode, equal
currents flow through Q1 and Q2
– Note: current through Q1 and Q2 always add up
to I, current through the current source
– So, collector voltages do not change and
difference is still zero….
– Differential pair circuits thus reject common
mode signals

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Case 2 & 3

VCC
• Q2 base grounded and Q1 base at +1 V
αI 0
– All current flows through Q1
RC RC
– No current flows through Q2
– Emitter voltage at 0.3V and Q2’s EBJ not FB VCC-αIRC
Q1 Q2
– vC1 = VCC-αIRC +1V
– vC2 = VCC I 0
VCC
0 αI
RC RC I 0.3V

• Q2 base grounded and Q1 base at -1 V

VCC VCC-αIRC
-1V Q1 Q2 – All current flows through Q2
0 I – No current flows through Q1
– Emitter voltage at -0.7V and Q1’s EBJ not FB
– vC2 = VCC-αIRC
I -0.7V – vC1 = VCC

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Case 4

• Apply a small signal vi

– Causes a small positive ΔI to flow in Q1
– Requires small negative ΔI in Q2
• since IE1+IE2 = I
– Can be used as a linear amplifier for small
signals (ΔI is a function of vi)
• Differential pair responds to differences in the input
voltage
– Can entirely steer current from one side of the
diff pair to the other with a relatively small
voltage

• Let’s now take a quantitative look at the large-signal

operation of the differential pair

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BJT Diff Pair – Large-Signal Operation

• First look at the emitter currents when the emitters are tied together

• Some manipulations can lead to the following equations

• and there is the constraint:

• Given the exponential relationship, small differences in vB1,2 can cause all of the
current to flow through one side

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• Notice vB1-vB2 ~= 4VT enough to switch all of current from one side to the other
• For small-signal analysis, we are interested in the region we can approximate to
be linear
– small-signal condition: vB1-vB2 < VT/2

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BJT Diff Pair – Small-Signal Operation

• Look at the small-signal operation: small

differential signal vd is applied

multiply top and

bottom by

– expand the exponential and keep the

first two terms

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Differential Voltage Gain

• For small differential input signals, vd << 2VT, the collector currents are…

• We can now find the differential gain to be…

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BJT Diff Pair – Differential Half Circuit

• We can break apart the differential pair circuit into two half circuits – which then
looks like two common emitter circuits driven by +vd/2 and –vd/2

Virtual Ground

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Small-Signal Model of Diff Half Circuit

• We can then analyze the small-signal operation with the half circuit, but must
remember
– parameters rπ,gm, and ro are biased at I / 2
– input signal to the differential half circuit is vd/2

vc1
gmvπ
vd/2 rπ vπ ro RC

– voltage gain of the differential amplifier (output taken differentially) is equal

to the voltage gain of the half circuit

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Common-Mode Gain

• When we drive the differential pair with a common-mode signal, vCM, the
incremental resistance of the bias current effects circuit operation and results in
some gain (assumed to be 0 when R was infinite)

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Common Mode Rejection Ratio

• If the output is taken differentially, the output is zero since both sides move
together. However, if taken single-endedly, the common-mode gain is finite

• If we look at the differential gain on one side (single-ended), we get…

• Then, the common rejection ratio (CMRR) will be

– which is often expressed in dB

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CM and Differential Gain Equation

• Input signals to a differential pair usually consists of two components: common

mode (vCM) and differential(vd)

• Thus, the differential output signal will be in general…

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MOS Diff Pair

• The same basic analysis can be applied to a MOS

differential pair

– and the differential input voltage is

– With some algebra…

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• We get full switching of the current when…

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Another Way to Analyze MOS Differential Pairs

• Let’s investigate another

technique for analyzing the RD RD RD RD
MOS differential pair
Vout1 X Y Vout2 Vout1 X Y Vout2
• For the differential pair circuit
on the left (driven by two
independent signals), compute V Vin2 Vin1
in1
the output using superposition
I I
– Start with Vin1, set Vin2=0
and first solve for X w.r.t.
Vin1
– Reduces to a degenerated
common-source amp
– neglecting channel-length RD
modulation and body- RD RD
effect, RS = 1/gm2 Vout1 X
Vout1 X Y Vout2
– so…
M1
M2 Vin1
Vin1 RS
RS

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Cont’d

• Now, solve for Y w.r.t. Vin1

• Replace circuit within box with a Thevenin equivalent RD RD
– M1 is a source follower with VT=Vin1
Vout1 X Y Vout2
– RT=1/gm1
• The circuit reduces to a common-gate amplifier where… M1 M2

Vin1

• So, overall (assuming gm1 = gm2)

RD

by symmetry Y Vout2

RT

VT

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Differential Pair with MOS loads

• Can use load resistors or MOS devices as loads

– Diode-connected nMOS loads = 1/gm load resistance
• Load resistance looking into the source
– Diode-connected pMOS loads = 1/gm load resistance
• Load resistance looking into diode connected drain
– pMOS current source loads = ro load resistance
• Has higher gain than diode-connected loads
– pMOS current mirror
• Differential input and single-ended output

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Differential Pair with MOS Loads

Vb

Vout Vout

Vin Vin

I I

• Consider the above two MOS loads used in place of resistors

• Left:
– a diode connected pMOS has an effective resistance of 1/gmP

• Right:
– pMOS devices in saturation have effective resistance of roP

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Active-Loaded CMOS Differential Amplifier

• A commonly used amplifier topology in CMOS technologies

• Output is taken single-endedly for a differential input
– with a vid/2 at the gate of M1, i1 flows M3 M4

i1
vo
– i1 is also mirrored through the M3-M4 current mirror i1
i2
– a –vid/2 at the gate of M2 causes i2 to also flow through M2
M1 M2
vid
• Given that ID= I / 2 (nominally)
I

• The voltage at the output then is given by…

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Differential Amp with Linearized Gain

• Use source generation to make the gain linear with respect to the
differential input and independent of gm
– Can build in two ways…

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• Assuming a virtual ground at node X, we can draw the following small-signal

half circuit.
gmvπ
vid vπ ro RD vο

is RS vS

– Assume ro is very large (simplifies the math)

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Offsets in MOS Differential Pair

• There are 3 main sources of offset that affect the performance of MOS
differential pair circuits
– Mismatch in load resistors
– Mismatch in W/L of differential pair devices
– Mismatch in Vth of differential pair devices
• Let’s investigate each individually

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Resistor Mismatch

• For the differential pair circuit shown, consider the case

where RD1 RD2
– Load resistors are mismatched by ΔRD
VO

– All other device parameters are perfectly matched

• With both inputs grounded, I1 = I2= I/2, but VO is not zero I1 I2
due to differences in the voltages across the load resistors
I

– It is common to find the input-referred offset which is

calculated as

– since Ad = gmRD

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W/L Mismatch

• Now consider what happens when device sizes W/L are mismatched for the two
differential pair MOS devices M1 and M2

• This mismatch causes mismatch in the currents that flow through M1 and M2

– This mismatch results in VO

– So in the input referred offset is…

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Vt Mismatch

• Lastly, consider mismatches in the threshold voltage

• Again, currents I1 and I2 will differ according to the following saturation current
equation

– For small ΔVt << 2(VGS-Vth)

– Again, using VOS=VO/Ad (Ad = gmRD and VO =2ΔIRD) we get…

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Mismatch Summary

• The 3 sources of mismatch can be combined into one equation:

– arising from Vt, RD, and W/L mismatches

• Notice that offsets due to ΔRD and ΔW/L are functions of the overdrive
voltage VGS – Vt

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Asst. Prof. Dr. MONTREE SIRIPRUCHYANUN