Chapter 10 Differential Amplifiers

Chapter 10 Differential Amplifiers
 10.1 General Considerations
 10.2 Bipolar Differential Pair
 10.3 MOS Differential Pair
 10.4 Cascode Differential Amplifiers
 10.5 Common-Mode Rejection
 10.6 Differential Pair with Active Load
1
Audio Amplifier Example
 An audio amplifier is constructed as above that takes a

rectified AC voltage as its supply and amplifies an audio
signal from a microphone.
CH 10 Differential Amplifiers 2
“Humming” Noise in Audio Amplifier Example
 However, VCC contains a ripple from rectification that leaks

to the output and is perceived as a “humming” noise by the
user.
Supply Ripple Rejection
v X  Av vin  vr
vY  vr
v X  vY  Av vin
 Since both node X and Y contain the same ripple, their

difference will be free of ripple.
Ripple-Free Differential Output
 Since the signal is taken as a difference between two nodes,

an amplifier that senses differential signals is needed.
Common Inputs to Differential Amplifier
vY  Av vin  vr
v X  vY  0
 Signals cannot be applied in phase to the inputs of a

differential amplifier, since the outputs will also be in phase,
producing zero differential output.
Differential Inputs to Differential Amplifier
vY   Av vin  vr
v X  vY  2 Av vin
 When the inputs are applied differentially, the outputs are

180° out of phase; enhancing each other when sensed
differentially.
Differential Signals
 A pair of differential signals can be generated, among other

ways, by a transformer.
 Differential signals have the property that they share the
same average value (DC) to ground and AC values are
equal in magnitude but opposite in phase.
Single-ended vs. Differential Signals
Example 10.3
 Determine the common-mode level at the output of the circuit

shown in Fig. 10.3(b).
In the absence of signals,

VX  VY  VCC  RC I C
where RC  RC1  RC 2 and

I C denotes the bias current of Q1 and Q2
Thus, VCM  VCC  RC I C
Interestingly, the ripple affects VCM

but not the differential output.
Differential Pair
 With the addition of a tail current, the circuits above operate

as an elegant, yet robust differential pair.
Common-Mode Response
VBE1  VBE 2
I EE
I C1  I C 2 
2
I EE
V X  VY  VCC  RC
2
To avoid saturation, the collector voltages must not fall below the base voltages:
I EE
VCC  RC  VCM
2
Example 10.4
 A bipolar differential pair employs a load resistance of 1 kΩ

and a tail current of 1 mA. How close to VCC can VCM be chosen?
I EE
VCC  VCM  RC
2
 05V
That is, VCM must remain below VCC

by at least 0.5 V.
Common-Mode Rejection
 Due to the fixed tail current source, the input common-

mode value can vary without changing the output common-
mode value.
Differential Response I
I C1  I EE
IC2  0
VX  VCC  RC I EE
VY  VCC
Differential Response II
I C 2  I EE
I C1  0
VY  VCC  RC I EE
VX  VCC
Differential Pair Characteristics
 None-zero differential input produces variations in output

currents and voltages, whereas common-mode input
produces no variations.
Example 10.5
 A bipolar differential pair employs a tail current of 0.5 mA and

a collector resistance of 1 kΩ. What is the maximum allowable
base voltage if the differential input is large enough to
completely steer the tail current? Assume VCC=2.5V.
Because I EE is completely steered,

VCC - RC I EE  2 V at one collector.
To avoid saturation, VB  2 V .
Small-Signal Analysis
I EE
I C1   I
2
I EE
IC2   I
2
 Since the input to Q1 and Q2 rises and falls by the same

amount, and their emitters are tied together, the rise in IC1
has the same magnitude as the fall in IC2.
Virtual Ground
I C1  g m (V  VP )
I C 2   g m (V  VP ) VP  0
I C 2  I C1  0 I C1  g m V
g m (V  VP )  g m (V  VP ) I C 2   g m V
 For small changes at inputs, the gm’s are the same, and the
respective increase and decrease of IC1 and IC2 are the same,
node P must stay constant to accommodate these changes.
Therefore, node P can be viewed as AC ground.
Small-Signal Differential Gain
VX   g m VRC
VY  g m VRC  2 g m VRC
Av    g m RC
VX  VY  2 g m VRC 2V
 Since the output changes by -2gmVRC and input by 2V, the
small signal gain is –gmRC, similar to that of the CE stage.
However, to obtain same gain as the CE stage, power
dissipation is doubled.
Example 10.6
 Design a bipolar differential pair for a gain of 10 and a

power budget of 1mW with a supply voltage of 2V.
VCC  2 V
1 mW
 I EE   0.5 mA
2V
I C I EE / 2 0.25 mA 1
 gm    
VT VT 26 mV 104 
Av
 RC   1040 
gm
Example 10.7
 Compare the power dissipation of a bipolar differential pair

with that of a CE stage if both circuits are designed for equal
voltage gains, collector resistances, and supply voltages.
Differential pair CE stage

 AV diff  g m1 2 RC  AV CE  g m RC
g m12 RC  g m RC
I EE I C

2VT VT
I EE  2 I C
PD ,diff  VC I EE  2VC I C PD ,CE  VC I C
Large Signal Analysis
Vin1  Vin 2  VBE1  VBE 2

I C1 I
 VT ln  VT ln C 2
I S1 IS 2
and IC1  IC 2  I EE
Vin1  Vin 2
 IC 2 exp  IC 2  I EE
VT
I EE
 IC 2 
V V
1  exp in1 in 2
VT
Vin1  Vin 2
I EE exp
VT
 I C1 
Vin1  Vin 2
1  exp
VT
Example 10.8
 Determine the differential input voltage that steers 98% of

the tail current to one transistor.
I C1  002 I EE
Vin1  Vin 2
 I EE exp
VT
Vin1  Vin 2  391 VT 
We often say a differential input of 4  VT

is sufficient to turn one side of the bipolar
pair nearly off.
Input/Output Characteristics
Vout1  VCC  RC I C1
Vin1  Vin 2
I EE exp
VT
 VCC  RC
V V
1  exp in1 in 2
VT
Vout 2  VCC  RC I C 2
I EE
 VCC  RC
V V
1  exp in1 in 2
VT
Vin1  Vin 2
1  exp
VT
Vout1  Vout 2  RC I EE
V V
1  exp in1 in 2
VT
Vin1  Vin 2
  RC I EE tanh
2 VT
Example 10.9
 Sketch the output waveforms of the bipolar differential pair in

Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs.
10.14(b) and (c). Assume Q1 and Q2 remain in the forward active
region.
Figure10.14 (a)
Example 10.9 (cont’d)
 The left column operates in linear region (small-signal), whereas

the right column operates in nonlinear region (large-signal).
Small-Signal Model
vin1  v 1  vP  vin 2  v 2
v 1 v
 g m1v 1   2  g m 2 v 2  0
r 1 r 2
With r 1  r 2 and g m1  g m 2 v 1  v 2

Since vin1  vin 2 , 2vin1  2v 1 .
 v P  v in 1  v  1
 0
Half Circuits
vout1  vout 2
  g m RC
vin1  vin 2
 Since VP is grounded, we can treat the differential pair as

two CE “half circuits”, with its gain equal to one half
circuit’s single-ended gain.
Example 10.10
 Compute the differential gain of the circuit shown in Fig.

10.16(a), where ideal current sources are used as loads to
maximize the gain.
v out 1  v out 2
Figure10.16 (a)
  g m rO
v in1  v in 2
Example 10.11
 Figure 10.17(a) illustrates an implementation of the

topology shown in Fig. 10.16(a). Calculate the differential
voltage gain.
vout1  vout 2
  g m  rON rOP 
vin1  vin 2
Figure10.17 (a)
Extension of Virtual Ground
VX  0
 It can be shown that if R1 = R2, and points A and B go up

and down by the same amount respectively, VX does not
move. This property holds for any other node that appears
on the axis of symmetry.
Half Circuit Example I
Av   g m1 rO1 || rO 3 || R1 
Half Circuit Example II
Av   g m1 rO1 || rO 3 || R1 
Half Circuit Example III
RC
Av  
1
RE 
gm
Half Circuit Example IV
RC
Av  
RE 1

2 gm
I/O Impedances
v 1 v 2
 iX  
r 1 r 2
iX vX  v 1  v 2
 2r 1iX
vX vX
 Rin   2r 1
iX
iX iX
In a similar manner,
Rout  2 RC
CH 10 Differential Amplifiers
vX 38
MOS Differential Pair’s Common-Mode Response
I SS
I D1  I D 2 
2
I SS
VX  VY  VDD  RD
2
 Similar to its bipolar counterpart, MOS differential pair

produces zero differential output as VCM changes.
Equilibrium Overdrive Voltage
I SS
ID 
2
1 W 2
 nCox VGS  VTH 
2 L
I SS
 VGS  VTH equil 
W
nCox
L
 The equilibrium overdrive voltage is defined as the

overdrive voltage seen by M1 and M2 when both of them
carry a current of ISS/2.
Minimum Common-mode Output Voltage
I SS
VDD  RD  VCM  VTH
2
 In order to maintain M1 and M2 in saturation, the common-

mode output voltage cannot fall below the value above.
 This value usually limits voltage gain.
Example 10.15
 A MOS differential pair is driven with an input CM level of

1.6V. If ISS=0.5mA, VTH=0.5 V, and VDD=1.8 V, what is the
maximum allowable load resistance?
I SS
VDD  RD  VCM  VTH
2
VDD  VCM  VTH
 RD  2
I SS
 2.8 k
Differential Response
Small-Signal Response
VP  0
ID1  gmV ,
ID2  gmV
VX VY  2gmRDV
Av  gmRD
 Similar to its bipolar counterpart, the MOS differential pair

exhibits the same virtual ground node and small signal gain.
Power and Gain Tradeoff
 In order to obtain the same gain as a CS stage, a MOS

differential pair must dissipate twice the amount of current.
This power and gain tradeoff is also echoed in its bipolar
counterpart.
Example 10.16
 Design an NMOS differential pair for a voltage gain of 5 and a

power budget of 2 mW subject to the condition that the stage
following the differential pair requires an output CM level of at
least 1.6V. Assume μnCox=100 μA/V2, λ=0, and VDD= 1.8 V.
Textbook
2 mW Error!
I SS   111 mA
1.8 V
I
VCM ,out  VDD  RD SS  1.6 V
2
 RD  360 
For RD  360 ,
Av 5 W I SS
gm    2 n Cox
RD 360  L 2
W
  1738
CH 10 Differential Amplifiers
L 46
Example 10.17
 What is the maximum allowable input CM level in the previous

example if VTH=0.4 V?
To guarantee that M1 and M 2

operate in saturation,
I
VCM ,in  VDD  RD SS  VTH
2
 VCM ,out  VTH .
Thus,
VCM ,in  2 V
Example 10.18
 The common-source stage and the differential pair shown in Fig.

10.28 incorporate equal load resistors. If the two circuits are
designed for the same voltage gain and the same supply voltage,
discuss the choice of (a) transistor dimensions for a given power
budget, (b) power dissipation for given transistor dimensions.
(a) for same power budget,

I D1  I SS  2 I D 2  2 I D 3
W1 1 W2 1 W3
  
L1 2 L2 2 L3
3
 W 
 g m  2 nCox I D 
 L 
(b) for same transistor dimensions,
Figure10.28
I SS  2 I D1
 Pdiff  2 PCS
MOS Differential Pair’s Large-Signal Response
Goal is to obtain ID1 - ID2

Vin1  VGS 1  Vin 2  VGS 2 .
I D1  I D 2  I SS 
I D  (1  2)  n Cox (W  L)(VGS  VTH ) 2 .
2I D
 VGS  VTH  
W
nCox
L
 Vin1  Vin 2  VGS 1  VGS 2
2
 ( I D1  I D 2 )
W
nCox
L
MOS Differential Pair’s Large-Signal Response (cont’d)
2
(Vin1  Vin 2 ) 2  ( I  I  2 I D1 I D 2 )
W D1 D 2
n Cox
L
2
 ( I  2 I D1 I D 2 )
W SS
n Cox
L
W
 4 I D1 I D 2  2 I SS   nCox (Vin1  Vin 2 ) 2
L
  2
W
 16 I D1 I D 2  2 I SS   nCox (Vin1  Vin 2 ) 2 


 L 
  2
 W 2
 16 I D1 ( I SS  I D1 )  2 I SS  n Cox (Vin1  Vin 2 ) 

 L 
MOS Differential Pair’s Large-Signal Response (cont’d)
2
 
2  W 2
 16 I D1  16 I SS I D1  2 I SS   nCox (Vin1  Vin 2 )   0

 L 
  2
I SS 1 2 W 2
 I D1   4 I SS    n Cox (Vin1  Vin 2 )  2 I SS 

2 4  L 
I SS Vin1  Vin 2 W  W 
2
  nCox  4 I SS   C
n ox (Vin1  Vin 2 ) 
2 4 L  L 
I SS Vin 2  Vin1 W  W 
2
 ID2   nCox  4 I SS  nCox (Vin 2  Vin1 ) 
2 4 L  L 
(  the symmetry of the circuit)
1 W 4 I SS
I D1  I D 2   n C ox Vin1  V in 2   Vin1  Vin 2 
2
2 L W
 n C ox
L
Maximum Differential Input Voltage
Edge of
Conduction
~0 ISS
+ +
VTH VGS2
- -
VGS 1  VTH 2 I SS
2 I SS Vin1  Vin 2   2 VGS  VTH equil
VGS 2  VTH  max W
nCox
W  n C ox
L L
 There exists a finite differential input voltage that completely

steers the tail current from one transistor to the other. This
value is known as the maximum differential input voltage.
Contrast Between MOS and Bipolar Differential Pairs
MOS Bipolar
 In a MOS differential pair, there exists a finite differential

input voltage to completely switch the current from one
transistor to the other, whereas, in a bipolar pair that
voltage is infinite.
The effects of Doubling the Tail Current
 Since ISS is doubled and W/L is unchanged, the equilibrium

overdrive voltage for each transistor must increase by 2
to accommodate this change, thus Vin,max increases by 2
as well. Moreover, since ISS is doubled, the differential
output swing will double.
The effects of Doubling W/L
 Since W/L is doubled and the tail current remains unchanged,

the equilibrium overdrive voltage will be lowered by 2 to
accommodate this change, thus Vin,max will be lowered by
as well. Moreover, the differential output swing will remain
unchanged since neither ISS nor RD has changed
Example 10.20
 Design an NMOS differential pair for a power budget of 3 mW

and ∆Vin,max=500 mV. Assume μnCox=100 μA/V2 and VDD=1.8 V.
3 mW
I SS   1.67 mA
1.8 V
2 I SS
From Vin1  Vin 2 max 
W
nCox
L
W 2 I SS
 2
 133.6
L nCox Vin,max
RD is determined by the required voltage gain.
Small-Signal Analysis of MOS Differential Pair
1 W 4 I SS 2
I D1  I D 2   n Cox Vin1  Vin 2   Vin1  Vin 2 
2 L W
n Cox
L
1 W 4 I SS
  n Cox Vin1  Vin 2 
2 L W
n Cox
L
W
  n Cox I SS Vin1  Vin 2 
L
 When the input differential signal is small compared to

[4ISS/nCox(W/L)]1/2, the output differential current is linearly
proportional to it, and small-signal model can be applied.
Virtual Ground and Half Circuit
VP  0
Av   g m RD
 Applying the same analysis as the bipolar case, we will

arrive at the same conclusion that node P will not move for
small input signals and the concept of half circuit can be
used to calculate the gain.
MOS Differential Pair Half Circuit Example I
0
 1 
Av   g m1  || rO 3 || rO1 
 g m3 
MOS Differential Pair Half Circuit Example II
 0
g m1
Av  
g m3
MOS Differential Pair Half Circuit Example III
 0
RDD 2
Av  
RSS 2  1 g m
Bipolar Cascode Differential Pair
Av   g m1  g m 3  rO1 || r 3  rO 3  rO 1 || r 3 
Output Impedance of CE Stage with Degeneration
v X   iX  g m v  rO  v
 iX  g miX  RE || r   rO  iX  RE || r 
 Rout  1  g m ( RE || r )  rO  RE || r
 rO  ( g m rO  1)( RE || r )
 rO 1  g m ( RE || r ) 
Output Impedance of CS Stage with Degeneration
iX  g m v1  iX  g m  iX RS   iX  g miX RS
 rO  iX  g miX RS   iX RS  vX
 Rout  rO 1  g m RS   RS
 1  g m rO  RS  rO
 g m rO RS  rO
Bipolar Telescopic Cascode
Av   g m1 g m 3 rO 3 rO1 || r 3  || g m5 rO 5 (rO 7 || r 5 )
Example: Bipolar Telescopic Parasitic Resistance
  R  R
Rop  rO 5 1  g m 5  rO 7 || r 5 || 1    rO 7 || r 5 || 1
  2  2
Av   g m1  g m 3 rO 3 ( rO1 || r 3 ) || Rop 
MOS Cascode Differential Pair
Av   g m1rO 3 g m 3 rO1
MOS Telescopic Cascode
Av   g m1  g m 3 rO 3 rO1  || ( g m 5 rO 5 rO 7 )
Example: MOS Telescopic Parasitic Resistance
Rop  1  g m 5  rO 5 || R1   rO 7  rO 5 || R1
Av   g m1 ( Rop || rO 3 g m 3 rO 1 )
Effect of Finite Tail Impedance
Vout ,CM RC / 2

Vin ,CM REE  1 / 2 g m
 If the tail current source is not ideal, then when a input CM
voltage is applied, the currents in Q1 and Q2 and hence
output CM voltage will change.
Input CM Noise with Ideal Tail Current
Input CM Noise with Non-ideal Tail Current
Comparison
 As it can be seen, the differential output voltages for both

cases are the same. So for small input CM noise, the
differential pair is not affected.
CM to DM Conversion, ACM-DM
VCM  VGS  2I D RSS
 1  I
 I D   2 RSS  ,  VGS  D
 gm  gm
VCM
 I D 
1
 2 RSS
gm
Vout  Vout1  Vout 2
 I D RD  I D  RD  RD 
1 W  I D RD
2
I D1   n Cox VGS 1  VTH  Textbook VCM
2 L Error!  RD
1 W 2
1/ g m  2 RSS
I D 2   n Cox VGS 2  VTH 
2 L Vout RD RD
  
I D1  I D 2 & I D1  I D 2 , VGS 1  VGS 2 VCM 1/ g m  2 RSS 2 RSS
 If finite tail impedance and asymmetry are both present,

then the differential output signal will contain a portion of
input common-mode signal.
Example: ACM-DM
ACM  DM 
R C
1
 2[1  g m 3 ( R1 || r 3 )]rO 3  R1 || r 3 
g m1
CMRR
ADM
CMRR 
ACM  DM
 CMRR defines the ratio of wanted amplified differential

input signal to unwanted converted input common-mode
noise that appears at the output.
Example 10.28
 Calculate the CMRR of the circuit in Fig. 10.46.
ADM g m1 RC
CMRR  
ACM  DM ACM  DM
g m1 RC  1 
   2 [1  g m3 ( R1 || r 3 )]rO 3  R1 || r 3 
RC  g m1 
Figure10.46
Differential to Single-ended Conversion
 Many circuits require a differential to single-ended

conversion, however, the above topology is not very good.
Supply Noise Corruption
 The most critical drawback of this topology is supply noise

corruption, since no common-mode cancellation
mechanism exists. Also, we lose half of the signal.
Better Alternative
 This circuit topology performs differential to single-ended

conversion with no loss of gain.
Active Load
 With current mirror used as the load, the signal current

produced by the Q1 can be replicated onto Q4.
 This type of load is different from the conventional “static
load” and is known as an “active load”.
Differential Pair with Active Load
 The input differential pair decreases the current drawn from

RL by I and the active load pushes an extra I into RL by
current mirror action; these effects enhance each other.
Active Load vs. Static Load
 The load on the left responds to the input signal and

enhances the single-ended output, whereas the load on the
right does not.
MOS Differential Pair with Active Load
 Similar to its bipolar counterpart, MOS differential pair can

also use active load to enhance its single-ended output.
Asymmetric Differential Pair
 Because of the vastly different resistance magnitude at the

drains of M1 and M2, the voltage swings at these two nodes
are different and therefore node P cannot be viewed as a
virtual ground when Vin2=-Vin1.
Quantitative Analysis - Approach 1
iX  iY & v A  iX  g mP

1
rOP 
vout v
iY   g mP v A  out  g mP iX  g mP
1
rOP   iX
rOP rOP
vout
 iX 
rOP 1  g mP  g mP
1
rOP  
M3 M4
1
rOP vA rOP v out
g mP g mP v A
A i X  
iY


rON 
N rON N
M1 M2
Quantitative Analysis - Approach 1 – cont’d
v A   iX  g mN v1  rON   iY  g mN v2  rON  vout  0

 v A  2iX rON  g mN rON  vin1  vin 2   vout  0
 v1  v2  vin1  vin 2 & iX  iY
Substituting for vA and iX ,
vout vout
 gmP1 rOP   2rON
rOP 1  g mP  g mP
1
rOP   rOP 1  g mP  g mP
1
rOP  
 vout  g mN rON  vin1  vin 2 
vout rOP 1  g mP  g mP

1
rOP  
  g mN rON
vin1  vin 2 2rON  2rOP
 g mN  rON rOP 
Quantitative Analysis - Approach 2
vX iX
iX
v1 v2
Textbook
Error!
vThev   g mN roN (vin1  vin 2 )

+ -
RThev  2roN
Textbook  v1  v2 &  iX  g m1v1  rO1   iX  g m 2 v2  rO 2  v X
Error!
Quantitative Analysis - Approach 2 – cont’d
1
rO 3
gm3
vA 
1
 vout  vThev 
rO 3  RThev
g m3
vout vout  vThev
g m 4vA   0
rO 4 1
rO 3  RThev + -
gm3
 1 
 rO 3 
g m3 1 v
  gm4    vout  vThev   out  0
 1 1  rO 4
 r O 3  R Thev rO 3  RThev 
 g m3 g m3 
2 v 1
  vout  vThev   out  0 ( rO 3  RThev and g m3  g m 4 )
RThev rO 4 gm3
 1 1  g mN rON  vin1  vin 2 
 vout   
r
 ON rOP  rON
vout
  g mN  rON rOP 
vin1  vin 2
Example 10.29
 Prove that the voltage swing at node A is much less than

that at the output.
 vout  1 
vA     g m 4 v A  rO 3 
 rO 4  g m 3 
A  vout  1
   g m 4vA 
 rO 4  g m3
I
vout
 vA    vA
rO 4 g m 3
vout
I   g m4 v A vout
rO4  vA  
2rO 4 g m 3

Chapter 10 Differential Amplifiers

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Chapter 10 Differential Amplifiers

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Chapter 10 Differential Amplifiers

 10.1 General Considerations

 10.2 Bipolar Differential Pair

 10.3 MOS Differential Pair

 10.4 Cascode Differential Amplifiers

 10.5 Common-Mode Rejection

 10.6 Differential Pair with Active Load

 An audio amplifier is constructed as above that takes a

 However, VCC contains a ripple from rectification that leaks

 Since both node X and Y contain the same ripple, their

 Since the signal is taken as a difference between two nodes,

 Signals cannot be applied in phase to the inputs of a

 When the inputs are applied differentially, the outputs are

 A pair of differential signals can be generated, among other

 Determine the common-mode level at the output of the circuit

In the absence of signals,

where RC  RC1  RC 2 and

Thus, VCM  VCC  RC I C

Interestingly, the ripple affects VCM

 With the addition of a tail current, the circuits above operate

 A bipolar differential pair employs a load resistance of 1 kΩ

That is, VCM must remain below VCC

 Due to the fixed tail current source, the input common-

 None-zero differential input produces variations in output

 A bipolar differential pair employs a tail current of 0.5 mA and

Because I EE is completely steered,

 Since the input to Q1 and Q2 rises and falls by the same

 Design a bipolar differential pair for a gain of 10 and a

 Compare the power dissipation of a bipolar differential pair

Differential pair CE stage

PD ,diff  VC I EE  2VC I C PD ,CE  VC I C

Vin1  Vin 2  VBE1  VBE 2

 Determine the differential input voltage that steers 98% of

Vin1  Vin 2  391 VT 

We often say a differential input of 4  VT

 Sketch the output waveforms of the bipolar differential pair in

 The left column operates in linear region (small-signal), whereas

With r 1  r 2 and g m1  g m 2 v 1  v 2

 Since VP is grounded, we can treat the differential pair as

 Compute the differential gain of the circuit shown in Fig.

 Figure 10.17(a) illustrates an implementation of the

 It can be shown that if R1 = R2, and points A and B go up

 Similar to its bipolar counterpart, MOS differential pair

 The equilibrium overdrive voltage is defined as the

 In order to maintain M1 and M2 in saturation, the common-

 A MOS differential pair is driven with an input CM level of

 Similar to its bipolar counterpart, the MOS differential pair

 In order to obtain the same gain as a CS stage, a MOS

 Design an NMOS differential pair for a voltage gain of 5 and a

 What is the maximum allowable input CM level in the previous

To guarantee that M1 and M 2

 The common-source stage and the differential pair shown in Fig.

(a) for same power budget,

Goal is to obtain ID1 - ID2

 Vin1  Vin 2  VGS 1  VGS 2

(  the symmetry of the circuit)

 There exists a finite differential input voltage that completely

 In a MOS differential pair, there exists a finite differential

 Since ISS is doubled and W/L is unchanged, the equilibrium

 Since W/L is doubled and the tail current remains unchanged,

 Design an NMOS differential pair for a power budget of 3 mW

 When the input differential signal is small compared to

 Applying the same analysis as the bipolar case, we will