Prof. S.

Ben-Yaakov , DC-DC Converters

[6- 1]

Output Voltage Ripple, Parasitic Effects

6.1 Output voltage ripple (Buck) 6.2 Parasitic effects 6.2.1 Diode recovery 6.2.2 Internal delay of switching 6.2.3 Stray and leakage inductances Clamp Diode snubber (clamp) Switch snubbers

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 2]

Output voltage ripple

S Vin control D L IL IC C R IR

IL

Iav t

IR

Iav

DC

Assumption: Low output ripple voltage

t IC Capacitor Current AC t

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 3]

IC
t1

IL 2
Ts

Ripple
IL

t2

VC

Vc

Q VC = ; C

Q = IL dt;
t1

t2

Q =

IL Ts 1 ; 2 2 2

Q =

IL Ts 8

VC =

IL 1 8C fs

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 4]

IL = Vo t off / L

IL =

Vo VD Doff Ts = o off L Lfs

VoDoff 1 VD = o off 2 CLfs 8fs 8CLfs

Ripple

VC =

The effect of fs

I =

VoDoff Lfs
VC = IL 8fsC

L; fs can be traded for same I C;fs can be traded for same I& VC if fs is increased for given L, C

VC =

VoDoff

2 8LCfs

VC goes down -40 db/dec (second order)

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 5]

S Vin control D

L IL

Example
IC C R IR

IL = 1A C = 47 F
Ts = 10 S ESR = 10 m

Find the output voltage ripple V

VC =

1A 10 S = 25 mV 8 47F

VESR = 10 m 1A = 10 mV
zApproximate

(upper limit) of total ripple)

V = VC + VESR = 25 mV + 10 mV = 35 mV

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 6]

Application of Simulation
10meg R4 D1 Dbreak V1 {Vin} L1 {L1} L2 {L1*(n*n)} out_gnd C1 220u IC = 6 RL {Load} out

drain

0
V1 = 0 V2 = 15 TD = 0 TR = 0.01u TF = 0.01u PW = 10u PER = 20u

gate V2

S1
+ +

Sbreak

K K1 K_Linear COUPLING = 1 L1 = l1 L2 = l2

PARAM ET ERS:
n = 0.5 Vin = 12 L1 = 300u Load = 10

Modify circuit to include ESR=100m Find ripple at output

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 7]

Diodes Recovery Implications

L Vin Vx C Vo R

Reverse current at switch turn on

zSoft

and hard recovery

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 8]

Stages in diode recovery

Lstray Lstray ESR Lstray

Diode voltage

VD

t VO VDmax

Lstray Lstray ESR

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 9]

Turn off of transistor

Lmain Lstray
Lmain Lstray Co Vo ESR

Lstray

Lstray Lstray

V DS VO t

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 10]

Diode forward recovery

I

+VC
I

t VD VPK VF t

clamp

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 11]

Parasitic effects: Internal delay

To turn on
RL

RL

RG CGS Vgs LS

(real) Vgs

Vgs

V'gs

Depend on Q

Q=

LS Cgs RL + R G

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 12]

Clamps
limiting maximum voltage

Vin
Vo

Vin

VO
Vds

Ipk

Llkg Cdss

Llkg Cdss

V DS VO t

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 13]

Solutions
Vin n:1 VO Vin n:1 VO

Llkg Cdss

Very fast diode Rc Cc

Llkg

Vz > Vin + Vo = Vin + nVo

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 14]

Simple Example
Vin

A
Vin

Clamp B is better from the point of view of efficiency.

VC ( A ) = Vin + Vo

But ...

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 15]

Parasitic inductance
Vin L1

Energy of L1 L2 L3 L4 will cause high spike on C (FET). The FET is not protected!
C L2 L3 L4

Rule:
Connect clamps and snubbers directly to the elements to be protected

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 16]

To protect FET
Vin Line

D LD

Line

Still:

RG LS S

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 17]

Designing the Snubber Components

Vin Rc Cc Llkg

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 18]

Snubber
VCc

Vav

Ts
+
' Vo

L lkg Ip CC R C VCc

Parasitic energy Ipav

VCc Cc

Rc

VCc > Vo

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 19]

Leakage discharge
Ipk

Ip

dI dt

Ip av Rc = VCc av Rc Cc = T > Ts

tp

dIp VCc av Vo ' = dt L lkg

tp =

L lkg Ipk VCc av Vo '

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 20]

Leakage average current

Ip av = Ipk t p fs 2

Procedure 1. Select VCc av 2. Calculate Ip av 3. Select R c = VCc av Ip av

4. Select Cc T > Ts 5. Trim in-circuit

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 21]

Simulation Exercise
10meg R4 D1 Dbreak V1 {Vin} drain L1 {L1} L2 {L1*(n*n)} out_gnd C1 220u IC = 6 RL {Load} out

0
V1 = 0 V2 = 15 TD = 0 TR = 0.01u TF = 0.01u PW = 10u PER = 20u

gate V2

S1
+ +

Sbreak

K K1 K_Linear COUPLING = 1 L1 = l1 L2 = l2

PARAM ET ERS:
n = 0.5 Vin = 12 L1 = 300u Load = 10

Add 1uH leakage to Flyback converter. Design a clamp and check it by simulation.

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 22]

Diode Snubber (clamp)

Vo
CD

Lstray

Lstray

Diode Snubber

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 23]

Snubber waveforms
VD
CS RS VO

no snubber

bad snubber

Vo

CD Lstray

VD
good snubber

CS is very l arg e VO

Cs > CD V 2CS 2

Energy lost to snubber

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 24]

Snubber design
Design - use simulation in circuit tuning Needed information Ipk ( Reverse ) Lstray

CS R S Lstray Ipk VO

L stray Ipk 2

moves to Cs Vo + V

R s damping

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 25]

Switch Snubbers
control

VGS

t
VS
VS

IS

Jd Pswitching
t

Switching losses due to overlap Pd linear with fS !

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 26]

Snubber types
Snubbers = control of
dV snubbers dt dI snubbers dt

dV dI or dt dt

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 27]

Snubber types
Passive (dissipative) snubber Energy lost to heat Non-dissipative (lossless) snubber Energy recovered Passive Snubbers by passive network Active snubbers by auxiliary active devices

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 28]

Switching overlap
control

VGS

t
VS dI dt dV dt
t
Jp

IS

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 29]

Switch Snubber
Vo

dV

dt (at turn off) can be slow down by adding external snubber capacitor C
Vo

At turn off
Cdss
C

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 30]

dV/dt
dV I = dt C + Cdss Cdss - output capacitance of FET I = 1 Amp C + Cdss= 1nF

dV 1 103 = 9 = 6 = 1 kV S dt 10 10

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 31]

Capacitor losses
C
2

Vo

Problem at turn on !

CVO EC = (J ) 2

CV Pd = O fs 2

Example : VO = 400 V C = 1 nF fs = 100 kHz Pd = 10 9 16 10 4 105 = 8 W 2

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 32]

Solution
VO CS RS

VO

Snubbing

CS

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 33]

Reset
VO CS RS

RDSon

If Rds on < Rs most energy will be lost to Rs Heat Selection of Cs Selection of Rs to ensure reset

T=

1 << t on R sC s

t on 4R sCs

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 34]

CV 2 2

Losses

Cdss

2 Cdss Vmax fs lost to heat 2

Linear with fs ! Switching losses (overlap) also linear with fs !

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 35]

Lossless snubbing (simple example)

Q1

C1 C2

VC 2 VC 2

t
Q2
delay

t
IL

C1 , C2 of transistor plus external (if any)

VDS1

t
VDS2

Prof. S. Ben-Yaakov , DC-DC Converters

[6- 36]

Dead time requirement

Q1

t
Q2
delay

t
IL

VDS1

t
VDS2