Chapter 5

SEQUENTIAL logic circuit

(Digital Logic Design, ECEg 3142)

Faculty of electrical and computer Engineering

Sileshi A.
(sileshi120@gmail.com) 2021/2022
 Sequential Circuits
• Most digital systems like digital watches, digital phones, personal
computers, digital traffic light controllers and so on require
memory elements.
• Memory elements are digital Combinational
outputs Memory outputs
circuits that can store and
retrieve data in the form of 1's
and 0's.
• The output of the systems with Combinational Memory
memory depends not only on logic elements
present inputs but also on what
has happened in the past

External inputs

Sequential circuit = Combinational logic + Memory Elements

1
 Sequential Circuits
• There are two types of sequential circuits:
 synchronous: outputs change only at specific time

 asynchronous: outputs change at any time

Inputs Outputs
Combinational
Circuit

Flip-flops
Clock
Inputs Outputs
Combinational
Circuit
Memory
Elements

2
 Memory Elements
• Memory element: a device which can remember value
indefinitely, or change value on command from its
inputs.

Memory Q
Command element Stored value

• Characteristic table: Q(t): current state

Q(t+1) or Q+: next state
Command Q(t) Q(t+1)
(at time t)
Set X 1
Reset X 0
Memorise / 0 0
No Change 1 1

3
 Latch vs Flip-Flops
• A latch is a temporary data storage device(memory element) that have two
possible states( i.e. it is bistable device).

• A flip-flop is synchronous bistable device(memory element) that changes state

at specified point.

• Similarity: Both are bistable devices.

• Differences: Latches are level sensitive devices and flip- flops are edge
sensitive devices.

• In other words, Latches are Asynchronous and Flip-flops are synchronous

devices.

• Latches are the building block of Flip-flops.

4
Set-Reset (S-R) Latch
• Complementary outputs: Q and Q'.
• When Q is HIGH, the latch is in SET state.
• When Q is LOW, the latch is in RESET state.
• For active-HIGH input S-R latch (NOR gate latch) ,
• R=HIGH (and S=LOW) a RESET state
• S=HIGH (and R=LOW) a SET state
• both inputs LOW a no change
• both inputs HIGH a Q and Q' both LOW (invalid)!

S Q

R Q’
5
 S-R Latch
• For active-LOW input S'-R' latch (also known as NAND gate latch),

• R'=LOW (and S'=HIGH) a RESET state

• S'=LOW (and R'=HIGH) a SET state

• both inputs HIGH a no change

• both inputs LOW a Q and Q' both HIGH (invalid)!

S
Q

R Q'

6
 S-R Latch
• SR Latch NOR gate implementation

R Q Characteristics table

S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
S Q 0 1 0 0 1
Q=0
0 1 1 0 1
1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0
Q = Q’
1 1 1

7
• S-R latch NAND gate implementation

Characteristics table
S Q S‘ R’ Q0 Q Q’
0 0 0 1 1
0 0 1 1 1
0 1 0 1 0
R Q
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0

8
S-R Latch (Active-high and Active-low)

S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
9
SR Latch: Timing Diagram

Q'

store set store reset

Q

 = propagation delay of the latch

10
SR Latch with Control Input (Gated SR Latch)
• The operation of the basic SR latch can be modified by providing an
additional control input that determines when the state of the latch can be
changed.
• It consists of the basic SR latch and two additional AND/NAND gates.

R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid 11
 Controlled Latches

• D Latch (D = Data)
Timing Diagram
• D latch is designed to eliminate the
indeterminate state in SR latch by making sure
C
that inputs S and R are never equal to 1 at the
same time D
D S
Q Q
C
R Q
t
Output may
C D Q change
0 x Q0 No change
1 0 0 Reset
1 1 1 Set 12
 Controlled Latches

• D Latch (D = Data)
Timing Diagram

S
C
D
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

13
 Graphic Symbols for latches

• A latch is designated by a rectangular block with inputs on the left and

outputs on the right. One output designates the normal output, and the other
designates the complement output.

14
 Latch Circuits: Not Suitable

• Latch circuits are not suitable in synchronous logic circuits.

• When the enable/control signal is active, the excitation inputs are gated directly
to the output Q.

• Thus, any change in the excitation input immediately causes a change in

the latch output.

• The problem is solved by using a special timing control signal called a clock to
restrict the times at which the states of the memory elements may change.

• This leads us to the edge-triggered memory elements called flip-flops.

15
Memory Elements

• Memory element with clock: Flip-flops are memory

elements that change state on clock signals.

Memory Q
command element stored value

clock

• Clock is usually a square wave.

Positive pulses

Positive edges Negative edges

16
 Edge-Triggered Flip-flops

• Controlled latches are level triggered

• Flip-flops: synchronous bistable devices

• Output changes state at a specified point on a triggering input
called the clock.
CLK Positive Edge

CLK Negative Edge

• Change state either at the positive edge (rising edge) or at the

negative edge (falling edge) of the clock signal.
17
S-R Flip-flop

R Q
Pulse
CLK transition LATCH
detector
S Q’

The pulse transition detector.

CLK'
CLK'
CLK CLK* CLK CLK*

CLK
CLK
CLK'
CLK'

CLK*
CLK*
Positive-going transition Negative-going transition
(rising edge) (falling edge)

18
 Edge-Triggered Flip-flops

• S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at

the clock input.

S Q D Q J Q
C C C
R Q' Q' K Q'

Positive edge-triggered flip-flops

S Q D Q J Q
C C C
R Q' Q' K Q'

Negative edge-triggered flip-flops

19
 S-R Flip-flop
• S-R flip-flop: on the triggering edge of the clock pulse,
• S=HIGH (and R=LOW) a SET state
• R=HIGH (and S=LOW) a RESET state
• both inputs LOW a no change
• both inputs HIGH a invalid

• Characteristic table of positive edge-triggered S-R flip-flop:

S R CLK Q(t+1) Comments

0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to HIGH

20
 S-R Flip-flop
• It comprises 3 parts:
• a basic NAND/NOR latch

• a pulse-steering circuit

• a pulse transition detector (or edge detector) circuit

• The pulse transition detector detects a rising (or falling) edge and produces a
very short-duration spike.

21
S-R Flip-flop

The pulse transition detector.

S
Q
Pulse
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)

22
Clock SR Flip Flop

If clock is low then both S and R becomes 0

Therefor the flip flop output will be in
memory(hold) state.

S R C Qn Qn+ description
1
0 0 0 0 hold
0 0 1 1
0 1 0 0 clear (reset)
0 1 1 0
1 0 k will0always1be 1. If it is
set0 so
1 0 it wont
1 show
1 any change.
1 1 0 ? Invalid
1 1 1 ?
D Flip Flop

Characteristics of D Flip Flop

D CLK Q(t+1) Comments
x  Q(t) No change
0  0 Reset
1  1 Set
 D Flip-flop

• Application: Parallel data transfer.

• To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage.

D Q Q1 =
CLK X*
X Q'
Combinational Y D Q Q2 =
logic circuit
Z CLK Y*
Q'

D Q Q3 =
Transfer CLK Z*
Q'
* After occurrence of negative-going transition

25
 JK Flip-Flop
• There are three operations that can be performed with a flip-flop: set it to 1,
reset it to 0, or complement its output.

• The JK flip-flop performs all three operations.

• The circuit diagram of a JK flip-flop constructed with a S-R flip-flop

26
 JK Flip-Flop
• The J input sets the flip-flop to 1, the K input resets it to 0, and when both
inputs are enabled, the output is complemented.

Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
J K CLK Q(t+1) Comments 1 0 1 0
1 1 0 1
0 0  Q(t) No change
1 1 1 0
0 1  0 Reset
1 0  1 Set
1 1  Q(t)' Racing
27
 Race around condition
• A condition occurs in JK Flip-Flop when both its inputs J=K=1, and the clock is HIGH for a
long period (For J-K flip-flop, if J=K=1, and if CLK=1 for a long period of time, then output
Q will toggle as long as CLK remains high which makes the output unstable or uncertain).

• This race around condition problem can be overcome by using a Master Slave JK flip flop.

Master Slave JK flip flop

• Constructed by cascading two JK flip flops are connected in series.
• The first JK flip flop is called the “master” and the other is a “slave”.
• The output from the master is connected to the two inputs of the slave whose output is fed
back to inputs of the master.
• The circuit also has an inverter other than the two flip flops.
• The Clock Pulse and inverter are connected because of which the flip flops get an inverted
clock pulse.
• In other words, if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and vice
versa.

28
Master Slave JK flip flop
Block diagram for active HIGH JK Master Slave Flip -Flop

Circuit diagram for active HIGH JK Master Slave Flip -Flop

29
Working of a Master Slave flip flop
• When the clock pulse goes high, the slave is isolated; J and K inputs can affect the
state of the system. The slave flip-flop is isolated when the CP goes low.
• When the CP goes back to 0, information is transmitted from the master flip-flop
to the slave flip-flop and output is obtained.
• As the master flip flop is positive triggered it responds first and the slave later (it
is negative edge triggered).
• The master goes to the K input of the slave when both inputs J=0 and K=1, and
also Qt’ = 1. In this case the slave copies the master as the clock forces the slave to
reset.
• The master goes to the J input of the slave when both J=1 and K=0, Q = 1. The
clock is set due to the negative transition of the clock.
• There is a state of toggle when both J=1 and K=1. On the negative transition of
clock slave toggles and the master toggles on the positive transition of the clock.
• Both the flip flops are disabled when both J=0 and K=0 and Qt is unchanged.
T-Flip-Flop

• The T(toggle) flip-flop is a complementing flip-flop and can be

obtained from a JK flip-flop when inputs J and K are tied together.

T J Q D Q
T

K Q Q

D = JQ’ + K’Q T Q
D = TQ’ + T’Q = T  Q
Q

31
Flip-Flop Characteristic/State Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
32
Flip-Flop state Equations

• Analysis / Derivation

J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 J KQ
0 1 0 0 0 1 0 0
0 1 1 0 1 1 0 1
K Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

33
Flip-Flop state Equations …

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
34
Flip Flop Excitation Tables
• Excitation tables : For each state transition from Q(t) to
Q(t+1), what input combination(s) will produce that
transition?

S-R J-K D T
FF FF FF FF

Q(t) Q(t+1) S R J K D T
0 0 0 x 0 x 0 0
0 1 1 0 1 x 1 1
1 0 0 1 x 1 0 1
1 1 x 0 x 0 1 0

35
Example:
A PN flip-flop has four operations: clear to 0, no change, complement, and
set to 1, when inputs P and N are 00, 01, 10, and 11, respectively.
(a) Tabulate the state table.
(b) Derive the characteristic equation.
(c) Show how the PN flip-flop can be converted to a D flip-flop.

Solution (c) Connect P and N to D inputs

by using the characteristic
equation that is determined at b.

36
Clocked Sequential Circuits Analysis

• The analysis of a sequential circuit consists of obtaining a table or a diagram

for the time sequence of inputs, outputs, and internal states.

• It is also possible to write Boolean expressions that describe the behavior of the

sequential circuit.

• The behavior of a clocked sequential circuit can be described algebraically by

means of state equations.

• A state equation specifies the next state as a function of the present state and

inputs.
37
 State Equation

• A state equation is an algebraic expression that specifies the

condition for a flip-flop state transition.

• The left side of the equation with (t+1) denotes the next state of the flip-
flop one clock edge later.

• The right side of the equation is Boolean expression that specifies the
present state and input conditions that make the next state equal to 1.

A(t+1) = A(t) x(t) + B(t) x(t)

• The time sequence of inputs, outputs, and flip-flop states can be

enumerated in a state table (sometimes called transition table).

38
State Diagram
• The information available in a state table can be represented
graphically in the form of a state diagram.
• In this type of diagram, a state is represented by a circle, and the
(clock-triggered) transitions between states are indicated by
directed lines connecting the circles
AB input/output
• The binary number inside each circle identifies the state of the
flip-flops.
• The directed lines are labeled with two binary numbers separated
by a slash which represents input and output during the present
state.

39
Example 1: Do analysis for the following sequential Circuit.
Solution:
Step1: Givens identification:
• *1- Input (x)
x
D Q A • * 2- Present states (A(t) and B(t))
• * 2- Next states (A(t+1) and B(t+1))
Q • * 1- output (y(t))
Step2: Obtain the next state and output
equations:
D Q B
A(t+1) = DA
CLK = A(t) x(t)+B(t) x(t)
Q
=Ax+Bx
y B(t+1) = DB
= A’(t) x(t)
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’ 40
Example 1: …
Step3: Generate the characteristic/State Table (Transition Table)

Present
Input Next State Output
State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

t t+1 t 41
Example 1: …
Step4: Obtain State Table (Transition Table)

Present Next State Output

State x=0 x=1 x=0 x=1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0

t t+1 t

42
Example 1: …

Step4: Obtain the State Diagram

0/0 1/0
0/1
00 10

0/1
1/0 0/1 1/0

01 11

1/0

43
Example 2: Do analysis for the following sequential Circuit.
Solution:
x D Q A Step1:Givens identification:
y • *2- Inputs (x and y)
CLK Q • * 1- Present state (A(t) )
Step3: Generate the characteristic/State (Transition) Table• * 1- next state (A(t+1))
• * 1- output (y(t))
Present
Input Next State
State Step2: Obtain the next state equation:
A x y A A(t+1) = DA
0 0 0 0 = A(t)  x(t)  y(t)
0 0 1 1 =Axy
0 1 0 1 Step4: Obtain the State Diagram
0 1 1 0 01, 10
00, 11
1 0 0 1
1 0 1 0 00, 11 0 1
1 1 0 0
01, 10
1 1 1 1
44
Example 3: Do analysis for the following sequential Circuit.
Then:
J Q A A(t+1) = JA Q’A + K’A QA
= A’B + AB’ + Ax
x K Q B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
J Q B Step3: Generate the characteristic/State (Transition Table)

Present Next Flip-Flop

K Q I/P
State State Inputs
CLK
Solution: A B x A B JA KA JB KB
Step1:Givens identification: 0 0 0 0 0 1 0
0 1
• *1- Input (x) 0 0 1 0 0 0 1
0 0
• * 2- Present states (A(t) and B(t) ) 0 1 0 1 1 1 0
1 1
• * 2- Next states (A(t+1) and B(t+1))
0 1 1 1 0 1 0 0 1
• * 2- Flip flop inputs (JA ,JB ,KA and KB )
1 0 0 1 1 0 0 1 1
Step2: Obtain the next state equations:
1 0 1 1 0 0 0 0 0
JA = B(t) = B KA = B(t)x(t)’ = Bx’ 1 1 0 0 0 1 1 1 1
JB = x(t)’ = x’ KB = A(t)  x(t) = A  x 1 1 1 1 0 0 0
1 1 45
Example 3: …
Step4: Obtain the State Diagram
1
0 1
00 11

0
0 0

01 10
1
1

46
 Example 4: Do analysis for the following sequential Circuit.
x A Then:
T Q y
A(t+1) = TA Q’A + T’A QA
R Q = AB’ + Ax’ + A’Bx
B(t+1) = TB Q’B + T’B QB
=xB
T Q
B y(t) = A(t)B(t) = AB
Step3: Generate the characteristic/State (Transition Table)
R Q
Present Next F.F
I/P O/P
CLK Reset State State Inputs
Solution: A B x A B TA TB y
Step1:Givens identification:
0 0 0 0 0 0 0 0
• *1- Input (x)
0 0 1 0 1 0 1 0
• * 2- Present states (A(t) and B(t) )
0 1 0 0 1 0 0 0
• * 2- Next states (A(t+1) and B(t+1))
0 1 1 1 0 1 1 0
• * 2- Flip flop inputs (TA and TB )
1 0 0 1 0 0 0 0
• * 1-output (y(t))
1 0 1 1 1 0 1 0
Step2: Obtain the next state equations:
TA = B x TB = x 1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 1 47
Example 4: …
Step4: Obtain the State Diagram

0/0 0/0
00 1/0 01

1/1 1/0
11 10
0/1 0/0
1/0

48
Flip Flop Operating Characteristics
• Propagation delay time: is the interval of time required after an
input signal has been applied for the resulting output change to
occur.
• Four categories:
1. Propagation delay( 𝑡𝑃𝐿𝐻 ) as measured the triggering edge of the clock
pulse to the LOW-to-HIGH transition of the output.

49
Flip Flop Operating Characteristics…
2. Propagation delay( 𝑡𝑃𝐻𝐿 ) as measured the triggering edge of the clock
pulse to the HIGH-to-LOW transition of the output.

3. Propagation delay( 𝑡𝑃𝐿𝐻 ) as measured from the leading edge of the preset
input to the LOW-to-HIGH transition of the output.

50
Flip Flop Operating Characteristics …

4. Propagation delay( 𝑡𝑃𝐻𝐿 ) as measured the leading edge of the clear input to
the HIGH-to-LOW transition of the output.

51
 Flip Flop Operating Characteristics…
• The Hold Time: is the minimum interval required for the logic levels to remain on
the inputs after the triggering edge of the clock pulse in order for the levels
to be reliably clocked into the flip-flop.

52
 Flip Flop Operating Characteristics …

• Set-up Time: is the minimum interval required for the logic levels to be maintained
constantly on the inputs (J and K, or D) prior to the triggering edge of the clock
pulse in order for the levels to be reliably clocked into the flip-flop.

53
Flip Flop Operating Characteristics …

• Maximum Clock Frequency(𝑓𝑚𝑎𝑥 ): is the highest rate at which a flip-flop can be

reliably triggered. At clock frequencies above the maximum, the flip-flop would
be unable to respond quickly enough, and its operation would be impaired.

• Pulse Widths: Minimum pulse widths (𝑡𝑊 ) for reliable operation are usually
specified by the manufacturer for the clock, preset, and clear inputs.
Typically, the clock is specified by its minimum HIGH time and its minimum
LOW time.

• Power Dissipation: The power dissipation of any digital circuit is the total power
consumption of the device.

54
Application of Flip-Flops
• Frequency Division
• When a pulse waveform is applied to the clock input of a J-K flip-flop that
is connected to toggle, the Q output is a square wave with half the frequency
of the clock input.

55
Application of Flip-Flops …
• The Q output of the second flip-flop is one-fourth the frequency of the
original clock input.

• This is because the frequency of the clock is divided by 2 by the first flip-
flop.

• The Q out put of the second flip-flop is the frequency of the clock divided
by 4, or the frequency of Q1 divided by 2.

56
 Application of Flip-Flops…
• Parallel Data Storage
• It is common to take several bits of data on parallel lines and store them
simultaneously in a group of flip-flops.

57
Exercise:
• A sequential circuit with two D flip-flops A and B, two inputs, x and y; and one
output z is specified by the following next-state and output equations
A(t+1) = 𝑥𝑦 ′
B(t+1) = 𝑥𝐴 + 𝑥𝑦 ′
Z(t) = A
a. Draw the logic diagram of the circuit.

b. List the state table for the sequential circuit.

c. Draw the corresponding state diagram.

58
The end of chapter 5

59