Lecture No.

23, 24, 25, 26

Computer Logic Design

Sequential Logic

1
 Sequential Circuits
• Sequential Circuits
– Digital circuits that use memory elements as part of
their operation
– Characterized by feedback path
– Outputs depend not only on its current inputs but also
on the past sequence of inputs, possibly arbitrarily far
back in time
• Examples
– Counters
– Parallel-to-Serial conversion of byte data
2
Q

Sequential Circuits
• State of Circuit
– Binary information stored in the memory
Q circuit
elements determines the “state” of the
– Output and next state is determined by input
signals and current state of circuit

3
Q

Sequential Circuits
• 2 Major Types of Circuits
• Asynchronous
– Inputs may change at any time Q
– Complicated and maybe unstable because of feedback
• Synchronous
– Input change is only effected at certain times
determined by a master clock (pulse or edge
detection) or master-slave operation

4
 Asynchronous Sequential Circuits
Latch
• Temporary storage device that has two stable states
• Normally has two inputs
• Two complementary outputs available: Q and Q’
• When the latch is set to a certain state it retains its
state unless the inputs are changed to set the latch to
a new state
• A latch serves as a memory element which is able
to retain the information stored in it
5
 S-R (Set-Reset) Latch
R 1 Q

s e d
a
eb Q
2

g at S

O R
N
Input Output
S R Qt+1
0 0 Qt
0 1 0
1 0 1
6
1 1 Invalid
 S-R (Set-Reset) Latch
Truth table Q S R Qt+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Invalid
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Invalid
Characteristic Equation
Qt+1 = S + R’Q; SR = 0
7
 S-R (Set-Reset) Latch
S 1 Q

e d
b as 2 Q
ate R
g
N D
NA Input Output
S’ R’ Qt+1
1 1 Qt
1 0 0
0 1 1
8
0 0 Invalid
 S-R (Set-Reset) Latch

Standard Logic Symbols

S Active-low Q S Active-high Q
Input Input

S-R S-R
Latch Latch

R Q R Q

9
 S-R (Set-Reset) Latch

Timing diagram of active-low input latch

S

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12

10
 S-R (Set-Reset) Latch

Timing diagram of active-high input latch

S

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12

11
Synchronous Sequential Circuits
• Latches
– Asynchronous circuits
– Outputs are transparent to inputs
• Gated or Clocked Latches
– Synchronous circuits b/c clock or enable input dictates when
inputs are latched onto outputs
– May still have both transparent and latched operation if inputs
change while clock is active
• Flip Flops
– Flip-Flops are synchronous bi-stable devices, known as bi-stable
multivibrators
– The output of the flip-flop can only change once by the applied
inputs upon application of clock input
– Edge Triggered or Master Slave
12
 S-R Gated Latch
– Adds a clock (control) input gated to an S-R latch
– S/R inputs are passed on to the latch portion
synchronised by the clock pulse
– Also called Clocked S-R Latch

S 3 1 Q S Q
Gated
EN
CK S-R
CK Latch

R Q
4 2 Q
R 13
 S-R Gated Latch
Truth table Q S R Qt+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Invalid
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Invalid
Characteristic Equation
Qt+1 = S + R’Q; SR = 0
14
 S-R Gated Latch Timing
S

CK

Q
t1 t2 t3 t4 t5 t6 t7 t8

15
 D Gated Latch

D 3 1 Q

CK
EN

4 2 Q

16
 D Gated Latch
Truth table
Q D Qt+1
0 0 0
0 1 1
1 0 0
1 1 1

Characteristic Equation
Qt+1 = D
17
 D Gated Latch Timing

CLK

Q
t1 t2 t3 t4 t5 t6 t7 t8 t9

18
 Latches - Transparency Problem

• What’s transparency?
– Output follows input instantaneously –
tunneling
– Behavior depicted in latches
• The transparency problem
– If output is fed back, circuit may become
unstable
• The solution?
– Master Slave or Edge Triggered FF 19
Transparency Problem

20
Transparency Problem

21
Master Slave Flip Flop

22
Master Slave Flip Flop

23
S-R Master Slave Flip Flop

24
 Master Slave Flip Flops Summary
• Have two stages – Master and Slave
• Each stage works in one half of the clock signal
• Inputs are applied in the first half of the clock signal
• Outputs do not change until the second half of the clock
signal
• Allows digital circuits to operate in synchronization with a
common clock signal
• Inherently slow throughput
• Mostly obsolete
Better Solution:
• Edge Triggered flip-flops
• An edge-triggered flip-flop ignores the pulse while it is at
a constant level and triggers only during a transition of the
clock signal - faster 25
 Edge-Triggered Flip Flops
• Rising Edge Detection Circuit
C LK C LK PULSE

• Timing Diagram
CLK

CLK

CLK PULSE 26
 Edge-Triggered Flip Flops
• Falling Edge Detection Circuit
CLK CLK
CLK PULSE

CLK
• Timing Diagram
CLK

CLK PULSE 27
 Edge-Triggered Flip Flops Logic Symbols

• Positive/Rising Edge S Q
S-R
CLK Flip-Flop

R Q

• Negative/Falling Edge S Q
S-R
CLK Flip-Flop

R Q
28
Edge Triggered S-R Flip-Flop

S 3 1 Q
C LK EDG E

4 2 Q
R

29
 Edge Triggered S-R Flip-Flop
• Function Table for Positive Edge Triggered FF

Input Output
CLK S R Qt+1
0 X X Qt
1 X X Qt
↑ 0 0 Qt
↑ 0 1 0
↑ 1 0 1 30

↑ 1 1 invalid
 Edge Triggered S-R Flip-Flop
• Function Table for Negative Edge Triggered FF

Input Output
CLK S R Qt+1
0 X X Qt
1 X X Qt
↓ 0 0 Qt
↓ 0 1 0
↓ 1 0 1 31

↓ 1 1 invalid
 Edge Triggered S-R Flip-Flop
• Timing Diagram (Pos Edge Triggered FF)
S

CLK

t1 t2 t3 t4 t5 t6 t8 t9 32
t7
 Edge Triggered S-R Flip-Flop
• Timing Diagram (Neg Edge Triggered FF)
S

CLK

t1 t2 t3 t4 t5 t6 t7 t8 t33
9
Pos Edge Triggered D Flip-Flop
Input Output
D Q CLK D Qt+1

CLK
D
Flip-Flop
0 X Qt
Q 1 X Qt
↑ 0 0
↑ 1 1

CLK

Q
34
t1 t2 t3 t4 t5 t6 t7 t8 t9
Neg Edge Triggered D Flip-Flop
D Q Input Output
D
CLK D Qt+1
CLK Flip-Flop

Q
0 X Qt
1 X Qt
↓ 0 0
↓ 1 1
D

CLK

Q
35
t1 t2 t3 t4 t5 t6 t7 t8 t9
 D Flip-Flop Apps – Registers
D0 SET Q0
D Q
D0

CLR Q D1

D1 SET Q1 D2

Connected to inputs of Multiplexer

D Q

D3
CLR Q
CLK

D2 SET Q2
D Q
Q0

CLR Q
Q1

D3 SET Q3
D Q Q2

CLK
Q3
CLR Q 36
t1
Edge Triggered J-K Flip Flop

J 3 1 Q

CLK

4 2 Q
K

37
Edge Triggered J-K Flip Flop
J Q J Q
J-K J-K
CLK Flip-Flop CLK Flip-Flop

K Q K Qt
Q

Input Output Input Output

CLK J K Qt+1 CLK J K Qt+1
0 X X Qt 0 X X Qt
1 X X Qt 1 X X Qt
↑ 0 0 Qt ↓ 0 0 Qt
↑ 0 1 0 ↓ 0 1 0
↑ 1 0 1 ↓ 1 0 1
↑ 1 1 Qt’ ↓ 1 1 Q
38t’
 J-K Flip Flop
Truth table Q J K Qt+1 Operation
0 0 0 0 Hold
0 0 1 0 Reset
0 1 0 1 Set
0 1 1 1 Toggle
1 0 0 1 Hold
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 0 Toggle
Characteristic Equation
Qt+1 = JQ’ + K’Q
39
 Edge Triggered J-K Flip Flop
Pos Edge
J

CLK

t1 t2 t3 t4 t5 t6 t7 t8 t9

Neg Edge
J

CLK

Q
40
t1 t2 t3 t4 t5 t6 t7 t8 t9
 Asynchronous Preset & Clear Inputs
PRE
J 3 1 Q

CLK

4 2 Q
K PRE

CLR J Q
J-K
CLK Flip-Flop

K Q

CLR41
 Asynchronous Preset & Clear Inputs

• Function table
Input Output
_______ _______
PRE CLR Qt+1
0 0 Invalid
0 1 1
1 0 0
Normal clocked
1 1
operation
42
 J-K Flip Flop - Async Preset & Clear Inputs

PRE

CLR
CLK

Q
t3 t4 t8 t9 t 10 t 11 t 14 t 16 t43
18
t1t2 t5 t6 t7 t 12 t 13 t 15 t 17
 J-K Flip Flop Apps - Freq Divider (÷ 2)
1

SET
J Q F
CLK
K CLR Q

C LO C K
In p u t

t1 t2 t3 t4 t5 t6 t7 t44
8
 J-K Flip Flop Apps - Freq Divider (÷ 4)
1 1

SET F1 SET F2
J Q J Q
CLK
K CLR Q K CLR Q
J-K flip-flop 1 J-K flip-flop 2

C LO C K
In p u t

F1 O u tp u t

F2 O u tp u t

t1 t2 t3 t4 t5 t6 t7 t 845
 J-K Flip Flop Apps – Down Counter
1 1

SET F1 SET F2
J Q J Q
CLK
K CLR Q K CLR Q
J-K flip-flop 1 J-K flip-flop 2

C LO C K
In p u t

F1 O u tp u t

F2 O u tp u t

t1 t2 t3 t4 t5 t6 t7 t 846
 J-K Flip Flop Apps – Shift Register

Q0 Q1 Q2 Q3
Data SET SET SET SET
J Q J Q J Q J Q
In

K CLR
Q K CLR
Q K CLR
Q K CLR
Q
J-K flip-flop 1 J-K flip-flop 2 J-K flip-flop 3 J-K flip-flop 4
CLK

47
 Edge Triggered T Flip Flop

T 3 1 Q

CLK

4 2 Q

48
 Edge Triggered T Flip Flop
T Q T Q
J-K J-K
CLK Flip-Flop CLK Flip-Flop

K Qt Q K Qt
Q

Input Output Input Output

CLK T Qt+1 CLK T Qt+1
0 X Qt 0 X Qt
1 X Qt 1 X Qt
↑ 0 1 ↓ 0 1
49
↑ 1 0 ↓ 1 0
 T Flip Flop
Truth table

Q T Qt+1
0 0 0
0 1 1
1 0 1
1 1 0

Characteristic Equation
Qt+1 = TQ’ + T’Q
50
 T Flip Flop

T
CLK

Q
t1 t2 t3 t4 t5 t6 t7 t8 t9

51
Flip Flop Logic Symbols Summary

52
Flip Flop Characteristic Equations

Qt+1 = S + R’Q; SR = 0 Qt+1 = JQ’ + K’Q

Qt+1 = D Qt+1 = TQ’ + T’Q 53

 Flip Flop Excitation Tables
Qt Qt+1 S R Qt Qt+1 D
0 0 0 X 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 0
1 1 X 0 1 1 1

Qt Qt+1 J K Qt Qt+1 T
0 0 0 X 0 0 0
0 1 1 X 0 1 1
1 0 X 1 1 0 1
54
1 1 X 0 1 1 0
 Flip Flop Usage Guide

Type of Application Preferred FF

Transfer of data
RS or D
(e.g. shift registers)
Complementation
T
(e.g. binary counters)
Above or any other
JK
general application 55