COMSATS UNIVERSITY

ISLAMABAD

DIGITAL LOGIC DESIGN

LAB REPORT

Name: Muhammad Mamoon Akber

Registration No.FA17-BEE-084
Section: BEE-2B
LAB # 10
Dated: 23 May, 2018
Submitted to: Maam Asma Ramay

Lab #10: Mealy /Moore Machine

implementation of Sequence Detector
Objective:

This experiment is to design behavioral description of Sequence detector using

Mealy/Moore models of Finite State Machine (FSM) and implement designs into
Xilinx.

Pre-Lab:

Background theory:
The most general model of a sequential circuit has inputs, outputs, and internal states.
It is customary to distinguish between two models of sequential circuits: the Mealy
model and the Moore model. They differ only in the way the output is generated. The
two models of a sequential circuit are commonly referred to as a finite state machine,
abbreviated FSM.

In the Mealy model, the output is a function of both the present state and the input as
shown in Figure 11.1. the outputs may change if the inputs change during the clock
cycle. The output of the Mealy machine is the value that is present immediately before
the active edge of the clock.

Figure 11.1: Mealy machine

In the Moore model, the output is a function of only the present state. A circuit may
have both types of outputs as shown in Figure 11. 2. The outputs of the sequential
circuit are synchronized with the clock, because they depend only on flip-flop outputs
that are synchronized with the clock.
In Lab: Implementation and design of a sequence detector
using Mealy machine

Lab Task #1: Circuit diagram, State table, State diagram

Draw the circuit diagram, state table and state diagram and for sequence detector
(Mealy/Moore)

State table:

Present State Input Next State Output

A B X A(t+1) B(t+1) y

0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 0 1 0
State diagram:

Circuit Diagram:
Lab Task #2: HDL implementation for Mealy machine on FPGA
Write the HDL (Verilog) behavioural description for Mealy based
sequence detector for the given sequence. Simulate the design and paste
the output waveforms
Task #1:

Mealy based Sequence Detector:

Module:
Test Bench:

Wave forms:
Task #2:

Moore based Sequence Detector:

Module:
Test Bench:

Wave forms:
Task #3:
Device Utilization Summary:

Critical Analysis:
 In the above experiment we analyzed the analyzed the working of
Mealy and Moore machines. We also analyzed the behavioral description of Sequence
detector of Mealy and Moore. The most general model of a sequential circuit has
inputs, outputs, and internal states. We also observed that In Mealy model, the output
is the function of both the preset state and the input as shown in figure 10.1. The output
is changed when the inputs change during the clock cycle, where as in Moore model,
the output is a function of only the preset state. We also observed that the outputs of
the sequential circuit are synchronized with the clock, because they depend only on flip
flop outputs that are synchronized with the clock.