DIGITAL LOGIC DESIGN

EEE-241

(Lab Report #6-9)

Name Aitazaz Ahmad Qureshi

Registration CIIT/FA19-BCE-050/ISB
Number

Class BCE-2A

Instructor’s Name Ma’am Asma Ramay

 LAB #06: Xilinx ISE Design Flow with FPGA

Pre-lab Task:
Design a code converter that converts a 4-bit binary number to a 4-bit Gray code.

a) Provide K-Map solution and Boolean expression.

b) Provide gate-level circuit diagram.

State Table for 4-bit Binary number to 4-bit Gray converter:

K-Map and Boolean Expression Calculations:

For W: (By K-MAP Solver)

By Hand:
For X: (By K-MAP Solver)

By Hand:
For Y: (By K-MAP Solver)

By Hand:
For Z: (By K-MAP Solver)

By Hand:
Gate-Level Circuit Diagram of Simplified Equation:
W=A

X = a’b + ab’

Y = b’c + bc’

Z = c’d + cd’
In-Lab Task:
1. Using Gate-level model, write a Verilog description of binary to gray
converter.
2. Using Behavioral model, write a Verilog description of binary to gray
converter.

Gate level code:

Test-Bench for Gate level code:

Output of Gate level code:
Behavioral level code:
Test-Bench for Behavioral code:
Output of Behavioral code:

Post-Lab Task:
Analyze the circuit implementation of In-lab Task 1 and In-lab Task 2
in terms of resources utilization and critical path delay.

Gate level code Design Summary:

Behavioral level Code Design Summary:

Critical Analysis / Conclusion

In this lab we learned, how to convert binary code to grey code. We learned the
data flow and gate level coding for binary to grey code. We also learnt a new
coding technique in Hardware Descriptive Language known as Behavioral level
coding. At the end, we came to know about the design summary of behavioral and
gate level coding.
 LAB #07: Design and Implementation of n-bit
Adder/Subtractor on FPGA

Pre-lab Task:
1. Using Gate-level models, write a Verilog description of a Half-Adder.

Gate-level code for Half-Adder:

2. Write Verilog Code for Full-Adder.

Gate-level code for Full-Adder:

In-Lab Task:
Implement a 4-bit binary Adder / Subtractor along with Test Bench for adder and
subtractor respectively.

4-bit Binary Adder / Subtractor:

Test-Bench for 4-bit Binary Adder:

Output of 4-bit Binary Adder:

Test-Bench for 4-bit Binary Subtractor:

Output of 4-bit Binary Subtractor:

Observation Table for 4-bit Binary Adder / Subtractor

Bit
V Calculated Cout Cin

3 2 1 0

A 0 0 0 0 0

B 0 0 0 0 0
1 Sum 0 0 0 0 0 0

Difference 1 0 0 0 0 1

A 0 0 1 1 0

B 0 0 1 1 0
2 Sum 0 0 1 1 0 0

Difference 1 0 1 1 0 1

A 1 0 1 0 1

B 1 0 1 0 1
3 Sum 1 0 1 0 0 0

Difference 0 0 1 1 0 1

A 1 1 1 1 1

B 1 1 1 1 1
4 Sum 1 1 1 1 0 0

Difference 1 0 0 0 1 1
4-bit Magnitude Comparator:

Test-Bench for Magnitude Comparator:

Magnitude Comparator Output:

Post-Lab Task:
Using Behavioral model, write a Verilog description of n-bit Adder / Subtractor.

o Make one stimulus for two different parameter values and show the wave
forms result.

Analyze the circuit implementation of 4-bit Adder/Subtractor by structural and

behavioral level coding in terms of resource utilization and critical path delay.
n-bit Adder/Subtractor Code:

Test-Bench for n-bit Adder:

Output of n-bit Adder:

Test-Bench for n-bit Subtractor:

Output of n-bit Subtractor:

Resource Utilization 4-bit Behavioral level code

Resource Utilization of 4-bit Structural level code:

Critical Analysis:
In this lab i learned about binary Adder/Subtractor, their implementation on
Verilog. I also learned a new keyword known as Parameter used to write n-bit
codes on Verilog.
I also wrote 4-bit Adder/Subtractor codes on Verilog and checked their output on
Xilinx.
 LAB #08: Design and Implementation of n-bit
Binary Multiplier on FPGA

Pre-Lab Task:
Structural level code for 2 bit by 2 bit multiplier:
 Test-Bench for 2 bit by 2 bit multiplier:

2 bit by 2 bit multiplier output:

Proteus Simulation of 4 bit by 2 bit multiplier:
In-Lab Task:

4 bit by 3 bit multiplier Structural level code:

Test Bench for 4 bit by 3 bit multiplier:

4 bit by 3 bit multiplier output:

Post-Lab Task:
1. Using Behavioral model, write a Verilog description of parametrized Multiplier.
o Make one stimulus for two different parameter values and show the wave
forms results.
2. Analyze the circuits’ implementation of Structural Binary Multiplier and Behavioral-
Level Multiplier, in terms of resource utilization and critical path delay.

Behavioral Level Code for Parametrized Multiplier:

Test-Bench for Parametrized Multiplier:

Stimulus for two parameter values:

Resource Utilization of 4-bit Multiplier:

Using Structural level coding:

Using Behavioral level coding:

Critical Analysis:
In this lab I learned the implementation of n-bit multiplier on Verilog. I learned the structural
and behavioral level coding technique for multiplier on Verilog. I also learned the
implementation of n-bit multiplier using parametrized Verilog description. Then I did a
simulation of multiplier code on Proteus.
 LAB #09: Design and Implementation of BCD
to 7-Segment Decoder on FPGA

In-Lab Task:
Proteus Simulation of BCD to 7-Segment Display:

BCD to 7-Segment Display Truth Table:

BCD 7-Segment

D C B A a b c d e f g DP Hex

0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 0 1 1 0 0 1 1 1 1 1 1

0 0 1 0 0 0 1 0 0 1 0 1 2

0 0 1 1 0 0 0 0 1 1 0 1 3

0 1 0 0 1 0 0 1 1 0 0 1 4
 0 1 0 1 0 1 0 0 1 0 0 1 5

0 1 1 0 0 1 0 0 0 0 0 1 6

0 1 1 1 0 0 0 1 1 1 1 1 7

1 0 0 0 0 0 0 0 0 0 0 1 8

1 0 0 1 0 0 0 1 1 0 0 1 9

Post-Lab Task:
BCD to 7-Segment Display Verilog Code:
Test-Bench for BCD to 7-Segment Display:

Output of BCD to 7-Segment Display:

Resource Utilization of BCD to 7-Segment Display:

Critical Analysis:
In this lab I came to know about 7-segment display and its use in electronics. I learned the
conversion of BCD to 7-Segment display using Verilog and also simulated it on Proteus. Also, I
learned the use of CASE statements in the conversion BCD to 7-Segment display.