DIGITAL LOGIC DESIGN

EEE-241

Lab 4

Name Aitazaz Ahmad Qureshi

Registration CIIT/FA19-BCE-050/ISB
Number

Class BCE-2A

Ma’am Asma Ramay

Instructor’s Name
Boolean Equations:

Sum of Min-Terms of F:
(A’B’CD)+(A’BCD)+(AB’C’D’)+(ABC’D)+(ABCD’)+(ABCD)

Reduced SOP Form:

(AB’C’D’)+(A’CD)+(ABC)+(ABD)

Product of Max Terms of F:

[(A+B+C+D).(A+B+C+D’).(A+B+C’+D).(A+B’+C+D).(A+B’+C+D’).(A+
B’+C’+D). (A’+B+C+D’).(A’+B+C’+D).(A’+B+C’+D’).(A’+B’+C+D)]

Reduced POS Form:

(A+C).(A’+B+C’).(A+C’+D).(A’+B+C+D’).(A’+B’+C+D)
SOP FORM CIRCUIT DIAGRAM: (F2)

REDUCED SOP FORM BY NAND:

POS FORM CIRCUIT DIAGRAM: (F3)

REDUCED POS FORM BY NOR:

 F2 F3

A B C D F F1 NAND NOR

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 0 1 1 1 1 1 1

0 1 0 0 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 0 0 0 0 0

0 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 1 1 1 1

1 1 1 0 1 1 1 1

1 1 1 1 1 1 1 1
 POST LAB TASK:

VERILOG FOR REDUCED SOP (F2):

TEST BENCH FOR REDUCED SOP:

SOP REDUCED FORM:

VERILOG FOR REDUCED POS (F3):

TEST BENCH FOR REDUCED POS:

POS REDUCED FORM: