DPSD Unit 3

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CS8351 DIGITAL
PRINCIPLES AND SYSTEM
DESIGN
Department: COMPUTER SCIENCE AND ENGINEERING
Batch/Year: BATCH 2019-23/II
Created by:
Dr. Sandra Johnson, Professor, CSE, RMKEC
Dr. S Selvi , Professor, CSE, RMKEC
Dr. B PrathushaLaxmi , ASP, IT, RMKEC
Dr. M A Berlin , ASP, CSE, RMDEC
Ms. J Geethapriya , AP, CSE, RMDEC
Dr. V Prasanna Srinivasan , ASP, IT, RMDEC
Ms P Prem Priya , AP, CSE, RMKCET
Date: 30th August 2020

Table of Contents
Sl. No. Contents Page No.
117 Contents 5
2 Course Objectives 6
3 Pre Requisites (Course Name with Code) 8
4 Syllabus (With Subject Code, Name, LTPC details) 10
5 Course Outcomes (6) 12
6 CO-PO/PSO Mapping 14
Lecture Plan (S.No., Topic, No. of Periods, Proposed
7 date, Actual Lecture Date, pertaining CO, Taxonomy 16
level, Mode of Delivery)
8 Activity based learning 18
Lecture Notes ( with Links to Videos, e-book reference,
9 20
PPTs, Quiz and any other learning materials )
Assignments ( For higher level learning and Evaluation
10 140
- Examples: Case study, Comprehensive design, etc.,)
11 Part A Q & A (with K level and CO) 142
12 Part B Qs (with K level and CO) 155

Supportive online Certification courses (NPTEL,
13 163
Swayam, Coursera, Udemy, etc.,)
14 Real time Applications in day to day life and to Industry 165
Contents beyond the Syllabus ( COE related Value
15 167
added courses)
16 Assessment Schedule ( Proposed Date & Actual Date) 169
17 Prescribed Text Books & Reference Books 171
18 Mini Project 173

Course Objectives
COURSE OBJECTIVES
To design digital circuits using simplified Boolean
functions.
To analyze and design combinational circuits.
To analyze and design synchronous sequential
circuits.
To analyze and design asynchronous sequential
circuits.
To understand Programmable Logic Devices.
To write HDL code for combinational and sequential
circuits.
PRE REQUISITES
PRE REQUISITES
SUBJECT CODE: NIL
SUBJECT NAME:
Syllabus
Syllabus
CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN LTPC
4004
OBJECTIVES:
• To design digital circuits using simplified Boolean functions
• To analyze and design combinational circuits
• To analyze and design synchronous and asynchronous sequential circuits
• To understand Programmable Logic Devices
• To write HDL code for combinational and sequential circuits
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 12

Number Systems - Arithmetic Operations - Binary Codes- Boolean Algebra and Logic
Gates - Theorems and Properties of Boolean Algebra - Boolean Functions - Canonical
and Standard Forms - Simplification of Boolean Functions using Karnaugh Map -
Logic Gates – NAND and NOR Implementations.
UNIT II COMBINATIONAL LOGIC 12

Combinational Circuits – Analysis and Design Procedures - Binary Adder-Subtractor -
Decimal Adder - Binary Multiplier - Magnitude Comparator - Decoders – Encoders –
Multiplexers - Introduction to HDL – HDL Models of Combinational circuits.
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 12

Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked
Sequential Circuits - State Reduction and Assignment - Design Procedure - Registers
and Counters - HDL Models of Sequential Circuits.
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 12

Analysis and Design of Asynchronous Sequential Circuits – Reduction of State and
Flow Tables – Race-free State Assignment – Hazards.
UNIT V MEMORY AND PROGRAMMABLE LOGIC 12

RAM – Memory Decoding – Error Detection and Correction - ROM - Programmable
Logic Array – Programmable Array Logic – Sequential Programmable Devices.
TOTAL : 60 PERIODS
Course Outcomes
Course Outcomes
Course Description Knowledge
Outcomes Level
Design Digital Circuits using simplified Boolean
CO1 K4
functions
CO2 Analyze and Design Combinational Circuits K4
CO3 Analyze and Design Synchronous Sequential Circuits K4
CO4 Analyze and Design Asynchronous Sequential Circuits K4
CO5 Implement designs using Programmable Logic Devices K3

Write HDL code for Combinational and Sequential
CO6 K3
Circuits
Knowledge Level Description
K6 Evaluation
K5 Synthesis
K4 Analysis
K3 Application
K2 Comprehension
K1 Knowledge
CO – PO/PSO Mapping
CO – PO /PSO Mapping Matrix
CO PO PO PO PO PO PO PO PO PO PO PO PO PS PS PS
1 2 3 4 5 6 7 8 9 10 11 12 O1 O2 03
1 3 2 1 1 3
2 3 3 2 2 3
3 3 3 2 2 3
4 3 3 2 2 3
5 3 3 2 2 3
6 3 2 1 1 3
Lecture Plan
Unit III
Lecture Plan – Unit 3 - SYNCHRONOUS
SEQUENTIAL LOGIC
Sl. Topic Numbe Proposed Actual CO Taxo Mode
No r of Date Lecture nomy of
. Period Date Level Deliver
s y
1 Sequential 2 CO3 K4 PPT /
Circuits - Online
Storage Lecture
Elements:
Latches ,
Flip-Flops
2 Analysis of 2 CO3 K4 PPT /
Clocked Online
Sequential Lecture
Circuits -
State
Reduction
and
Assignment
3 Design 2 CO3 K4 PPT /
Procedure Online
Lecture
4 Registers 2 CO3 K4 PPT /
and Online
Counters Lecture
5 HDL Models 2 CO6 K3 PPT /

of Online
Sequential Lecture
Circuits
Activity Based Learning
Unit III
Activity Based Learning
1 Quiz – 1 65
2 Online Quiz – Flip Flops 90
3 Games of Shift 108
4 Crossword Puzzle - Counters 132

Lecture Notes – Unit III
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC

Sequential Circuits
1 Asynchronous Sequential Circuits 23
Synchronous Sequential Circuits
2 Latches vs Flip Flops 26
Types of Latches
SR Latch
SR Latch with NOR gate
3 28
SR Latch with NAND gate
SR Latch with Control Input
D Latch – Edge triggered Master-Slave D Flip Flop
Flip Flops
JK Flip Flop
4 T Flip Flop 38
Master Slave JK Flip Flop
Excitation Table for Flip Flops
5 Mealy Model & Moore Model 47
Analysis of Clocked Sequential Circuits – e.g. for Mealy
6 49
Model; Moore Model
State Reduction and Assignment
7 Algorithm 66
Example
8 Design Procedure 76
Examples – for design of Synchronous Sequential

9 77
Circuits
Realization of one flip flop by another flip flop
SR Flip-Flop to other Flip-Flop Conversions0
10 D Flip-Flop to other Flip-Flop Conversions 83
JK Flip-Flop to other Flip-Flop Conversions
T Flip-Flop to other Flip-Flop Conversions
11 4 bit registers 91
UNIT III SYNCHRONOUS SEQUENTIAL LOGIC
Shift Registers
Serial In − Serial Out shift register
12 Serial In − Parallel Out shift register 91

Parallel In − Serial Out shift register
Parallel In − Parallel Out shift register
Serial Addition
Serial Transfer
13 109
Register with Parallel load
Serial Adder using JK Flip Flop
14 Universal Shift Register 114

Counters
Binary Ripple Counter – using T / D / JK Flip Flop
15 115
BCD Ripple Counter
Asynchronous Mod-n Counter
Synchronous Counters
Binary Up Counter
Binary Down Counter
16 121
Binary Up-Down Counter
BCD Counter
Binary Counter with Parallel Load
17 Non Binary Counters 133
18 Ring Counters 136
19 Johnsons Counter 137

1. SEQUENTIAL CIRCUITS
Introduction of Sequential Circuits
The technology enabling and supporting the devices such as digital cameras, cell
phones, personal computers and navigation receivers are critically dependent on
electronic components that can store information, i.e., have memory.
The digital circuits considered thus far have been combinational—their output
depends only and immediately on their inputs—they have no memory, i.e.,
dependence on past values of their inputs.
Sequential circuits, however, act as storage elements and have memory. They can
store, retain, and then retrieve information when needed at a later time.
Definition of Sequential Circuits
A sequential circuit consists of a combinational circuit to which storage elements

are connected to form a feedback path.
The output of a sequential circuit is a function of both the inputs and the present
state of the storage elements.
Block diagram of a Sequential Circuit
The storage elements are devices capable of storing binary information.
The binary information stored in these elements at any given time defines the
state of the sequential circuit at that time.
The sequential circuit receives binary information from external inputs that,
together with the present state of the storage elements, determine the binary
value of the outputs.
These external inputs also determine the condition for changing the state in the
storage elements.
Types of Sequential Circuits
1. Synchronous Sequential Circuit/ Clocked Sequential Circuit
2. Asynchronous Sequential Circuit/ Unclocked Sequential Circuit
1. Synchronous Sequential Circuit
A synchronous sequential circuit is a system whose behaviour can be defined

from the knowledge of its signals at discrete instants of time.
Synchronization is achieved by a timing device called a clock generator, which

provides a clock signal having the form of a periodic train of clock pulses.
Block diagram of Synchronous Sequential Circuit
Timing diagram of clock pulses

2. Asynchronous Sequential Circuit

The behaviour of an asynchronous sequential circuit depends upon the input
signals at any instant of time and the order in which the inputs change.
The generation of output is not governed by clock signal. The storage elements
commonly used in asynchronous sequential circuits are time-delay devices.
Differences between Synchronous and Asynchronous

Sequential Circuits
2. LATCHES vs. FLIP FLOPS
Memory Elements/ Storage Elements
A Storage element is a digital circuit that can maintain a binary state indefinitely
until directed by an input signal to switch states.
The two storage elements are:
1. Latches
2. Flip Flops
Differences between Latches and Flip Flops
Clock Response in Latches

Latches are level triggered (i.e.) the circuit will become operational when the
clock pulse is on a particular level. Latches responds to a change in the level
(positive or negative level) of a clock pulse.
Response to Positive level

The circuit will become active at positive level (i.e. level 1)
2. LATCHES vs. FLIP FLOPS
Response to Negative level
The circuit will become active at negative level (i.e. level 0)
Clock Response in Flip Flops

Flip flops are edge triggered. (i.e.) the circuit will become operational only during
Signal Transition.
A clock pulse goes through two transitions: from 0 to 1 (called as positive edge)
and the return from 1 to 0 (called as negative edge)
Response to Positive Edge
The circuit will become operational when the signal transits from Level 0 to Level 1
Response to Negative Edge
The circuit will become operational when the signal transits from Level 1 to Level 0
3. LATCHES - SR LATCH WITH NOR GATES
3.1 SR LATCH
The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled
NAND gates, and two inputs labelled S for set and R for reset.
3.1.1 SR LATCH WITH NOR GATES

SR Latch can be constructed with two cross-coupled NOR gates.
The latch has two useful states. When output Q = 1 and Q‘ = 0, the latch is said
to be in the set state . When Q = 0 and Q‘ = 1, it is in the reset state .
Outputs Q and Q are normally the complement of each other.
Graphic Symbol Logic diagram
Truth table of NOR Function table of SR Latch with NOR gate

3.1.1 SR LATCH WITH NOR GATES
Working of SR Latch with NOR gate
Initially, both inputs of this latch remain at 0, unless the state has to be changed.
When S=1, R=0 (Set state)
The application of a ‗1‘ to the S input causes the latch to shift to the SET state
and the outputs of the latch are Q=1 and Q‘=0.
When S=0, R=0 (after S=1 & R=0)
When the S input goes back to ‗0‘ , the previous state of Q and Q‘ are retained by
the latch. Here, the latch remains in the ‗Set‘ state.
When S=0, R=1 (Reset state)
After both inputs return to ‗0‘, it is then possible to shift to the RESET state by
applying a ‗1‘ to the R input.
In this case, the outputs of the latch are Q=0 and Q‘=1.
When the R input goes back to ‗0‘ , the previous state of Q and Q‘ are retained by
the latch. Here, the latch remains in ‗Reset‘ state.
Thus, when both inputs S and R are equal to 0, the latch can be in either the set
or the reset state, depending on which input (S or R) was most recently a ‗1‘.
When S=1, R=1
If a ‗1‘ is applied to both the S and R inputs of the latch, both outputs go to ‗0‘.
(i.e. Q and Q‘ are not mutually complement of each other).
This action produces an undefined next state.

3.1.2 SR LATCH WITH NAND GATES (S’R’ LATCH)
SR Latch can be constructed with two cross-coupled NAND gates.
The latch has two useful states. When output Q = 0 and Q‘ = 1, the latch is said
to be in the set state . When Q = 1 and Q = 0, it is in the reset state .
Outputs Q and Q are normally the complement of each other.
Graphic Symbol Logic diagram
Truth table of NAND Function table of SR Latch with NAND gate
Working of SR Latch with NAND gate
Initially, both inputs of this latch remain at 1, unless the state has to be changed.
When S=0, R=1 (Set state)
The application of a ‗0‘ to the S input causes the latch to shift to the SET state
and the outputs are Q=1 and Q‘=0.
3.1.2 SR LATCH WITH NAND GATES (S’R’ LATCH)
When the S input goes back to ‗1‘ , the previous state of Q and Q‘ are retained by
the latch. Here, the latch remains in ‗Set‘ state.
When S=1, R=0 (Reset state)
After both inputs return to ‗1‘, it is then possible to shift to the RESET state by
applying a ‗0‘ to the R input.
In this case, the outputs of the latch are Q=0 and Q‘=1.
When the R input goes back to ‗1‘ , the previous state of Q and Q‘ are retained by
the latch. Here, the latch remains in ‗Reset‘ state.
Thus, when both inputs S and R are equal to ‗1‘, the latch can be in either the set
or the reset state, depending on which input(S or R) was most recently a ‗0‘.
When S=0, R=0
If a ‗0‘ is applied to both the S and R inputs of the latch, both outputs go to ‗1‘
(i.e. Q and Q‘ are not mutually complement of each other).
This action produces an undefined next state.
When comparing the NAND with the NOR latch, it is noted that the input signals
for the NAND require the complement of those values used for the NOR latch.
Because the NAND latch requires a 0 signal to change its state, it is sometimes
referred to as an S’R’ latch.
3.1.3 SR LATCH WITH CONTROL INPUT
The operation of the basic SR latch can be modified by providing an additional

input signal that controls when the state of the latch can be changed by
determining whether S and R (or S‘ and R‘) can affect the circuit.
An SR latch with a control input consists of the basic SR latch and two additional
NAND gates.
The control input En acts as an enable signal for the other two inputs.
Logic Diagram Function table
Working of the SR Latch with Control Input
The outputs of the NAND gates stay at the logic-1 level as long as the enable
signal remains at 0.
When the enable input goes to 1, information from the S or R input is allowed to
affect the latch.
When En=1, S=1, R=0, the SET state is reached
When En=1, S=0, R=1, the RESET state is reached
When En=1,S=0, R=0, the state of the circuit does not change
When En=1,S=1, R=1, an indeterminate condition occurs. This indeterminate

condition makes this circuit difficult to manage, and it is seldom used in practice.
When En returns to 0, the circuit remains in its current state.

3.2 D LATCH (Transparent Latch)
One way to eliminate the undesirable condition of the indeterminate state

in the SR latch is to ensure that inputs S and R are never equal to 1 at the
same time. This is done in the D latch.
This latch has only two inputs: D (data) and En (enable)
Graphic Symbol Logic Diagram
Function Table of D Latch
Working of D Latch
The D input goes directly to the S input, and its complement is applied to the R
input.
As long as the enable input is at 0, the cross-coupled SR latch has both inputs at
the 1 level and the circuit cannot change state regardless of the value of D .
The D input is sampled when En = 1.
If D = 1, the Q output goes to 1, placing the circuit in the SET state.
If D = 0, output Q goes to 0, placing the circuit in the RESET state.

3.2 D LATCH (Transparent Latch)
It is named as D latch because of its ability to hold data in its internal storage.
It is suited for use as a temporary storage for binary information between a unit
and its environment.
The binary information present at the data input of the D latch is transferred to
the Q output when the enable input is asserted.
As long as the enable input is asserted, the output follows changes in the data
input.
This situation provides a path from input D to the output, and for this reason, the
circuit is often called a transparent latch.
When the enable input signal is de-asserted, the binary information that was
present at the data input at the time the transition occurred is retained (i.e.,
stored) at the Q output until the enable input is asserted again.
3.2 EDGE TRIGGERED MASTER SLAVE D- FLIP FLOP
A D flip-flop is constructed with two D latches and an inverter
Graphic symbol of Edge triggered D-Flip Flop
Positive - edge Negative – edge

Block diagram of Master Slave D-Flip Flop
Working of Master Slave D – Flip flop
The first latch is called the master and the second the slave. The circuit samples
the D input and changes its output Q only at the negative edge of the
synchronizing or controlling clock (designated as Clk ).
When the clock is 0, the output of the inverter is 1. The slave latch is enabled,
and its output Q is equal to the master output Y . The master latch is disabled
because Clk = 0.
When the clock is 1, the data from the external D input are transferred to the
master. The slave, however, is disabled as long as the clock remains at the 1 level,
because its enable input is equal to 0.
Any change in the input changes the master output at Y, but cannot affect the
slave output.
When the clock pulse returns to 0, the master is disabled and is isolated from the
D input.
At the same time, the slave is enabled and the value of Y is transferred to the
output of the flip-flop at Q .
Thus, a change in the output of the flip-flop can be triggered only by and during
the transition of the clock from 1 to 0.
The behaviour of the master–slave flip-flop dictates that
(1) The output may change only once
(2) A change in the output is triggered by the negative edge of the clock
(3) The change may occur only during the clock‘s negative level. The value that is
produced at the output of the flip-flop is the value that was stored in the master
stage immediately before the negative edge occurred
EDGE TRIGGERED D FLIP FLOP USING THREE SR LATCHES
An edge triggered D Flip flop can be constructed using three SR latches as

follows.
Two latches respond to the external D (data) and Clk (clock) inputs. The third
latch provides the outputs for the flip-flop.
Logic Diagram of Positive edge triggered D Flip Flop

Initially, the S and R inputs of the output latch are maintained at the logic-1 level
when Clk = 0. This causes the output to remain in its present state.
Input D may be equal to 0 or 1.
If D = 0 when Clk goes from 0 to 1, R changes to 0. This causes the flip-flop

to go to the reset state(R=0), making Q = 0. If there is a change in the D input
while Clk = 1, R remains at 0 because Q is 0. Thus, the flip-flop is unresponsive to
further changes in the input.
If D = 1 when Clk goes from 0 to 1, S changes to 0. This causes the flip flop
to go to the set state(S=0), making Q = 1. If there is any change in D input while
Clk = 1, S remains at 0. Thus, the Flip flop output is not affected.
When the clock returns from 1 to 0, the output of the Flip flop is not affected
and remains in its present state
In sum, when the input clock in the positive-edge-triggered flip-flop makes a

positive transition(0 to 1), the value of D is transferred to Q .
A negative transition of the clock (1 to 0) does not affect the output, nor is the
output affected by changes in D when Clk is in the steady logic-1 level or the
logic-0 level. Hence, this type of flip-flop responds to the transition from 0 to 1
and nothing else.
4. FLIP FLOP
4.1 JK FLIP FLOP:
JK means Jack Kilby, Texas Instrument (TI) Engineer, who invented IC in 1958. JK
Flip-Flop has two inputs J(set) and K(reset). A JK Flip-Flop can be obtained from
the clocked SR Flip-Flop by augmenting two AND gates as shown below.
The data input J and the output Q‘ are applied o the first AND gate and its
output (JQ‘) is applied to the S input of SR Flip-Flop. Similarly, the data
input K and the output Q are applied to the second AND gate and its
output (KQ) is applied to the R input of SR Flip-Flop.
J= K= 0
When J=K= 0, both AND gates are disabled. Therefore clock pulse have no
effect, hence the Flip-Flop output is same as the previous output.
4.1 JK FLIP FLOP
J= 0, K= 1
When J= 0 and K= 1, AND gate 1 is disabled i.e., S= 0 and R= 1. This

condition will reset the Flip-Flop to 0.
J= 1, K= 0
When J= 1 and K= 0, AND gate 2 is disabled i.e., S= 1 and R= 0.

Therefore the Flip-Flop will set on the application of a clock pulse.
J= K= 0
When J=K= 1, it is possible to set or reset the Flip-Flop. If Q is High, AND

gate 2 passes on a reset pulse to the next clock. When Q is low, AND gate
1 passes on a set pulse to the next clock. Either way, Q changes to the
complement of the last state i.e., toggle. Toggle means to switch to the
opposite state.
The truth table of JK Flip-Flop is given below.
Inputs Output
CLK State
J K Qn+1
No
1 0 0 Qn
Change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Qn‘ Toggle
4.1 JK FLIP FLOP
Input and Output Waveforms for JK Flip Flop
Characteristic table and Characteristic equation:
The characteristic table for JK Flip-Flop is shown in the table below. From the
table, K-map for the next state transition (Qn+1) can be drawn and the simplified
logic expression which represents the characteristic equation of JK Flip-Flop can
be found.
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Characteristic equation: Qn+1= JQ’+ K’Q

4.2 T FLIP FLOP
T FLIP FLOP
The T (Toggle) Flip-Flop is a modification of the JK Flip-Flop. It is obtained from

JK Flip-Flop by connecting both inputs J and K together, i.e., single input.
Regardless of the present state, the Flip-Flop complements its output when the
clock pulse occurs while input T= 1.
When T= 0, Qn+1= Qn, ie., the next state is the same as the present state and no
change occurs.
When T= 1, Qn+1= Qn‘, i.e., the next state is the complement of the present
state.
4.2 T FLIP FLOP
The truth table of T Flip-Flop is given below.
T Qn+1 State
0 Qn No Change
1 Qn‘ Toggle
The characteristic table for T Flip-Flop is shown below and characteristic equation is
derived using K-map.
Qn T Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
K-map Simplification:
Characteristic equation: Qn+1= TQn’+ T’Qn

4.3 MASTER SLAVE JK FLIP FLOP
Master-Slave JK FLIP FLOP
A master-slave Flip-Flop is constructed using two separate JK Flip-Flops. The first

Flip-Flop is called the master. It is driven by the positive edge of the clock pulse.
The second Flip-Flop is called the slave. It is driven by the negative edge of the
clock pulse. The logic diagram of a master-slave JK Flip-Flop is shown below.
When the clock pulse has a positive edge, the master acts according to its J- K
inputs, but the slave does not respond, since it requires a negative edge at the
clock input.
When the clock input has a negative edge, the slave Flip-Flop copies the master
outputs. But the master does not respond since it requires a positive edge at its
clock input.
The clocked master-slave J-K Flip-Flop using NAND gates is shown below.
4.2 APPLICATION TABLE OR EXCITATION TABLE FOR
FLIP FLOPS
The characteristic table is useful for analysis and for defining the operation of
the Flip-Flop. It specifies the next state (Qn+1) when the inputs and present state
are known.
The excitation or application table is useful for design process. It is used to

find the Flip-Flop input conditions that will cause the required transition, when the
present state (Qn) and the next state (Qn+1) are known.
SR FLIP FLOP
SR Flip Flop Characteristics Table SR FF Modified Characteristics Table
Present Next Present Next

Inputs Inputs Inputs
State State State State
Qn S R Qn+1 Qn Qn+1 S R S R
0 0 0 0 0 0 0 0
0 x
0 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 1 0
0 1 1 x 1 0 0 1 0 1
1 0 0 1 1 1 0 0
x 0
1 0 1 0 1 1 1 0
1 1 0 1
1 1 1 x
The following table is the excitation table for SR Flip-Flop. It consists of present
state (Qn), next state (Qn+1) and a column for each input to show how the
required transition is achieved.
FLIP FLOPS
There are 4 possible transitions from present state to next state. The required
Input conditions for each of the four transitions are derived from the information
available in the characteristic table. The symbol ‗x‘ denotes the don‘t care
condition, it does not matter whether the input is 0 or 1.
Excitation Table for SR Flip Flop
Present Next
Inputs
State State
Qn Qn+1 S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0
Similar analysis can be done for JK, D and T flip flops for obtaining the respective
excitation tables
JK FLIP FLOP
JK Flip Flop Characteristics Table JK FF Modified Characteristics Table

Inputs Inputs Inputs
Qn J K Qn+1 Qn Qn+1 J K J K
0 0 0 0 0 0 0 0
0 x
0 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0
1 x
0 1 1 1 0 1 1 1
1 0 0 1 1 0 0 1
x 1
1 0 1 0 1 0 1 1
1 1 0 1 1 1 0 0
x 0
1 1 1 0 1 1 1 0
FLIP FLOPS
Excitation Table for JK Flip Flop

Present Next
Inputs
State State
Qn Qn+1 J K
0 0 0 x
0 1 1 x
1 0 x
1
1 1 x 0
D FLIP FLOP
D Flip Flop Characteristics Table D Flip Flop Excitation Table

Input Input
Qn D Qn+1 Qn Qn+1 D
0 0 0 0 0 0
0 1 1
0 1 1
1 0 0
1 0 0
1 1 1
1 1 1
T FLIP FLOP
T Flip Flop Characteristics Table T Flip Flop Excitation Table

Input Input
Qn T Qn+1 Qn Qn+1 T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
5. MODELS FOR REPRESENTING SEQUENTIAL
CIRCUITS
In synchronous or clocked sequential circuits, clocked Flip-Flops are used as

memory elements, which change their individual states in synchronism with the
periodic clock signal. Therefore, the change in states of Flip-Flop and change in
state of the entire circuits occur at the transition of the clock signal.
The synchronous or clocked sequential networks are represented by two
models.
• Moore model: The output depends only on the present state of the Flip-Flops.
• Mealy model: The output depends on both the present state of the Flip-Flops
and on the inputs.
Moore model
In the Moore model, the outputs are a function of the present state of the
Flip- Flops only. The output depends only on present state of Flip-Flops, it
appears only after the clock pulse is applied, i.e., it varies in synchronism
with the clock input.
Mealy model
In the Mealy model, the outputs are functions of both the present state of the
Flip-Flops and inputs.
5. MEALY & MOORE MODEL
Difference between Moore and Mealy model
Sl.
Moore model Mealy model
No
Its output is a function of present Its output is a function of present
1
state only. state as well as present input.
Input changes does not affect the Input changes may affect the output
2
output. of the circuit.
It requires more number of states It requires less number of states for
3
for implementing same function. implementing same function.
6. ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
The behavior of a sequential circuit is determined from the inputs, outputs and
the state of its Flip-Flops. The outputs and the next state are both a function of
the inputs and the present state.
The analysis of a sequential circuit consists of obtaining a table or diagram from

the time sequence of inputs, outputs and internal states.
State Diagram
State diagram is a pictorial representation of a behavior of a sequential circuit.
In the state diagram, a state is represented by a circle and the transition between
states is indicated by directed lines connecting the circles.
A directed line connecting a circle with circle with itself indicates that next state is
same as present state.
The binary number inside each circle identifies the state represented by the circle.
In case of Moore circuit, the directed lines are labeled with only one binary
number representing the state of the input that causes the state transition. The
output state is indicated within the circle, below the present state because output
state depends only on present state and not on the input.
State diagram for Mealy circuit State diagram for Moore circuit
State Table
State table represents relationship between input, output and Flip-Flop states.
It consists of three sections labeled present state, next state and output.
The present state designates the state of Flip-Flops before the occurrence of a
clock pulse, and the output section gives the values of the output variables during
the present state.
Both the next state and output sections have two columns representing two
possible input conditions: X= 0 and X=1.
Next state Output

Present state
X= 0 X= 1 X= 0 X= 1
AB AB AB Y Y
a a c 0 0
b b a 0 0
c d c 0 1
d b d 0 0
In case of Moore circuit, the output section has only one column since output
does not depend on input.
Next state Output

Present state
X= 0 X= 1 Y
AB AB AB
a a c 0
b b a 0
c d c 1
d b d 0
State Diagram
It is an algebraic expression that specifies the condition for a Flip-Flop state

transition.
The Flip-Flops may be of any type and the logic diagram may or may not include
combinational circuit gates.
ANALYSIS PROCEDURE FOR CLOCKED SYNCHRONOUS SEQUENTIAL CIRCUITS
The synchronous sequential circuit analysis is summarizes as given below:
Assign a state variable to each Flip-Flop in the synchronous sequential circuit.
Write the excitation input functions for each Flip-Flop and also write the Moore/
Mealy output equations.
Substitute the excitation input functions into the bistable equations for the Flip-
Flops to obtain the next state output equations.
Obtain the state table and reduced form of the state table.
Draw the state diagram by using the second form of the state table.
Analysis of Mealy Model
1. A sequential circuit has two JK Flip-Flops A and B, one input (x) and one
output (y). the Flip-Flop input functions are,
JA= B+ x JB= A’+ x’
K A= 1 K B= 1
and the circuit output function, Y= xA’B.
a) Draw the logic diagram of the Mealy circuit,
b) Tabulate the state table,
c) Draw the state diagram.
Solution
Logic Diagram
State Table
To obtain the next-state values of a sequential circuit with JK Flip-Flops, use the JK
Flip-Flop characteristics table.
Present
Input Flip-Flop Inputs Next state Output
state
A B x JA= B+ x KA= 1 JB= A’+ x’ KB= 1 A(t+1) B(t+1) Y= xA’B
0 0 0 0 1 1 1 0 1 0
0 0 1 1 1 1 1 1 1 0
0 1 0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0 0 0
1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 1 0 0 0
Modified State Table
Next state Output

Present
state x= 0 x= 1 x= 0 x= 1
A B A B A B y y
0 0 0 1 1 1 0 0
0 1 1 0 1 0 0 1
1 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0
State Diagram
2. A sequential circuit with two ‗D‘ Flip-Flops A and B, one input (x) and
one output (y). the Flip-Flop input functions are:
DA= Ax+ Bx
DB= A’x and the circuit output function is,
Y= (A+ B) x’.
(a) Draw the logic diagram of the circuit,
(b) Tabulate the state table,
(c) Draw the state diagram.
Solution
Logic Diagram
State Table
Present
state
D A= D B= Y=
A B x A(t+1) B(t+1)
Ax+Bx A’x (A+B)x’
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 1
1 1 1 1 0 1 0 0
Next state Output

Present x=
state x= 0 x= 1 x= 0
1
A B A B A B Y Y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
State Diagram
3. Analyze the synchronous Mealy machine and obtain its state diagram
Solution
The given synchronous Mealy machine consists of two D Flip-Flops, one inputs and
one output.
The Flip-Flop input functions are,
DA= Y1’Y2X’ DB= X+ Y1’Y2
The circuit output function is, Z= Y1Y2X
State Table
Present
state
DA= D B= Y1 Y2 Z=
Y1 Y2 X
Y1’Y2X’ X+ Y1’Y2 (t+1) (t+1) Y1Y2X
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 0 1 1
Next state Output

Present
state X=
X= 0 X= 1 X= 0
1
Y1 Y2 Y1 Y2 Y1 Y2 Z Z
0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 0
1 1 0 0 0 1 0 1
State Diagram
4. A sequential circuit has two JK Flop-Flops A and B, two inputs x and y and one
output z. The Flip-Flop input equation and circuit output equations are
JA = Bx + B' y' KA = B' xy'
JB = A' x KB = A+ xy'
z = Ax' y' + Bx' y‘
a) Draw the logic diagram of the circuit
b) Tabulate the state table.
c) Derive the state equation.

Solution
Logic Diagram
Solution
State Table
Present
state
JA= KA= JB= KB=
A B x y A(t+1) B(t+1) z
Bx+B’y’ B’xy’ A’x A+xy’
0 0 0 0 1 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 1 1 1 1 1 0
0 0 1 1 0 0 1 0 0 1 0
0 1 0 0 0 0 0 0 0 0 1
0 1 0 1 0 0 0 0 0 0 0
0 1 1 0 1 0 1 1 1 1 0
0 1 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 0 1 1 0 1
1 0 0 1 0 0 0 1 1 0 0
1 0 1 0 1 1 0 1 0 0 0
1 0 1 1 0 0 0 1 1 0 0
1 1 0 0 0 0 0 1 1 0 1
1 1 0 1 0 0 0 1 1 0 0
1 1 1 0 1 0 0 1 1 0 0
1 1 1 1 1 0 0 1 1 0 0
State Equations
5. A sequential circuit has two JK Flip-Flop A and B. the Flip-Flop input functions are:
JA= B JB= x’
KA= Bx’ KB= A  x.
a) Draw the logic diagram of the circuit,
Solution
Logic Diagram
Solution
State Table
Present
Input Flip-Flop Inputs Next state
state
K A= K B=
A B x JA= B JB= x’ A(t+1) B(t+1)
Bx’ Ax
0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 1 0
1 1 0 1 1 1 1 0 0
1 1 1 1 0 0 0 1 1

Next state
Present
X= 0 X= 1
state
A B A B A B
0 0 0 1 0 0
0 1 1 1 1 0
1 0 1 1 1 0
1 1 0 0 1 1
State Diagram
Analysis of Moore Model
1. Analyze the synchronous Moore circuit and obtain its state diagram.
Solution
Using the assigned variable Y1 and Y2 for the two JK Flip-Flops, we can write
the four excitation input equations and the Moore output equation as follows:
JA= Y2X KA= Y2’
JB= X KB= X’ and output function, Z= Y1Y2’
State Table
Present state Input Flip-Flop Inputs Next state Output
JA= Y2
Y1 Y2 X KA= Y2’ JB= X KB= X’ Y1 (t+1) Z= Y1Y2’
Y2X (t+1)
0 0 0 0 1 0 1 0 0 0
0 0 1 0 1 1 0 0 1 0
0 1 0 0 0 0 1 0 0 0
0 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 1 0 0 1
1 0 1 0 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0 0
1 1 1 1 0 1 0 1 1 0
Next state Output

Present
state X= 0 X= 1
Y1 Y2 Y1 Y2 Y1 Y2 Y
0 0 0 0 0 1 0
0 1 0 0 1 1 0
1 0 0 0 0 1 1
1 1 1 0 1 1 0
State Diagram
Here the output depends on the present state only and is independent of
the input. The two values inside each circle separated by a slash are for the
present state and output.
2. A sequential circuit has two T Flip-Flop A and B. The Flip-Flop input functions are:
TA= Bx TB= x
y= AB
Solution
Logic Diagram
State Table
Present
state
B
A B x TA= Bx TB= x A (t+1) y= AB
(t+1)
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 1 0
0 1 1 1 1 1 0 0
1 0 0 0 0 1 0 0
1 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1
1 1 1 1 1 0 0 1
Next state Output

Present
state x= 0 x= 1 x= 0 x= 1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 1 1 0 0 0
1 0 1 0 1 1 0 0
1 1 1 1 0 0 1 1
State Diagram
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7. STATE REDUCTION-ALGORITHM
Sometimes, certain properties of sequential circuits may be used to reduce the

number of gates and flip-flops during the design.
The problem of state reduction is to find ways of reducing the number
of states in a sequential circuit, while keeping the external input-output
relationships unchanged.
The reduction in the number of flip-flops in a sequential circuit is referred to as the

state-reduction problem. Reducing the number of flip flops will reduce the cost of a
circuit. That is, a reduction in the number of states may (or may not) result in a
reduction in the number of flip-flops.
State reduction is concerned with reducing the number of states in a state table,
while keeping the external input-output requirements unchanged .
The two states are said to be equivalent, if for each set of inputs, the circuits
produce exactly the same output and enable the circuit to move to the same state
or an equivalent state.
Algorithm for State Reduction:
Step 1: Consider the specifications given in the state diagram. If state table is
given in the problem, then move to step 3. Otherwise, do Step 2.
Step 2: Draw state table from the given state diagram
Step 3: Identify the equal states
Step 4: If two states are equal, replace one of the states with the other one and
remove one equal state from the table.
Step 5: Draw the reduced state table
Step 6: Draw the reduced state diagram

7. STATE REDUCTION - EXAMPLES
1. Minimize the state diagram shown below
Solution
Steps to reduce:
1. Draw state table
2. Identify the equal states
3. If two states are equal, replace one of the states with the other one and remove
one equal state from the table.
4. Draw the reduced state table
5. Draw the reduced state diagram
Step 1: Draw the state table
Present Next State Output

State
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
Step 2: Identify the equal states
 From the state table, we could identify that two present states e and g go to the same
next state a and f and have the same outputs of 0 and 1 for x = 0 and x = 1,
respectively. Therefore, states g and e are equivalent, and one of these states can be
removed.
Step 3: If two states are equal, replace one of the states with the other one and remove
one equal state from the table.
Now, states d and f are equal along with its outputs. So, state f can be replaced with d
and state f can be removed from the state table.
The reduced state table is shown below.
The reduced state diagram is shown below:

2. Reduce the number of states in the following state table and
a) Tabulate the reduced state table.
b) Starting from state a and input sequence 01110010011, determine the

output sequence for the given reduced state table.

State
x=0 x=1 x=0 x=1
a f b 0 0
b d c 0 0
c f e 0 0
d g a 1 0
e d c 0 0
f f b 1 1
g g h 0 1
h g a 1 0
Solution for (a)
Steps 1 and 2: The state table is given. From this, identify the equal states
Equal States are,
1. b Ξ e
2. d Ξ h

2. Reduce the number of states in the following state table and
a) Tabulate the reduced state table.
b) Starting from state a and input sequence 01110010011, determine the

output sequence for the given reduced state table.
Step 3: If two states are equal, replace one of the states with the other one and
remove one equal state from the table. Therefore, states e and h are removed
from the state table.
Now,
a Ξ c, So remove c
and replace c with a.

State
x=0 x=1 x=0 x=1
a f b 0 0
b d a 0 0
d g a 1 0
f f b 1 1
g g d 0 1

b)Starting from state a and input sequence 01110010011, determine the output
sequence for the given reduced state table.
Solution for (b)
Based on the input sequence, create a table with the state transition and display the
output sequence.
Input State Output

Sequence transition Sequence
from state a
0 af 0
1 f b 1
1 ba 0
1 ab 0
0 bd 0
0 dg 1
1 gd 1
0 dg 1
0 gg 0
1 gd 1
1 da 0
 Let us consider the previous reduced state table. When the first input x=0 from
the input sequence, there will be a transition from state a to state f and produces
output 0. When the next input x=1, there will be a transition from state f to state b
and produces output 1.
 Similarly , the output sequence 01000111010 is produced.

7. STATE ASSIGNMENT - EXAMPLES
In order to design a sequential circuit with physical components, it is necessary to

assign unique coded binary values to the states.
With three bits, it is possible to assign codes to eight states, 23 = 8, denoted by

binary numbers 000 through 111.
The three possible state assignments with five states are given below.
States Binary Gray Code One-Hot Code

Assignment Assignment Assignment
a 000 000 00001

b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000
The above state assignment is given for only 5 states, a,b,c,d, and e.
1. Reduce the following state diagram and draw the reduced one.
Solution
Let as assign the states as given below.
00 ----> a
01 ----> b
10 ----> c
11 ----> d
Now, Convert the given state diagram into state table
State table is,

State
x=0 x=1 x=0 x=1
a a b 0 0
b a d 1 0
c a c 1 0
d a c 1 0
Now,
 It is noted that,
• State c is equivalent to state d
• Therefore, state d can be removed from the state table
• Again state b is equivalent to state c. Therefore state c can be removed
• Therefore, the final reduced state table and the reduced state diagram are,
Presen Next State Output

t State
x=0 x=1 x=0 x=1
a a b 0 0
b a b 1 0
a) Reduced State
Table b) Reduced State
Diagram
8. DESIGN PROCEDURE
The steps needed for the design of synchronous sequential circuit is shown below
1. If word description and specifications of the desired operation is given in

the problem statement, then first draw the state diagram. If the state
diagram is given in the problem statement, then start from step 2.
2. Reduce the number of states.
3. Assign binary values to the states. Do steps 2 and 3 if necessary.
4. Obtain the binary-coded state table. Derive the state table with external
inputs (x) and Flip flop inputs.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram using the given flip flop.
9. EXAMPLES-DESIGN OF SYNCHRONOUS SEQUENTIAL
CIRCUIT
1. Design a synchronous sequential circuit using JK Flip Flop for the following state
diagram.
Solution
Each state contains two bits. It shows that there are two present states in the
sequential circuit.
These present states are denoted as A and B.
Step1 to 4 : The state table is given below with external inputs (x) and Flip flop
inputs
Present Next State

State
x=0 x=1
A B A(t+1) B(t+1) A(t+1) B(t+1)
0 0 0 0 0 1
0 1 1 0 0 1
1 0 1 0 1 1
1 1 1 1 0 0
CIRCUIT
Step 5: Choose the type of flip-flops to be used and Derive the state table with external
inputs (x) and Flip flop inputs
External
input and Next State Flip Flop Inputs
Present
State
x A B A(t+1) B(t+1) JA KA JB KB
0 0 0 0 0 0 x 0 x
0 0 1 1 0 1 x x 1
0 1 0 1 0 x 0 0 x
0 1 1 1 1 x 0 x 0
1 0 0 0 1 0 x 1 x
1 0 1 0 1 0 x x 0
1 1 0 1 1 x 0 1 x
1 1 1 0 0 x 1 x 1
Step 6: Derive the simplified flip-flop input equations and output equations.
K-map for JA K-map for KA
JA = x'B KA = xB
CIRCUIT
K-map for JB K-map for KB
JB = x
KB = x'A' + xA
(This is equivalent
to XNOR)
Step 7: Draw the logic diagram (Using JK Flip Flop)

CIRCUIT
2. Design a circuit that detects a sequence of three or more consecutive 1‘s in a
string of bits coming through an input line (Or) Design a sequence detector for
implementing three or more consecutive 1‘s in a string of bits coming through an
input line. Implement using D Flip flop.
Solution
Step 1: In the problem statement, word description and specifications of the desired
operation is given. So, we need to draw the state diagram first.
The state diagram is derived by starting with state S0.
If the input is 0, the circuit stays in S0, but if the input is 1, it goes to state S1 to
indicate that a 1 was detected.
If the next input is 1, the change is to state S2 to indicate the arrival of two
consecutive 1‘s, but if the input is 0, the state goes back to S0.
The third consecutive 1 sends the circuit to state S3.
If more 1‘s are detected, the circuit stays in S3. Any 0 input sends the circuit back
to S0. So, S0 is a reset state.
Therefore, the circuit remains in S3 as long as there are three or more consecutive
1‘s received.
This is a Moore model sequential circuit, since the output is 1 when the circuit is
in state S3 and is 0 otherwise.
Based on the above descriptions, the state diagram is drawn.

CIRCUIT
2. Design a circuit that detects a sequence of three or more consecutive 1‘s in a string of bits
coming through an input line (Or) Design a sequence detector for implementing three or
more consecutive 1‘s in a string of bits coming through an input line.
Step 2 to 4 : The state table of the sequence detector is given below with the external
inputs (x) and Flip flop inputs
External
input and Next State Output
Present
State
A B x A(t+1) B(t+1) y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
Step 5: Choose the Flip Flop
The characteristic equation of the D flip-flop is Q(t + 1) = DQ and the flip-flop input
equations in sum -of-minterm form is,
Step 6: Derive the simplified flip-flop input equations and output equations.
K-map for DA K-map for DB
DA = Ax + Bx DB = Ax + B’x
CIRCUIT
2. Design a circuit that detects a sequence of three or more consecutive 1‘s in a string of bits
coming through an input line (Or) Design a sequence detector for implementing three or
more consecutive 1‘s in a string of bits coming through an input line.
K-map for y
y = AB
Step 7: Draw the logic diagram (Using D Flip Flop)

10. REALIZATION OF ONE FLIP-FLOP USING OTHER
FLIP-FLOPS
It is possible to convert one Flip-Flop into another Flip-Flop with some

additional gates or simply doing some extra connection. The realization of one
Flip- Flop using other Flip-Flops is implemented by the use of characteristic tables
and excitation tables.
Follow these steps for converting one flip-flop to the other.
● Consider the characteristic table of desired flip-flop.
● Fill the excitation values inputs of given flip-flop for each combination of,
present state and next state. The excitation table for all flip-flops is shown
below.
Present Next SR flip-flop D flip-flop JK flip-flop T flip-
State State inputs input inputs flop
input
Q(t) Q(t+1) S R D J K T
0 0 0 x 0 0 x 0
0 1 1 0 1 1 x 1
1 0 0 1 0 x 1 1
1 1 x 0 1 x 0 0
● Get the simplified expressions for each excitation input. If necessary, use
Kmaps for simplifying.
● Draw the circuit diagram of desired flip-flop according to the simplified
expressions using given flip-flop and necessary logic gates.
Conversions among Flip-Flops are
• SR Flip-Flop to other Flip-Flop Conversions
• D Flip-Flop to other Flip-Flop Conversions
• JK Flip-Flop to other Flip-Flop Conversions
• T Flip-Flop to other Flip-Flop Conversions
FLIP-FLOPS
SR Flip-Flop to other Flip-Flop Conversions
Following are the three possible conversions of SR flip-flop to other flip-flops.
● SR flip-flop to D flip-flop
● SR flip-flop to JK flip-flop
● SR flip-flop to T flip-flop
SR flip-flop to D flip-flop conversion

• Write the characteristic table for required Flip-Flop (D Flip-Flop).
• Write the excitation table for given Flip-Flop (SR Flip-Flop).
• Determine the expression for the given Flip-Flop inputs (S and R) by using K-
map.
• Draw the Flip-Flop conversion logic diagram to obtain the required Flip- Flop
(D Flip-Flop).
The excitation table for the above conversion is
Given Flip-Flop
Required Flip-Flop (D)
(SR)
Present
Input Next state Flip-Flop Inputs
state
D Qn Qn+1 s R
0 0 0 0 x
0 1 0 0 1
1 0 1 1 0
1 1 1 x 0
FLIP-FLOPS
SR flip-flop to T flip-flop conversion
• Write the characteristic table for required Flip-Flop (T Flip-Flop).
• Write the excitation table for given Flip-Flop (SR Flip-Flop).
• Determine the expression for the given Flip-Flop inputs (S and R) by using K-
map.
• Draw the Flip-Flop conversion logic diagram to obtain the required Flip- Flop
(T Flip-Flop).
Given Flip-Flop
Required Flip-Flop (T)
(SR)
Present
state
T Qn Qn+1 S R
0 0 0 0 x
0 1 1 x 0
1 0 1 1 0
1 1 0 0 1
REALIZATION OF ONE FLIP-FLOP USING OTHER FLIP-FLOPS
D Flip-Flop to other Flip-Flop Conversions

Following are the three possible conversions of D flip-flop to other flip-flops.
● D flip-flop to T flip-flop
● D flip-flop to SR flip-flop
● D flip-flop to JK flip-flop
D flip-flop to T flip-flop conversion
Here, the given flip-flop is D flip-flop and the desired flip-flop is T flip-flop.
Therefore, consider the following characteristic table of T flip-flop along with the
excitation input of D flip-flop.
T flip-flop input Present State Next State D flip-flop input
T Qn Qn+1 D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
From the above table, Boolean function can directly writen as.
D=T⊕Q(t)
So, it require a two input Exclusive-OR gate along with D flip-flop. The circuit
diagram of T flip-flop is shown in the following figure.
FLIP-FLOPS
This circuit consists of D flip-flop and an Exclusive-OR gate. This Exclusive-OR gate
produces an output, which is Ex-OR of T and Q( t). So, the overall circuit has single
input, T and two outputs Q(t) & Q(t‘). Hence, it is a T flip-flop.
Exercise
Construct Realisation of
I. D flip-flop to SR flip-flop
II. D flip-flop to JK flip-flop
JK Flip-Flop to other Flip-Flop Conversions
Following are the three possible conversions of JK flip-flop to other flip-flops.
JK flip-flop to T flip-flop
JK flip-flop to D flip-flop
JK flip-flop to SR flip-flop
JK flip-flop to T flip-flop conversion
Here, the given flip-flop is JK flip-flop and the desired flip-flop is T flip-flop.
Therefore, consider the following characteristic table of T flip-flop.
The excitation table for the above conversion is Given Flip-Flop

(JK)
Present
state
T Qn Qn+1 J K
0 0 0 0 x
0 1 1 x 0
1 0 1 1 x
1 1 0 x 1
REALIZATION OF ONE FLIP-FLOP USING OTHER FLIP-FLOPS
JK Flip-Flop to D Flip-Flop
Given Flip-Flop
(JK)
Present
state
D Qn Qn+1 J K
0 0 0 0 x
0 1 0 x 1
1 0 1 1 x
1 1 1 x 0
Exercise
Construct
Realisation of JK
to SR FLIP-FLOP
FLIP-FLOPS
T Flip-Flop to other Flip-Flop Conversions
Following are the three possible conversions of T flip-flop to other flip-flops.
● T flip-flop to D flip-flop
● T flip-flop to SR flip-flop
● T flip-flop to JK flip-flop
T flip-flop to D flip-flop conversion
Here, the given flip-flop is T flip-flop and the desired flip-flop is D flip-flop.
Therefore, consider the characteristic table of D flip-flop and write down the
excitation values of T flip-flop for each combination of present state and next state
values. The following table shows the characteristic table of D flip-flop along with
the excitation input of T flip-flop.
Given Flip-
Required Flip-Flop (D) Flop
(T)
Present
state
D Qn Qn+1 T
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0
From the above table, the Boolean function of T can directly written as
T=D⊕Q(t)
So, it requires a two input Exclusive-OR gate along with T flip-flop. The circuit
diagram of D flip-flop is shown in the following figure.
FLIP-FLOPS
This circuit consists of T flip-flop and an Exclusive-OR gate. This Exclusive-OR

gate produces an output, which is Ex-OR of D and Q(n) . So, the overall circuit
has single input, D and two outputs Q(n) & Q(n+1). Hence, it is a D flip-flop.
Similarly, you can do other two conversions.
Exercise
Construct Realisation of
i T flip-flop to SR flip-flop
ii T flip-flop to JK flip-flop
ACTIVITY
ONLINE QUIZ
https://instrumentationtools.com/realisation-one-flip-flop-using-flip-flops-questions
12. SHIFT REGISTERS
Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To
increase the storage capacity in terms of number of bits, it is required to use a
group of flip-flop. Such a group of flip-flop is known as a Register. The n-bit register
will consist of n number of flip-flop and it is capable of storing an n-bit word.
The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers.
There are four mode of operations of a shift register.
● Serial Input Serial Output

● Serial Input Parallel Output
● Parallel Input Serial Output
● Parallel Input Parallel Output
Serial Input Serial Output
Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If

an entry of a four bit binary number 1 1 1 1 is made into the register, this number
should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e.
D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the
input of the next flip-flop i.e. D2 and so on.
Block Diagram
D3 D2 D1 Q1 D0
Q3 Q2 Q0
Flip-Flop-1
Flip-Flop-3 Flip-Flop-2 Flip-Flop-0
12. SHIFT REGISTERS
Serial Input Parallel Output

● In such types of operations, the data is entered serially and taken out in
parallel fashion.
● Data is loaded bit by bit. The outputs are disabled as long as the data is
loading.
● As soon as the data loading gets completed, all the flip-flops contain their
required data, the outputs are enabled so that all the loaded data is made
available over all the output lines at the same time.
● 4 clock cycles are required to load a four bit word. Hence the speed of
operation of SIPO mode is same as that of SISO mode.
Block Diagram
D3 D2 Q2 D1 Q1 D0 Q0
Q3
Flip-Flop-3
Parallel Input Serial Output (PISO)

● Data bits are entered in parallel fashion.
● The circuit shown below is a four bit parallel input serial output register.
● Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
● The binary input word B0, B1, B2, B3 is applied though the same
combinational circuit.
● There are two modes in which this circuit can work namely - shift mode or
load mode.
12. SHIFT REGISTERS
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they
will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of
clock, the binary input B0, B1, B2, B3 will get loaded into the corresponding flip-
flops. Thus parallel loading takes place.
Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive.
Hence the parallel loading of the data becomes impossible. But the AND gate 1,3
and 5 become active. Therefore the shifting of data from left to right bit by bit on
application of clock pulses. Thus the parallel in serial out operation takes place.
Block Diagram
D3 D2 Q2 D1 Q1 D0 Q0
Q3
Flip-Flop-3
12. SHIFT REGISTERS
Parallel Input Parallel Output (PIPO)
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0,
D1, D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is
applied, the input binary bits will be loaded into the flip-flops simultaneously. The
loaded bits will appear simultaneously to the output side. Only clock pulse is
essential to load all the bits.
Block Diagram
D3 D2 D1 Q1 D0
Q3 Q2 Q0
Flip-Flop-1
12. SHIFT REGISTERS
Operation of 4 bit Register
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the
number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling
edge of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 =
1000.
D3 D2 D1 Q1 D0
Q3 Q2 Q0
Flip-Flop-1
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the
clock hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.
D3 D2 Q2 D1 Q1 D0
Q3 Q0
Flip-Flop-2 Flip-Flop-1
Flip-Flop-3 Flip-Flop-0
Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the
third negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2
Q1 Q0 = 1110.
D3 D2 D1 Q1 D0
Q3 Q2 Q0
Flip-Flop-1
12. SHIFT REGISTERS
Truth Table
Waveforms
The simplest register is a 1-bit register. A 1-bit register is simply a single D flip-flop.
It holds a logical value of exactly one bit in length. Larger registers can hold longer
strings of bits. For example, an 8-bit register holds an 8-bit logical value (i.e.
10110110), and it is formed by a collection of eight D flip-flops. In order to form a
register form a collection of flip-flops, the flip-flops must all run on the same clock
signal.
In general, there are two major types of registers:
Parallel-Load Registers
Shift Registers.
12. SHIFT REGISTERS
Parallel-Load Registers
Parallel-load registers are a type of register where the individual bit values in the
register are loaded simultaneously. More specifically, every flip-flop within the
register takes an external data input, and these inputs are loaded into the flip-flops
on the same edge in a clock cycle.
D D D D
Q Q Q Q
FF3 FF3 FF3 FF3
It is a simple 4-bit parallel-load register where D0, D1, D2, and D3 are the individual
data bits; Q0, Q1, Q2, and Q3 form the output value (as a 4-bit word Q3Q2Q1Q0);
and Clk is the single clock signal.
Load Signal
Many commonly used parallel-load registers, however, also implement a load signal.
A load signal is used to synchronize the loading of a register's flip-flops in cases
where the individual data inputs are not provided simultaneously. When the load
signal is set, all the flip-flops in the register are loaded with the provided data inputs
during the next clock cycle. When the load signal is clear, all the flip-flops retain
their current value. This functionality is often implemented using multiplexers, or
muxes.
D D Q D D
Q Q Q
FF3
FF3 FF3 FF3
12. SHIFT REGISTER
Shift Register
As one flip-flop can store one-bit of information. In order to store multiple bits of
information, its is required to use multiple flip-flops. The group of flip-flops, which
are used to hold store the binary data is known as register.
If the register is capable of shifting bits either towards right hand side or towards
left hand side is known as shift register. An ‗N‘ bit shift register contains ‗N‘ flip-
flops. Following are the four types of shift registers based on applying inputs and
accessing of outputs.
● Serial In − Serial Out shift register

● Serial In − Parallel Out shift register
● Parallel In − Serial Out shift register
● Parallel In − Parallel Out shift register
Serial In − Serial Out shift register
The shift register, which allows serial input and produces serial output is known as
Serial In – Serial Out SISO shift register. The block diagram of 3-bit SISO shift
register is shown in the following figure.
D2 Q2 D1 Q1 D0 Q0
D D D
Flip-Flop Flip-Flop Flip-Flop
The block diagram consists of three D flip-flops, which are cascaded. That means,
output of one D flip-flop is connected as the input of next D flip-flop. All these flip-
flops are synchronous with each other since, the same clock signal is applied to each
one.
12. SHIFT REGISTER
In SISO shift register, bits can send serially from the input of left most D flip-flop.
Hence, this input is also called as serial input. For every positive edge triggering of
clock signal, the data shifts from one stage to the next. So, bits can receive serially
from the output of right most D flip-flop. Hence, this output is also called as serial
output.
Example
Let us see the working of 3-bit SISO shift register by sending the binary information
―011‖ from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to rightmost is
Q2Q1Q0=000. The working of 3-bit SISO shift register is illustrated in table below.
No of positive edge of Serial

Q2 Q1 Q0
Clock Input
0 - 0 0 0
1 1 1 0 0
2 1 1 1 0
3 0 1 1 1
4 - - 0 1
5 - - - 0
The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000.
Here, the serial output is coming from Q0. So, the LSB 1 is received at 3rd
positive edge of clock and the MSB 0 is received at 5th positive edge of clock.
Therefore, the 3-bit SISO shift register requires five clock pulses in order to
produce the valid output. Similarly, the N-bit SISO shift register requires 2N-1 clock
pulses in order to shift ‗N‘ bit information.
12. SHIFT REGISTER
Serial In − Parallel Out shift register
The shift register, which allows serial input and produces parallel output is known as
Serial In – Parallel Out SIPO shift register. The block diagram of 3-bit SIPO shift
D2 D1 Q1 D0
Q2 Q0
D
D Flip-Flop D
Flip-Flop Flip-Flop
This circuit consists of three D flip-flops, which are cascaded. In this shift register,
bits are send serially from the input of left most D flip-flop. Hence, this input is also
called as serial input. For every positive edge triggering of clock signal, the data
shifts from one stage to the next. In this case, the outputs of each D flip-flop in
parallel. So, it generates parallel outputs from this shift register.
Example
Let us see the working of 3-bit SIPO shift register by sending the binary information
―011‖ from LSB to MSB serially at the input.
No of positive Serial Note:

Q2 Q1 Q0 The 3-bit SIPO shift
edge of Clock Input
register requires three
0 - 0 0 0 clock pulses in order to
produce the valid output.
1 1 1 0 0
Similarly, the N-bit SIPO
2 1 1 1 0 shift register requires N
clock pulses in order to
3 0 0 1 1 shift ‗N‘ bit information.
12. SHIFT REGISTER
Parallel In − Serial Out Shift Register
The shift register, which allows parallel input and produces serial output is known as
Parallel In − Serial Out PISO shift register. The block diagram of 3-bit PISO shift
D2 Pr Q2 D1 Pr Q1 D0 Pr Q0
D D D
This circuit consists of three D flip-flops, which are cascaded. In this shift register,
inputs can apply parallel to each D flip-flop by making Preset Enable to 1. For every
positive edge triggering of clock signal, the data shifts from one stage to the next.
So, it generates serial output from the right most D flip-flop.
12. SHIFT REGISTER
Example Parallel In − Serial Out Shift Register
Let us see the working of 3-bit PISO shift register by applying the binary information
―011‖ in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of
the D flip-flops from leftmost to rightmost will be Q2Q1Q0=011. The working of 3-
bit PISO shift register is illustrated in table.
No of positive edge
Serial Input Q2 Q1 Q0
of Clock
0 - 0 1 1
1 1 - 0 1
2 1 - - 0
Here, the serial output is coming from Q0. So, the LSB 1 is received before
applying positive edge of clock and the MSB 0 is received at 2nd positive edge of
clock.
Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce
the valid output. Similarly, the N-bit PISO shift register requires N-1 clock pulses in
order to shift ‗N‘ bit information.
12. SHIFT REGISTER
Parallel In - Parallel Out Shift Register
The shift register, which allows parallel input and produces parallel output is known
as Parallel In − Parallel Out PIPO shift register. The block diagram of 3-bit PIPO shift
D2 Pr Q2 D1 Pr Q1 D0 Pr Q0
D D D
In this shift register, inputs are apply parallel to each D flip-flop by making Preset
Enable to 1. The parallel inputs are applied through preset or clear. These two are
asynchronous inputs. That means, the flip-flops produce the corresponding outputs,
based on the values of asynchronous inputs. In this case, the effect of outputs is
independent of clock transition. So, it generates parallel outputs from each D flip-
flop.
12. SHIFT REGISTER
Example : Parallel In - Parallel Out Shift Register
The working of 3-bit PIPO shift register by applying the binary information ―011‖ in
parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of
the D flip-flops from leftmost to rightmost will be
Q2Q1Q0=011. So, the binary information ―011‖ is obtained in parallel at the outputs
of D flip-flops before applying positive edge of clock.
Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to produce
the valid output. Similarly, the N-bit PIPO shift register doesn‘t require any clock
pulse in order to shift ‗N‘ bit information.
Applications of shift registers.
Based on the requirement the applications of shift registers are,
● Shift register is used as Parallel to serial converter, which converts the parallel
data into serial data. It is utilized at the transmitter section after Analog to
Digital Converter ADC block.
● Shift register is used as Serial to parallel converter, which converts the serial
data into parallel data. It is utilized at the receiver section before Digital to
Analog Converter DAC block.
● Shift register along with some additional gate s generate the sequence of
zeros and ones. Hence, it is used as sequence generator.
● Shift registers are also used as counters. There are two types of counters
based on the type of output from right most D flip-flop is connected to the
serial input. Those are Ring counter and Johnson Ring counter.
12. SHIFT REGISTER
Serial Transfer
In telecommunication and data transmission, serial communication is the process of

sending data one bit at a time, sequentially, over a communication channel or
computer bus. i.e Shifting the bits from source register to the destination register.
Shifting can be controlled by controlling the clock (clock gating)
12. SHIFT REGISTER
Bidirectional Shift Register

● To multiply and divide the given binary number, then we should be able to
move the data in either left or right direction. Such a register is called bi-
directional register. Bidirectional shift registers are the storage devices which
are capable of shifting the data either right or left depending on the mode
selected.
● There are two serial inputs namely the serial right shift data input DR, and
the serial left shift data input DL along with a mode select input (M).
D3 D2 Q2 D1 Q1 D0 Q0
Q3
FF-2 FF-3 FF-3
FF-3
Operation
With M = 1 ; Shift right operation
If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND
gates 2, 4, 6 and 8 will be disabled.The data at DR is shifted to right bit by bit from
FF-3 to FF-0 on the application of clock pulses. Thus with M = 1 enables the serial
right shift operation.
With M = 0 ; Shift left operation
When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are
enabled while 1, 3, 5 and 7 are disabled.
The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock
pulses. Thus with M = 0 enables the serial right shift operation.
12. SHIFT REGISTER
Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-
directional shift register. A shift register which can shift the data in both directions is
called a bi-directional shift register. Applying the same logic, a shift register which
can shift the data in both directions as well as load it parallely, is known as a
universal shift register. The shift register is capable of performing the following
operation −
● Parallel loading
● Left Shifting
● Right shifting
The mode control input is connected to logic 1 for parallel loading operation
whereas it is connected to 0 for serial shifting. With mode control pin connected to
ground, the universal shift register acts as a bi-directional register. For serial left
operation, the input is applied to the serial input which goes to AND gate-1 shown
in figure. Whereas for the shift right operation, the serial input is applied to D input.
Block Diagram
R R R R
CK FF-4 CK FF-3 CK FF-2 CK FF-1
S Q S Q S Q S Q
12. SHIFT REGISTER
Applications of shift Registers
● The shift registers are used for temporary data storage.
● The shift registers are also used for data transfer and data manipulation.
● The serial-in serial-out and parallel-in parallel-out shift registers are used to
produce time delay to digital circuits.
● The serial-in parallel-out shift register is used to convert serial data into
parallel data thus they are used in communication lines where demultiplexing
of a data line into several parallel line is required.
● A Parallel in Serial out shift register is used to convert parallel data to serial
data.
You can refer to the following video to get a clearer understanding of the working
principle of shift registers.
https://www.youtube.com/watch?v=6fVbJbNPrEU
Games of shift
https://www.yad.com/Type-Shift
13. SERIAL ADDER
Serial Binary Adder in Digital Logic
Serial binary adder is a combinational logic circuit that performs the addition of two
binary numbers in serial form. Serial binary adder performs bit by bit addition. Two
shift registers are used to store the binary numbers that are to be added.
A single full adder is used to add one pair of bits at a time along with the carry. The
carry output from the full adder is applied to a D flip-flop. After that output is used
as carry for next significant bits. The sum bit from the output of the full adder can
be transferred into a third shift register.
Block diagram of Serial Binary Adder:

13. SERIAL ADDER
Shift Register
Shift Register is a group of flip flops used to store multiple bits of data. There are
two shift registers used in the serial binary adder. In one shift register augend is
stored and in other shift register addend is stored.
Full Adder
Full adder is the combinational circuit which takes three inputs and gives two
outputs as sum and carry. The circuit adds one pair at a time with the help of it.
D Flip-flop
the carry output from the full adder is applied on the D flip-flop. Further, the output
of D flip-flop is used as a carry input for the next pair of significant bits.
Working Process
Following is the procedure of addition using serial binary adder:
● Step-1:The two shift registers A and B are used to store the numbers to be
added.
● Step-2:A single full adder is used to add one pair of bits at a time along with
the carry.
● Step-3:
The contents of the shift registers shift from left to right and their output
starting from a and b are fed into a single full adder along with the output of
the carry flip-flop upon application of each clock pulse.
● Step-4:The sum output of the full adder is fed to the most significant bit of
the sum register.
● Step-5:The content of sum register is also shifted to right when clock pulse
is applied.
● Step-6:
After applying four clock pulse the addition of two registers (A & B) contents
are stored in sum register.
13. SERIAL ADDER
Serial Binary Adder in Using JK Flip-Flop
Serial binary adder is a combinational logic circuit that performs the addition of two
binary numbers in serial form. Serial binary adder performs bit by bit addition. Two
shift registers are used to store the binary numbers that are to be added.
A single full adder is used to add one pair of bits at a time along with the carry. The
carry output from the full adder is applied to a JK flip-flop. After that output is used
as carry for next significant bits. The sum bit from the output of the full adder can
be transferred into a third shift register.
Block diagram of Serial Binary Adder:
SI SO
Shift Register
A
SI SO J
Shift Register
B
C
K
13. SERIAL ADDER
Shift Register
Shift Register is a group of flip flops used to store multiple bits of data. There are
two shift registers used in the serial binary adder. In one shift register augend is
stored and in other shift register addend is stored.
Full Adder
Full adder is the combinational circuit which takes three inputs and gives two
outputs as sum and carry. The circuit adds one pair at a time with the help of it.
JK Flip-flop
the carry output from the full adder is applied on the JK flip-flop. Further, the output
of JK flip-flop is used as a carry input for the next pair of significant bits.
Working Process
Following is the procedure of addition using serial binary adder:
● Step-1:The two shift registers A and B are used to store the numbers to be
added.
● Step-2:A single full adder is used to add one pair of bits at a time along with
the carry.
● Step-3:The contents of the shift registers shift from left to right and their
output starting from a and b are fed into a single full adder along with the
output of the carry flip-flop upon application of each clock pulse.
JQ=xy
KQ=x’y’
● Step-4:The sum output of the full adder is fed to the most significant bit of
the sum register.
S=x⊕ y ⊕Q
● Step-5:The content of sum register is also shifted to right when clock pulse
is applied.
● Step-6:After applying four clock pulse the addition of two registers (A & B)
contents are stored in sum register.
13. SERIAL ADDER
Q represents Cin (present state) and Cout (next state)
State table for serial adder using JK Flip-Flop
Given Flip-
Required Flip-Flop (T) Flop
(JK)
Present Next
Inputs Output Flip-Flop Inputs
state state
Q x y Qn+1 S J K
0 0 0 0 0 0 x
0 0 1 0 1 0 x
0 1 0 0 1 0 x
0 1 1 1 0 1 x
1 0 0 0 1 x 1
1 0 1 1 0 x 0
1 1 0 1 0 x 0
1 1 1 1 1 x 0
EXERCISE
Implement the following
i Serial Adder with RS Flip-Flops
ii Serial Adder with T Flip-Flops

14. UNIVERSAL SHIFTREGISTER
UNIVERSAL SHIFT REGISTER:
FUNCTION TABLE
A register capable of shifting in one direction only is a unidirectional shift

register. One that can shift in both directions is a bidirectional shift register. If
the register has both shifts and parallel‐load capabilities, it is referred to as a
universal shift register
The circuit consists of four D flip‐flops and four multiplexers. The four multiplexers
have two common selection inputs s1 and s0. Input 0 in each multiplexer is selected
when s1s0 = 00, input 1 is selected when s1s0 = 01, and similarly for the other two
inputs. The selection inputs control the mode of operation of the register according
to the function entries in Table. When s1s0 = 00, the present value of the register is
applied to the D inputs of the flip‐flops. This condition forms a path from the output
of each flip‐flop into the input of the same flip‐flop, so that the output re-circulates
to the input in this mode of operation. The next clock edge transfers into each
flip‐flop the binary value it held previously, and no change of state occurs.
When s1s0 = 01, terminal 1 of the multiplexer inputs has a path to the D inputs of
the flip‐flops. This causes a shift‐right operation, with the serial input transferred
into flip‐flop A3. When s1s0 = 10, a shift‐left operation results, with the other serial
input going into flip‐flop A0. Finally, when s1s0 = 11, the binary information on the
parallel input lines is transferred into the register simultaneously during the next
clock edge. Note that data enters MSB_in for a shift‐right operation and enters
LSB_in for a shift‐left operation. Clear_b is an active‐low signal that clears all of the
flip‐flops.
15 COUNTERS
COUNTERS
• A register that goes through a prescribed sequence of states upon the application
of input pulses is called a counter.
• A counter that follows the binary number sequence is called a binary counter.
• An n-bit binary counter consists of n flip-flops and can count in binary from 0
through 2n-1.
• Two categories of counters:
1. Asynchronous counters (or Ripple counters)
2. Synchronous counters
• In a ripple counter, a flip-flop outputs transition serves as a source for triggering
other flip flops. (i.e) the ‗c‘ input of some or all flip-flops are triggered, not by the
common clock pulses, but rather by the transition that occurs in other flip-flop
outputs.
• In a synchronous counter, the ‗c‘ inputs of all flip-flops receive the common clock.
RIPPLE BINARY COUNTER (BRC)

• A binary ripple counter consists of a series connection of complementing flip-
flops, with the output of each flip-flop connected to the ‗c‘ input of the next
higher order flip-flop.
• The flip-flop holding the least significant bit receives the incoming count pulses.
• The counter is constructed with the complementing flip-flops of the T type, D type
and JK type.
• Complementing flip-flops can be obtained from
JK Flip-flop – with the J & K inputs tied together = 1
T Flip-flop – T input = 1
D Flip-flop – D input is connected to complement output.
Using T Flip-Flop:
• The T inputs are connected to permanent logic 1.
• This complements the flip-flop, if the clock input goes through a negative
transition (i.e) 1 to 0.
• The negative transition occurs when the output of the previous flip-flop to which c
is connected goes from 1 to 0.
15 COUNTERS
15 COUNTERS
Count starts with binary 0, initially

Since T=1, A0 = 1 (complemented) , the transition of A0 is 0 to 1, so positive
transition, which does not affect the other higher order bits.
In the next clock pulse, since T = 1, A0 = 0, complemented again, the transition of
A0 from 1 to 0 is negative transition, so triggers the next flip-flop, whose output A1
is complemented.
A1‘s transition from 0 to 1 is not propagated. Likewise, the counter counts up to 15
and goes back to 0 to repeat the count.
Clock Pulse A3 A2 A1 A0
Initially 0 0 0 0
1st Clock pulse 0 0 0 1

T1 =1, A0 is complements.
A0 from 0 to 1 is +ve transition
does not affect other flip flops
2nd Clock pulse 0 0 1 0
A0 from 1 to 0 is –ve transition , so
affect A1 from 0 to 1 (+ve
transition) does not affect other flip
flops
3rd clock pulse 0 0 1 1
A0 from 0 to 1 (+ve transition) does
not affect other flip flops
4th clock pulse 0 1 0 0
A0 from 1 to 0 (-ve)
A1 from 1 to 0 (-ve)
A2 from 0 to 1 (+ve) does not affect
A3.
5th clock pulse 0 1 0 1
15 COUNTERS
Using JK Flip flop
• A binary counter with a reverse count is called binary countdown counter.

• In a downward counter, the binary count is decremented by 1 with every input
count pulse.
• Ex: 15, 14, 13, 12,…….. 0 and then back 15.
• All Flip-flops in a downward counter trigger on the positive edge of the clock.
• (i.e) LSB is complemented with every clock pulse, any other bit in the sequence is
complemented if its previous LSB goes from 0 to 1.
BCD RIPPLE COUNTER
• A decimal counter follows a sequence of ten states and returns to 0 after the
count of 9.
• A decimal digit is represented by a binary code of at least four bits.
• The state diagram of a decimal BCD counter is shown in below figure.
15 COUNTERS
Q8 Q4 Q2 Q1 Rule for Q1
0 0 0 0 Q1 complements for every clock pulse
0 0 0 1 Rule for Q2
Q2 complements when there is a negative transition
0 0 1 0 of 1 to 0 in Q1 and when Q8 = 0.
0 0 1 1 When Q8 = 1 => Q2 = 0
0 1 0 0 Rule for Q4
Q4 complements when there is a –ve transition from 1
0 1 0 1 to 0 in Q2.
0 1 1 0 Rule for Q8
0 1 1 1 Q8 = 0, as long as Q4 or Q2 = 0
When Q4=Q2=1, Q8 complements, when Q1 goes
1 0 0 0 from 1 to 0
1 0 0 1 Q8 is cleared in the next transition of Q1 from 1 to 0
(i.e) Q2 and Q4 = 0
0 0 0 0
15 COUNTERS
• A BCD counter is a decade counter since it counts from 0 to 9.

• To count in decimal from 0 to 99, need two decade counter. To count from 0 to
999, we need three decade counter.
• Multiple decade counters can be constructed by connecting BCD counters in
cascade, one for each decade.
• The inputs to the second and third decade come from Q8 of the previous decade.
• When Q8 in one decade goes from 1 to 0, it triggers the count for the next higher
order decade while its own decade goes from 9 to 0.
• The block diagram for three decade BCD counter is shown in the figure.
ASYNCHRONOUS MOD-N COUNTER
Design an Asynchronous mod-5 counter

Mod-5 counter counts from 0-1-2-3-4-0.
000 -> 0001 -> 0010 -> 0011 -> 0100
15 COUNTERS
SYNCHRONOUS COUNTER
• Clock pulses are applied to the inputs of all flip-flops.
• A common clock triggers all flip-flops simultaneously.
• The design whether a flip-flop is to be complemented is determined from the
values of the data inputs such as T or JK at the time of the clock edge.
If T=0 or J=K=0, the flip flop does not change.
T=1 or J=K=1, the flip flop complements.
I) Design a 4 BIT BINARY UP COUNTER
State Table:
Present State Next State Flip-Flop Inputs
A B C D A B C D JA KA JB KB JC KC JD KD
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X
1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1
Excitation table for JK Flip-Flop State Diagram
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
15 COUNTERS
CD 00 01 11 10 CD 00 01 11 10
AB AB
00 00 X X X X
01 1 01 X X X X
X X X X 1
11 11
X X X X
10 10
JA = BCD KA = BCD
CD 00 01 11 10 CD 00
AB 01 11 10
AB
00 1 00 X X X X
01 X X X X 01 1
11 X X X X 1
11
1 X X X X
10 10
JB = CD
KB = CD
15 COUNTERS
CD CD 00 01 11 10
00 01 11 10 AB
AB
00 1 X X 00 X X 1
01 1 X X 01 X X 1
1 X X X X 1
11 11
1 X X X X 1
10 10
JC = D KC = D
CD 00 01 11 10 CD 00
AB 01 11 10
AB
00 00
01 1 01 1
11 X X X X X X X X
11
X X X X X X X X
10 10
J= BCD JA = BCD
15 COUNTERS
CD CD 00 01 11 10
00 01 11 10 AB
AB
00 1 X X 00 X X 1
01 1 X X 01 X X 1
1 X X X X 1
11 11
1 X X X X 1
10 10
JC = D KC = D
CD 00 01 11 10 CD 00
AB 01 11 10
AB
00 1 X X 1 00
1 X X 1
01 1 X X 1 01 1 X X 1
11 1 X X 1 11 1 X X 1
1 X X 1 1 X X 1
10 10
JD= 1 KD = 1
15 COUNTERS
For example, if the present state of a four‐bit counter is ABCD = 0011, the next
count is 0100. D is always complemented. C is complemented because the present
state of D = 1. B is complemented because the present state of CD = 11. However,
A is not complemented, because the present state of BCD = 011, which does not
give an all‐1‘s condition
16 SYNCHRONOUS COUNTERS
II) Design a Synchronous 3 bit Binary Down Counter
State Diagram
State Table
Present State Next State Flip-Flop Inputs

A B C A B C JA KA JB KB JC KC TA TB TC
1 1 1 1 1 0 X 0 X 0 X 1 0 0 1
1 1 0 1 0 1 X 0 X 1 1 X 0 1 1
1 0 1 1 0 0 X 0 0 X X 1 0 0 1
1 0 0 0 1 1 X 1 1 X 1 X 1 1 1
0 1 1 0 1 0 0 X X 0 X 1 0 0 1
0 1 0 0 0 1 0 X X 1 1 X 0 1 1
0 0 1 0 0 0 0 X 0 X X 1 0 0 1
0 0 0 1 1 1 1 X 1 X 1 X 1 1 1
Excitation Table for JK Flip-flop Excitation Table for T Flip-flop
Q(t) Q(t+1) T
Q(t) Q(t+1) J K
0 0 0
0 0 0 X
0 1 1
0 1 1 X
1 0 1
1 0 X 1
1 1 0
1 1 X 0
BC BC
00 01 11 10 00 01 11 10
A A
0 1 0 X X X X
1 X X X X 1 1
JA = B’C' BC KA = B’C
BC
00 01 11 10 00 01 11 10
A A
0 1 X X 0 X X 1
1 1 X X 1 X X 1
JB = C’ KB = C’
BC BC
00 01 11 10 00 01 11 10
A A
0 X 1 1 X 0 1 X X 1
1 X 1 1 X 1 1 X X 1
JC = 1 KC = 1
3 bit Binary Down Counter
III) DESIGN A BINARY UP-DOWN COUNTER

• The two operation (up & down) can be combined together in one circuit to
form a counter capable of counting wither up or down.
• When the up input is ‗1‘, the circuit counts up. When the down input is ‗1‘ ,
the circuit counts down.
UP DOWN Operation
0 0 No Change
0 1 Counts down
1 0 Counts up
1 1 Counts up
The up input has priority over the down input

JA = BCD+B‘C‘D‘ JB = CD+C‘D‘ JC = D+D‘ JD = 1
KA = BCD+B‘C‘D‘ KB = CD+C‘D‘ KC = D+D‘ KD = 1
TA = BCD+B‘C‘D‘ TB = CD+C‘D‘ TC = D+D‘ TD = 1
IV) DESIGN A SYNCHRONOUS BCD COUNTER
• A BCD counter counts in binary coded decimal from 0000 to 1001 and back to
0000.
• Because of the return to 0 after a count of 9, a BCD counter does not have a
regular pattern with a straight binary counts.
• State Table
TQ1 = 1
TQ2 = Q8Q1
TQ4 = Q2Q1
TQ8 = Q8Q1 + Q4Q2Q1
y = Q8Q
V) DESIGN A BINARY COUNTER WITH PARALLEL LOAD
Parallel Load capability for transferring an initial binary number into the counter
prior to the count operation.
The input load control disables the count operation and causes a transfer of
data from the four data inputs into the four flip‐flops.
Function Table
Block Diagram of Four Bit Register
Logic Diagram of Four Bit Register

CROSS WORD PUZZLE
Cross word Puzzle
17. NON BINARY COUNTERS
A non binary counter is a circuit that consists of flip-flops which along with
combinational elements are used for generation of control signals.
The counter with ‗n‘ Flip-Flops has a maximum MOD number 2n.
We can find the number of Flip-Flops (n) required for the desired MOD number
(N) using the equation, 2n ≥ N
For example, a 3 bit binary counter is a MOD 8 counter. The basic counter can be
modified to produce MOD numbers less than 2n by allowing the counter to skin
those are normally part of counting sequence.
n= 3
N= 8
2n = 23= 8= N
Example : To construct a MOD 10 Counter: 2n= N= 10 i.e 23= 8 less than N.
24= 16 > N(10).
So we need 4 Flip Flips to construct a MOD 10 counter
Steps to construct any MOD-N counter
1. Find the number of Flip-Flops (n) required for the desired MOD number (N)
using the equation, 2n ≥ N.
2. Connect all the Flip-Flops as a required counter.
3. . Find the binary number for N.
4. Connect all Flip-Flop outputs for which Q= 1 when the count is N, as inputs
to NAND gate.
5. Connect the NAND gate output to the CLR input of each Flip-Flop.
When the counter reaches Nth state, the output of the NAND gate goes LOW,
resetting all Flip-Flops to 0. Therefore the counter counts from 0 through N-1.
1. Design a MOD 10 counter using JK Flip Flips
MOD-10 counter reaches state 10 (1010). i.e., Q3Q2Q1Q0= 1 0 1 0. The

outputs Q3 and Q1 are connected to the NAND gate and the output of the NAND
gate goes LOW and resetting all Flip-Flops to zero. Therefore MOD-10 counter
counts from 0000 to 1001. And then recycles to the zero value.
The MOD-10 counter circuit is shown below.
2. Design a 3-Bit Asynchronous Binary Counter(or)binary ripple counter
The basic operation is the same as that of the 2-bit counter except that the
3-bit counter has eight states, due to its three Flip-Flops. A timing diagram is
shown below for eight clock pulses. Notice that the counter progresses through a
binary count of zero through seven and then recycles to the zero state. This
counter can be easily expanded for higher count, by connecting additional toggle
Flip-Flops.
Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
Output y is 1 for octal digits 2, 3, 6, or 7,
Output x is 1 for digits 4, 5, 6, or 7

3-Bit Asynchronous Binary Counter
Timing diagram
18. RING COUNTER
SHIFT REGISTER COUNTERS:
A shift register counter is basically a shift register with the serial output
connected back to the serial input to produce special sequences. Two of the most
common types of shift register counters are:
Ring counter
Johnson counter (Shift Counter)
The ring counter utilizes one Flip-Flop for each state in its sequence. It
has the advantage that decoding gates are not required. In the case of a l0-bit
ring counter, there is a unique output for each decimal digit.
Ring Counter
The output Q0 sets D1 input, Q1 sets D2, Q2 sets D3 and Q3 is fed back to D0.
Because of these conditions, bits are shifted left one position per positive clock
edge and fed back to the input. All the Flip-Flops are clocked together. When CLR
goes low then back to high, the output is 0000.
Timing sequence of a Ring Counter

The first positive clock edge shifts MSB to LSB position and other
bits to one position left so that the output becomes Q= 0010. This
process continues on second and third clock edge so that
successive outputs are 0100 and 1000. The fourth positive clock
edge starts the cycle all over again and the output is 0001. Thus the
stored 1 bit follows a circular path (i.e., the stored 1 bits move left
through all Flip-Flops and the final Flip-Flop sends it back to the
first Flip-Flop). This action has given the name of ring counter.
19. JOHNSON COUNTER
Johnson Counter / Shift Counter
In a Johnson counter the complement of the output of the last Flip-Flop is

connected back to the D input of the first Flip-Flop. This feedback arrangement produces a
characteristic sequence of states as shown in table below. The 4-bit sequence has a total of
eight states, and that the 5-bit sequence has a total of ten states. In general, a Johnson
counter will produce a modulus of 2n, where ‗n‘ is the number of stages in the counter.
4-bit Johnson counter

The Q output of each stage is connected to the D input of the next
stage (assuming that D Flip-Flops are used). The complement output of the
last stage is connected back to the D input of the first stage.
Timing sequence for 4-bit Johnson counter

Video Links
UNIT III
Video Links
Sl. Topic Video Link
No.
Introduction to Sequential https://www.youtube.com/watch?v=ib
1
Circuits QBb5yEDlQ
https://www.youtube.com/watch?v=2ecMG
2 S-R,J-K and D Flip Flops
_OciLo
https://www.youtube.com/watch?v=4CRPla
3 J-K and T Flip Flops
BnfV0
DESIGN OF SYNCHRONOUS https://www.youtube.com/watch?v=MiuMY
4 En3dpg
SEQUENTIAL CIRCUITS
https://www.youtube.com/watch?v=t1
5 DESIGN USING J-K FLIP FLOP
_rhFnKAeo
https://www.youtube.com/watch?v=aG
6 Application of Shift Registers
HpADG8Yo4
Assignments
UNIT III
Assignment Questions
1) A sequential circuit with two D Flip-flops A and B, one input
x , and one output z is specified by the following next state
and output equations: A(t+1) = A'+B; B(t+1)=B'x ;
z =A+B'
(i)Draw the logic diagram of the circuit.
(ii)Derive the state table.
(iii)Draw the state diagram of the circuit.
1) Design a 4 bit synchronous BCD counter using T flip flop

that counts in the following way : 0000,0001,……,1001 and
back to 0000.
2) Design a mod 5 asynchronous counter using JK flip flop.
Draw the waveforms.
Part A – Q & A
Unit - III
Part A Q & A (with K level and CO)
1) Define Sequential Logic Circuit. Give an example (CO3, k1)
•A sequential circuit consists of a combinational circuit to which storage elements are

connected to form a feedback path.
•The output of a sequential circuit is a function of both the inputs and the present state
of the storage elements.
•Examples: Flip flops, counters, registers
Block diagram of a Sequential Circuit
2) What are the classification of Sequential Logic Circuit? (CO3, k1)
The two types of Sequential Logic Circuit are:
1. Synchronous Sequential Circuit
2. Asynchronous Sequential Circuit
3) Define a Synchronous Sequential Logic Circuit (CO3, k1)
•A synchronous sequential circuit is a system whose behaviour can be defined from the
knowledge of its signals at discrete instants of time.
•Synchronization is achieved by a timing device called a clock generator, which provides

a clock signal having the form of a periodic train of clock pulses.
Block diagram of Synchronous Sequential Circuit

4) State the differences between Synchronous and Asynchronous

Sequential Circuit. (CO3, k1)
5) What is a Master Slave Flip flop? (CO3, k1)
• A master-slave flip-flop consists of two flip-flops where one circuit serves as a

master and the other as a slave.
6) State the differences between Latches and Flip flops. (CO3, K1)
Part-A Questions and Answers (JK FF,TF F and Analysis)
7. State the operation of JK flip flop [CO3,K2]
When J input is high and K input is low, the Q output of the flip flop is set
When J input is low and K input is high, the Q output of the flip flop is reset
When both the inputs K and J are low, the output does not change
When both the inputs K and J are high, the flip flop toggles between set and reset
states for every clock pulse
8. Mention the characteristic equation of JK flip flop [CO3,K2]
Characteristic equation of JK flip flop is Qn+1 = JQn‘ + K‘ Qn
9. Define race around condition in JK flip flop [CO3,K2]
In JK flip flop, if both the inputs K and J are high, the flip flop toggles continuously
between set and reset states for every clock pulse. This condition is called as race
around condition
10. Give the characteristic table of JK flip flop [CO3,K2]
11. Give the excitation table of JK flip flop [CO3,K2]

12. What is master-slave flip flop [CO3,K2]
A master slave flip flop consist of two flip flops, where one flip flop serves as a
master and another as a salve. The race around problem is solved using the master
slave flip flop.
13. State the operation of T flip flop [CO3,K2]
T flip flop is also known as toggle flip flop. When T=0, there is no change in the
output. When T=1, the flip flop toggles between set and reset states for every clock
pulse.
14. Mention the characteristic equation of T flip flop [CO3,K2]
Characteristic equation of T flip flop is Qn+1= TQn’+ T’Qn
9. Give the characteristic table of T flip flop [CO3,K2]
15. Mention the two types of models used to represent clocked sequential
circuits. [CO3,K2]
a) Moore Model
b) Mealy Model
16. Draw the symbol of JK flip flop [CO3,K2]
17. Draw the symbol of T flip flop [CO3,K2]
18. Define Moore model synchronous sequential circuit [CO3,K2]
When the output of the sequential circuit depends only on the present state of the
flip flops then it is referred as Moore circuit. Moore circuit requires more number of
states.
19. Define Mealy model synchronous sequential circuit [CO3,K2]
When the output of the sequential circuit depends both on the present state of the
flip flops and on the inputs then it is referred as Mealy circuit. It requires lesser
number of states.
20. What is present state? [CO3,K2]
The information stored in the memory elements at any given time defines the
present state of the sequential circuit.
21. What is next state? [CO3,K2]
The present state and the external inputs determines the output and next state of
the sequential circuit.
22. Define state equation [CO3,K2]
A state equation also called as application equation is an algebraic expression that

specifies the next state as a function of present state and inputs.
23. Define state table [CO3,K2]
A state table represents the relationship between input, output and flip flop states.
It consists of four sections labelled as present state, input, next state and output.
24. Define state diagram [CO3,K2]
State diagram is the graphical representation of a state table. In this diagram, a

circle represents a state and the transitions between the states are indicated by
directed lines connecting the circles. The directed lines are labelled by two binary
numbers separated by a slash. The first number is the input value and the number
after the slash is output.
25. Mention the applications of flip flops [CO3,K2]
a) Used as memory elements
b) Used as delay elements
c) Used as a basic building blocks in sequential circuits such as counters and

registers
d) Data transfer
e) Frequency division and counting

26. What is state reduction ? (CO3, k1)
The process of eliminating the equivalent or redundant states from a state table
or state diagram of sequential circuit is known as state reduction.
27. Why is state reduction necessary? (CO3, k1)
Reduction to the minimum number of states reduces the number of flip flops and logic
gates needed to design the sequential circuit. This highly reduces the cost required to
design the circuit.
28. Why is state assignment necessary? (CO3, k1)
In order to design a sequential circuit with physical components, it is necessary to

assign unique coded binary values to the states.
29. Discuss the design procedure of sequential circuits. (CO3, k2)
The steps needed for the design of synchronous sequential circuit is shown below
1. If word description and specifications of the desired operation is given in the
problem statement, then first draw the state diagram. If the state diagram is
given in the problem statement, then start from step 2.
2. Reduce the number of states.
3. Assign binary values to the states. Do steps 2 and 3 if necessary.
4. Obtain the binary-coded state table. Derive the state table with external inputs
(x) and Flip flop inputs.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram using the given flip flop.
30. Define registers. [CO3,K1]
A register is a group of flip-flops flip-flop can store one bit information.

So an n-bit register has a group of n flip-flops and is capable of storing any
binary information/number containing n-bits.
31. Define shift registers. [CO3,K1]
The binary information in a register can be moved from stage to stage

within the register or into or out of the register upon application of clock
pulses. This type of bit movement or shifting is essential for certain arithmetic
and logic operations used in microprocessors. This gives rise to group of
registers called shift registers.
32. What are the different types of shift type? [CO3,K1]
There are five types. They are, Serial In Serial Out Shift Register Serial In
Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel
Out Shift Register & Bidirectional Shift Register
33. Explain the flip-flop excitation tables for RS FF. [CO3,K2]
RS flip-flop In RS flip-flop there are four possible transitions from the

present state to the next state.They are ,
0→ 0 transition: This can happen either when R=S=0 or when R=1 and S=0.
0 →1 transition: This can happen only when S=1 and R=0.
1 →0 transition: This can happen only when S=0 and R=1.
1 →1 transition: This can happen either when S=1 and R=0 or S=0 and R=0.
34. Define sequential circuit? [CO3,K1]
In sequential circuits the output variables dependent not only on the

present input variables but they also depend up on the past history of these
input variables.
35. What do you mean by present state? [CO3,K1]
The information stored in the memory elements at any given time

defines the present state of the sequential circuit.
36. What do you mean by next state? [CO3,K1]
The present state and the external inputs determine the outputs and
the next state of the sequential circuit.
37. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 =

1, Q2 = 1, and Q3 = 1. What is the sequence on the the sixth clock
pulse?[CO3,K3]
Johnson counter.
Reset -- 0000
1 -- 1000, 2 -- 1100, 3 -- 1110, 4 -- 1111, 5 -- 0111, 6 -- 0011
38. In the given figure shows a 4 bit serial in parallel out right shift
register. The initial contents as shown are 0110. After 3 clock pulses
the contents will be?[CO3,K3]
Here ex-or gate is connected out to input of the register.

In intial state 0110,
1st Clock pulse : i/p of ex-or is 10. So, output is 1 is given to register. Now the
register is 1011.
2nd Clock pulse : i/p of exor is 11. So, the output is 0 is given to register. Now the
register is 0101.
Finally 3rd clk pulse : i/p of exor is 01. So, the output is 1 is given to register. Now
register is 1010.
Hence after 3 clock pulses upline the content of shift register will be 1010.
39. What is counter? (CO3, K1)

A counter is used to count pulse and give the output in binary form.
40. What is synchronous counter? (CO3, K1)

In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops.
The output of the flip-flops change state at the same instant. The speed of
operation is high compared to an asynchronous counter
41. What is Asynchronous counter? (CO3, K1)

In a Asynchronous counter, the clock pulse is applied to the first flip-flops. The
change of state in the output of this flip-flop serves as a clock pulse to the next flip-
flop and so on. Here all the flip-flops do not change state at the same instant and
hence speed is less.
42. What is the difference between synchronous and asynchronous
counter? (CO3, K1)
Asynchronous counters Synchronous counters

Clock pulse is applied to the In this type there is no
first flip-flop, the change of connection between output of
output is given as clock to next first flip-flop and clock input of
flip-flop the next flip - flop
All the flip-flops are Not All the flip-flops are clocked
clocked simultaneously simultaneously
Speed of operation is low. Speed of operation is high
43. Name the different types of counter. (CO3, K1)

a) Synchronous counter
b) Asynchronous counter
i) Up counter
ii) Down counter
iii) Modulo – N counter
iv) Up/Down counter
44. What is a ripple counter? (CO3, K1)

A ripple counter is nothing but an asynchronous counter, in which the output of the
flip-flop changes state like a ripple in water.
45. What are the uses of a counter? (CO3, K1)

i) The digital clock
ii) Auto parking control
iii) Parallel to serial data conversion.
46 What is a modulo counter? (CO3, K1)

A counter that counts from 0 to T is called as modulo counter.
Part B – Questions
Part B Questions
Q. Questions K CO
No. Level Mapping
1 Explain the working of SR Latch with NOR gates with K2 CO3
a neat diagram.
2 Explain the working of SR Latch with NAND gates K2 CO3
with a neat diagram.
3 Explain in detail the working of a D Latch. K2 CO3
4 With a neat diagram explain the functionality of a K2 CO3

Edge triggered Master Slave D Flip Flop.
5 Explain the operation of JK flip flop with its logic K2 CO3
diagram, characteristic table and equation.
6 Explain the operation of T flip flop with its logic K2 CO3
diagram, characteristic table and equation.
7 How the race condition can be avoided in a flip flop K2 CO3
8 Explain the working of Master-Slave JK flip flop with K2 CO3

neat diagram.
9 A sequential circuit has two JK Flip-Flops A and K4 CO3
B, one input (x) and one output (y). the Flip-
Flop input functions are,
JA= B+ x JB= A’+ x’
K A= 1 K B= 1
and the circuit output function, Y= xA’B.
a) Draw the logic diagram of the Mealy circuit,
10 A sequential circuit with two ‗D‘ Flip-Flops K4 CO3
A and B, one input (x) and one output
(y). the Flip-Flop input functions are:
DA= Ax+ Bx
DB= A’x and the circuit output
function is,
Y= (A+ B) x’.
(a) Draw the logic diagram of the circuit,
(b) Tabulate the state table,
(c) Draw the state diagram.

Part B Questions
Q. Questions K CO
No. Level Mapping
11 Analyze the synchronous Mealy machine and obtain K4 CO3
its state diagram
12 A sequential circuit has two JK Flop-Flops A and B, K4 CO3
two inputs x and y and one output z. The Flip-Flop

input equation and circuit output equations are
JA = Bx + B' y' KA = B' xy'
JB = A' x KB = A+ xy'
z = Ax' y' + Bx' y‘
a) Draw the logic diagram of the circuit
b) Tabulate the state table.
c) Derive the state equation.
13 A sequential circuit has two JK Flip-Flop A and B. the K4 CO3
Flip-Flop input functions are:

JA= B JB= x’
KA= Bx’ KB= A  x.
Part B Questions
Q. Questions K CO
No. Level Mapping
14 Analyze the synchronous Moore circuit and obtain its K4 CO3
state diagram
15 A sequential circuit has two T Flip-Flop A and B. The K4 CO3

Flip-Flop input functions are:
TA= Bx TB= x
y= AB
16 Implement state reduction and state K5 CO3
assignment for the following state diagram.

Part B Questions
Q. Questions K CO
No. Level Mapping
17 For the circuit described by the given state K4 CO3
diagram
a) Determine the state transitions and output

sequence that will be generated when an
input sequence of 010110111011110 is
applied to the circuit and it is initially in
the state 00.
(b) Find all of the equivalent states and draw a
simpler, but equivalent, state diagram.
(c) Using D flip-flops, design the equivalent
machine (including its logic diagram)
described by the state diagram in (b).
18 Design a sequential circuit with two JK flip- K4 CO3

flops A and B and two inputs E and F . If E = 0,
the circuit remains in the same state
regardless of the value of F . When E = 1 and F
= 1, the circuit goes through the state
transitions from 00 to 01, to 10, to 11, back to
00, and repeats. When E = 1 and F = 0, the
circuit goes through the state transitions from
00 to 11, to 10, to 01, back to 00, and repeats.
(CO3,K5)
Part B Questions
Q. Questions K CO
No. Level Mapping
19 A sequential circuit has three flip-flops A, B, C ; K5 CO3
one input x_in ; and one output y_out .

The state diagram is shown below. The
circuit is to be designed by treating the
unused states as don’t-care conditions.
Analyze the circuit obtained from the
design to determine the effect of the
unused states.
(a) Use D flip-flops in the design.
(b) Use JK flip-flops in the design.
20 Design the sequential circuit specified by the K5 CO3
state diagram in the above problem, using

T flip-flops.
21 Implement T flip flop using D flip flop. K2 CO3
22 Implement SR flip flop using T flip flop. K2 CO3
23 Implement JK flip flop using SK flip flop. K2 CO3

Part B Questions
Q. Questions K CO
No. Level Mapping
24 Design a shift register using JK flip-flops. K2 CO3
25 a. Explain Serial in Serial out Shift Register. K2 CO3

b. Explain Serial in parallel out Shift Register.
26 a. Explain parallel in parallel out Shift Register. K2 CO3
b. Explain parallel in Serial out Shift Register.
27 Explain parallel load register in detail. K2 CO3
28 A sequential circuit with two D flip-flops A and B, K3 CO3

one input x and one output z is specified by
the following next-state and output equations:
A(t+1)= A′+B, B(t+1)=B′x, z=A+B′
(1) Draw the logic diagram of the circuit
(2) Draw the state table
(3) Draw the state diagram of the circuit
29 Draw the necessary connecting wires between flip- K3 CO3
flops so that serial data is shifted from right to
left instead of left to right as you may be
accustomed to seeing in a shift register
schematic:
Part B Questions
Q. Questions K CO
No. Level Mapping
30 Using D Flip-flops, design a synchronous counter K6 CO3
which counts in the sequence 000, 001, 010,
011, 100, 101, 111, 000. Design a 3-bit binary
counter.
31 Design a 3-bit binary up-down counter. K6 CO3
32 Design a 4-bit binary synchronous counter with D K6 CO3

flip-flops.
33 Design a synchronous counter with the following K6 CO3
sequence: 0,1,3,7,6,4 and repeats. Use JK flip-
flops.
34 Design a synchronous sequential circuit using JK K6 CO3
flip flop to generate the sequence and repeat.
0, 1, 2, 4, 5, 6.
35 Design a synchronous sequential counter that goes K6 CO3
through the sequence 2, 6, 1, 7, 5, 4 and
repeat. Use JK flip flop.
36 Design a synchronous counter using JK flip-flops to K6 CO3
count the following sequence:

―1-3-15-5-8-2-0-12-6-9‖
37 Design a MOD 16 up counter using JK Flip flops. K6 CO3
38 Design and implement a Mod-5 synchronous counter K6 CO3

using JK flip-flops.
39 Draw a 4-bit and 3-bit ripple counter with D Flip- K1 CO3
flops.
40 Design a mod 5 asynchronous counter. K6 CO3
41 How do ripple counters differ from synchronous K2 CO3

counters? Explain.
Supportive online
Certification courses
(NPTEL, Swayam,
Coursera, Udemy, etc.,)
Supportive Online Certification Courses
Swayam:
• Digital Circuits By Prof. Santanu Chattopadhyay | IIT Kharagpur
• https://swayam.gov.in/nd1_noc19_ee51/preview
Coursera:
• Digital Systems: From Logic Gates to Processors offered by Universitat
Autònoma de Barcelona
• https://www.coursera.org/learn/digital-systems
Classcentral.com:
• Online Course - Digital Electronic Circuits by Indian Institute of
Technology, Kharagpur and NPTEL via Swayam
• https://www.classcentral.com/course/swayam-digital-electronic-circuits-
12953
Udemy:
• Master The Digital Electronics- Minimisation And Basic Gates –
[Learn about the digital gates, boolean algebra, k-map| Update your digital
from base to pro]
• https://www.udemy.com/course/professional-digital-electronics/
Real time Applications in
day to day life and to
Industry
Real time Applications
Some of the most common applications of flip – flops are
Counters
Registers
Frequency Divider circuits
Data transfer
COUNTERS
SHIFT REGISTERS
FREQUENCY DIVIDER
DATA TRANSFER
Content Beyond Syllabus
Applications of Ring Counter
Applications of Ring counters
Ring counters are used to count the data in a continuous loop.
They are also used to detect the various numbers values or various patterns
within a set of information, by connecting AND & OR logic gates to the ring
counter circuits.
2 stage, 3 stage and 4 stage ring counters are used in frequency divider circuits
as divide by 2 and divide by 3 and divide by 4 circuits, respectively.
The 3 stage Johnson counter is used as a 3 phase square wave generator which
produces 1200 phase shift.
The 5 stage Johnson counter circuit is generally used as synchronous decade

(BCD) counter and also as divider circuit.
The 2 stage Johnson counters are also known as ―Quadrature oscillator‖ which is
used to produce 4 level individual outputs which are out of phase with 900 with
each other. This quadrature generator is used to produce 4 phase timing signal.
Assessment Schedule
(Proposed Date & Actual
Date)
Assessment Schedule (Proposed Date &
Actual Date)
Prescribed Text Books &
Reference
Prescribed Text Books & Reference
TEXT BOOK:
M. Morris R. Mano, Michael D. Ciletti, “Digital Design: With an Introduction to the Verilog
HDL, VHDL, and System Verilog” , 6th Edition, Pearson Education, 2017.
REFERENCES:
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson Education,
2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition, CENGAGE
Learning, 2013
4. Donald D. Givone, Digital Principles and Design‖, Tata Mc Graw Hill, 2003.
Mini Project Suggestions
Mini Project Suggestions
1) Car Alarm :
A fairly simple circuit can be designed that could operate a car alarm. The circuit has
one input Y which would be connected to the car's door switch to determine if the car
door is open or shut. When the door is shut Y = 0, and when the door is open Y = 1.
The circuit has one output Z which is used to operate a relay that honks the horn by
shorting the wires that go to the horn switch in the steering wheel. When Z = 1, the
relay is activated and the horn honks. The circuit would be asynchronously reset by
the accessories power line that is high when the ignition is turned on or is in
accessory-only mode, both of which require the key to the car.
2) 12-Hour Clock
Digital clocks are usually set up to start at 12:00, and they count 12:01, 12:02, 12:03,
12:04, 12:05, 12:06, 12:07, 12:08, 12:09, 12:10, and eventually the clock gets to
12:58, 12:59, 1:00, and so on. The one's place of the minutes (the right-most digit)
counts 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and then repeats, and a circuit that counts in this
way is called a mod-10 counter. The ten's place of the minutes (second digit from the
right) counts 0, 1, 2, 3, 4, 5, and then repeats, which is called a mod-6 counter. The
hour counter counts 12, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, and repeats. The output from
each counter is a binary coded decimal (BCD) number that represents one of the
digits in the time, and BCD-to-Seven segment decoders are used to drive the seven
segment displays.
Thank you
Disclaimer:
This document is confidential and intended solely for the educational purpose of RMK Group of
Educational Institutions. If you have received this document through email in error, please notify the
system manager. This document contains proprietary information and is intended only to the
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Date: 30th August 2020

3 Pre Requisites (Course Name with Code) 8

4 Syllabus (With Subject Code, Name, LTPC details) 10

5 Course Outcomes (6) 12

12 Part B Qs (with K level and CO) 155

17 Prescribed Text Books & Reference Books 171

18 Mini Project 173

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 12

UNIT II COMBINATIONAL LOGIC 12

UNIT III SYNCHRONOUS SEQUENTIAL LOGIC 12

UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC 12

UNIT V MEMORY AND PROGRAMMABLE LOGIC 12

CO3 Analyze and Design Synchronous Sequential Circuits K4

CO4 Analyze and Design Asynchronous Sequential Circuits K4

CO5 Implement designs using Programmable Logic Devices K3

Knowledge Level Description

5 HDL Models 2 CO6 K3 PPT /

2 Online Quiz – Flip Flops 90

3 Games of Shift 108

4 Crossword Puzzle - Counters 132

Sl. No. Contents Page No.

Examples – for design of Synchronous Sequential

Sl. No. Contents Page No.

12 Serial In − Parallel Out shift register 91

Parallel In − Parallel Out shift register

14 Universal Shift Register 114

18 Ring Counters 136

19 Johnsons Counter 137

Definition of Sequential Circuits

A sequential circuit consists of a combinational circuit to which storage elements

Block diagram of a Sequential Circuit

The storage elements are devices capable of storing binary information.

Types of Sequential Circuits

1. Synchronous Sequential Circuit/ Clocked Sequential Circuit

2. Asynchronous Sequential Circuit/ Unclocked Sequential Circuit

1. Synchronous Sequential Circuit

A synchronous sequential circuit is a system whose behaviour can be defined

Synchronization is achieved by a timing device called a clock generator, which

Block diagram of Synchronous Sequential Circuit

Timing diagram of clock pulses

2. Asynchronous Sequential Circuit

Differences between Synchronous and Asynchronous

Memory Elements/ Storage Elements

The two storage elements are:

Differences between Latches and Flip Flops

Clock Response in Latches

Response to Positive level

Response to Negative level

The circuit will become active at negative level (i.e. level 0)

Clock Response in Flip Flops

Response to Positive Edge

Response to Negative Edge

3.1.1 SR LATCH WITH NOR GATES

Outputs Q and Q are normally the complement of each other.

Graphic Symbol Logic diagram

Truth table of NOR Function table of SR Latch with NOR gate

Working of SR Latch with NOR gate

When S=1, R=0 (Set state)

When S=0, R=0 (after S=1 & R=0)

When S=0, R=1 (Reset state)

When S=0, R=0 (after S=0 & R=1)

When S=1, R=1

This action produces an undefined next state.