DSDE 152

Digital System Design

Lecture 6: SD, ASM Chart,

Transition Map, Timing
Diagram
Spring 2021
Dr. Shawkat S. Khairullah
Department of Computer Engineering 1
University of Mosul
Simplest Circuits with Feedback
• Two inverters form a static memory cell
• Will hold value as long as it has power
applied
"1"

"stored value"
"0"

• How to get a new value into the memory cell?

• Selectively break feedback path
• Load new value into cell

"remember"
2
"load" "stored value"
"data"
Memory with Cross-coupled Gates

• Cross-coupled NOR gates

• Similar to inverter pair, with capability to force output to 0 (reset=1)
or 1 (set=1)
R Q
Q
R
S S Q'
• Cross-coupled NAND gates
• Similar to inverter pair, with capability to force output to 0 (reset=0)
or 1 (set=0)

S' Q

Q 3
S'
Q'
R' R'
 Latches and Flip-Flops
• Binary cells capable of storing 1 bit of information.
• Generates one of two possible stable states.
• Two outputs labeled Q and Q’.
• One or more inputs.
• These sequential devices differ in the way their outputs are
changed:
• The output of a latch changes independent of a clocking signal.
• The output of a flip–flop changes at specific times determined by
a clocking signal.

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S-R Latch

• SR latch based on NOR gates.

• The S input sets the Q output to 1 while R reset it to 0.
• When R=S=0 then the output keeps the previous value.
• When R=S=1 then Q=Q’=0, and the latch may go to an
unpredictable next state.

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To investigate the properties of
these latch circuit we utilize the
following analysis tools
• 1- Circuit delay module
• 2- Characteristic equation
• 3- Characteristic or present state/next state table
• 4- State diagram
• 5- ASM chart
• 6- Karnaugh map
• 7- Transition map
• 8- Flow map
• 9- Timing diagram 6
 1- Circuit delay module
R (reset)
Q
S Q

R Q
Q
S (set)

S(set)
X

q=Q after ∆t
Q ∆t q
R (reset) (delay)
Q(t) q(t)
Excitation input Delay output or t
(present state ∆t
or (next state
output signal( output signal) 7

Delay model for a S-R cross-coupled NOR gate latch

2- Characteristic equation
(next state equation)
X  S q S(set)
X

Q  S qR
Q ∆t q
Q  S qR R (reset) (delay)

Q  ( S  q)  R
Q  S RqR
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 HW1
Analyze the S-R cross-coupled NAND gate latch to find
1-Delay model
2- Characteristic equation

~S S
Q Q
S Q

R Q

Q
~R R

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 3- Characteristic or (present
state/next state) table
present External next state
state (PS) input (NS) output present state X  S q
output signals signal condition of comment After ∆t
signal q
X  S Q
q S R Q
0 0 0 0 Stable Reset state (Q=0) 1
0 0 1 0 Stable Reset state (Q=0) 1
0 1 0 1 Unstable Set state (Q=1) 0
0 1 1 0 Stable Normally not allowed 0
1 0 0 1 Stable Set state (Q=1) 0
1 0 1 0 Unstable Reset state (Q=0) 1
1 1 0 1 Stable Set state (Q=1) 0
10
1 1 1 0 Unstable Normally not allowed 0

Q  S RqR
 4- State diagram
present External next state
state (PS) input (NS) output
output signals signal
SR
signal
q S R Q SR 01
State a State b SR
00 11
00
0 0 0 0 01
10
11
0 0 1 0
a b
0 1 0 1 0 1
0 1 1 0
1 0 0 1
SR State=q
1 0 1 0 State transition from 10
state a to state b
1 1 0 1
1 1 1 0
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State diagram for a S-R cross-coupled NOR gate latch
 5- ASM chart
An ASM chart has an entry point and is constructed with blocks. A block is
constucted with the following type of symbols .

One state box. The state box has a

name and lists outputs that are asserted
when the system is in that state. These
outputs are called synchronous or
Moore type outputs.
Optional decision box(es). A decision
box may be conditioned on a signal or a
test of some kind.
Optional conditional output
box(es). Such an output box indicates
outputs that are conditionally asserted.

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Certain Rules
• The drawing of ASM charts must follow certain necessary rules:

• The entrance paths to an ASM block lead to only one state box .

• Of 'N' possible exit paths, for each possible valid input

combination, only one exit path can be followed, that is there is
only one valid next state.

• No feedback internal to a state box is allowed. The following

diagram indicates valid and invalid cases.

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 5- ASM chart
SR ASM 0 State=q
block for a
SR 01
SR State
00 11 State box
00
01
10
11
a b
0 1 0
S.R Boolean expression
representing condition
SR 1
Exit path for a
10 true condition Exit path for a
true condition
1
b

Decision
1
R box

0 14
ASM chart for a S-R cross-coupled NOR gate latch
 6- Karnaugh map
SR
next state q 00 01 11 10
present External
state (PS) input (NS) output Q=
output signals signal 0 0 0 0 1
signal
q S R Q
1 1 01 0 1
0 0 0 0
0 0 1 0 Karnaugh map for a S-R NOR gate latch
0 1 0 1
SR
0 1 1 0 q 00 01 11 10
1 0 0 1 Q=
0 0 0 0 1
1 0 1 0
1 1 0 1
1 1 0 0 1
1 1 1 0
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Karnaugh map for a S-R NOR gate latch
with stable state indented
7- Transition map
• Transition map can be used to analyze the response of a circuit to
its inputs changes.
• Transition map is usually obtained from Karnaugh map.
• When external input conditions change in the transition map the
latch always ends up in a stable state.
1-When external input conditions change and q does not change, a
horizontal movement in the transition map occurs during the
time interval ∆t.
qSR=001→000
SR
q 00 01 11 10
NS=
0

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1
7- Transition map (Cont.)
2-When external input conditions change and q change, the
following movement in the transition map take place during the
time interval ∆t:
A) a horizontal movement from the stable present state value to
an unstable present state value occurs.
B) a vertical movement from the unstable present state value to a
stable present state value occurs.
• qSR=001→110
→ qSR=010 (horizontal movement)
→ qSR=110 (vertical movement)

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8- Flow map
• Like the transition map, the flow map for a circuit is usually
obtained from Karnaugh map.
• The same information in the state chart represented in tabular
format is called a flow table or flow map.
• State values are used in the cells of Karnaugh map.
• qSR=110 →SR=00 →SR=01
1 2

SR SR
q 00 01 11 10 q 00 01 11 10
NS= NS=
0 a a a b 0 a a2 a b

1 b a a b 1 b 1 a a b
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 race condition
• A race condition or race hazard is a flaw in an electronic system or
process whereby the output and/or result of the process is
unexpectedly and critically dependent on the sequence or timing of
other events.

• The term originates with the idea of two signals racing each other
to influence the output first.

• A typical example of a race condition may occur in a system of logic

gates, where inputs vary. If a particular output depends on the state
of the inputs, it may only be defined for steady-state signals.

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A- critical race
 A critical race occurs when the order in which internal
variables are changed determines the eventual state that
the state machine will end up in.
 SR=11→00
1
qSR=011→ qSR=001 →
2
qSR=000 (red path)
3
qSR=011→ qSR=110 →
4
qSR=100 (blue path)
SR
q 00 01 11 10
NS=
0 a a a b
2 1

3 20
1 b a a b
4
B- non-critical race
 A non-critical race occurs when moving to a desired state
means that more than one internal state variable must be
changed at once, but no matter in what order these
internal state variables change, the resultant state will be
the same.
 SR=01→10
1 2

3 qSR=000 →
qSR=001→ 4 qSR=110 (red path)

qSR=001→ qSR=01100 → qSR=110

11 (blue
10 path)
SR
q 01
NS=
0 a1 a 3
a b
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1 b a a 2
b4
Thank you

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