ECE 2300

Digital Logic & Computer Organization

Spring 2018

Sequential Logic:
Clocks
Latches
Flip-Flops

Lecture 6: 1
 Announcements

• Lab 3 will be released tonight

– Including a tutorial on Quartus/Verilog

• Late submission policy

– Email ece2300-staff@csl.cornell.edu before the
deadline to request slip days

Lecture 6: 2
 Example: Logic Function using Mux
• Use a 4:1 mux to implement function F

A B Cin
C S Cout
F
0 0 0 0 1
0 0 1 1 1 1 0

0 1 0 1 1 C’ 1
4:1 F
0 1 1 0 0 C 2 MUX

1 0 0 1 0 0 3

1 0 1 0 1 S1 S0

1 1 0 0 0
A B
1 1 1 1 0

Lecture 6: 3
 Combinational vs. Sequential Circuits
Combinational Circuit Sequential Circuit
inputs outputs
inputs Combinational outputs Combinational
Logic Logic

State

• Combinational • Sequential
– Output depends only on – Output depends on current
current inputs inputs plus past history
– Includes memory

Lecture 6: 4
 Sequential Circuits
• Outputs depend on inputs and state variables

• The state variables embody the past

– Storage elements hold the state variables

• A clock periodically advances the circuit

Lecture 6: 5
 Bistable Element
• Basic storage element
• Inverters with outputs connected to inputs

QN

• What does the circuit do?

Lecture 6: 6
 Bistable = Two Stable States
• Bistable element stores a “given” value
indefinitely (as long as powered)

0 1 1 0
Q Q

QN QN
1 0 0 1

How to change the stored value?

Lecture 6: 7
 Revisit NOR and NAND Gates
• Null elements for NOR and NAND
X X 1
0
1 0

• Implement NOT with NAND / NOR

X X X’
X’
0 1

Lecture 6: 8
 S-R Latch (Set-Reset Latch)
(RESET)
R Q
(SET)
S QN

Truth table?
Set (S) and Reset (R) inputs
allow (re)setting stored value S R Qnext
Hold state
0 0
Reset
Qnext is new value of Q when 0 1
R or S changes Set
1 0
1 1

Lecture 6: 9
 S-R Latch (Set-Reset Latch)
(RESET)
R Q
(SET) S Q
S QN
R QN

S R R’•S R’•Q Qnext

0 0 0 Q Q
Boolean expression for Qnext
0 1 0 0 0
in terms of R, S, and Q:
1 0 1 Q 1
Qnext = (R + QN)’
1 1 0 0 0
= (R + (S + Q)’)’
= R’•(S + Q) When S=0 and R=0, it holds
= R’•S + R’•Q (latches) its previous state
Lecture 6: 10
 Instability (Avoid SR=11!)
• SR=11 may create theoretical instability
1. When SR=11 à Q=QN=0
2. If inputs subsequently change to SR=00, output may
be undefined

(RESET)
R Q
(SET)
S QN

Lecture 6: 11
 D Latch
• D latch: builds on S-R latch where S and R
cannot be both 1
– Output “follows” input

• D latch captures input data (what to set) when

certain condition holds (when to set)

• Operates in two modes

– Open (or transparent): input flows through to output
– Closed (or opaque): output does not change

Lecture 6: 12
 D Latch
• When C is enabled, Q output follows D input
• When C is disabled, Q output retains last state
D
R (RESET)
Q

C D Q
C QN
QN
S (SET)

C D R S Q QN
1 0 1 0 0 1
1 1 0 1 1 0
0 X 0 0 Last Q Last QN
Lecture 6: 13
 Multi-bit Latch
• Simultaneously latches multiple bits
• “Latch” may refer to 1 bit latch or multi-bit one
D1 D Q Q1

D2 D Q Q2

D3 D Q Q3

D4 D Q Q4

C C Lecture 6: 14
 Clock
• An input to a sequential circuit that changes output and
state values at a predetermined rate

Positive Negative
(rising) (falling)
edge edge

Clock Waveform
• Triggering edge: Transition of the clock (LàH or HàL)
that captures input data
– We mostly use positive edge as triggering edge in this class
– Clock tick: Occurrence of a triggering edge
Lecture 6: 15
 Clock Period and Frequency

• Clock Period (cycle time): Time between successive

transitions in the same direction (LàH or HàL)
– e.g., 1ms, 2ns, 250ps
• Clock Frequency: 1/period
– e.g., 1kHz, 500MHz, 4GHz

Lecture 6: 16
 D Latch Timing
D Latch

D D Q
Q
C

CLK

CLK (open) (closed) (open) (closed)

D
Q

Lecture 6: 17
 Flip-Flop
• Samples input on triggering edge of clock
– Rising edge à positive edge-triggered flip-flop
– Falling edge à negative edge-triggered flip-flop

• D flip-flop: Two D latches back-to-back

Lecture 6: 18
 D Flip-Flop
L1 L2
D D
Q
Q D Q
C C

CLK CLKL1 CLKL2

D CLK Q
0 0 D Q
1 1
CLK
X 0 Last Q
X 1 Last Q

• Copies D to Q on the rising edge of the clock

Lecture 6: 19
 D Flip-Flop Timing
L1 L2
D D Q1 Q
Q D Q
C C

CLK CLKL1 CLKL2

CLK
CLKL1 (L1 open) (L1 closed) (L1 open) (L1 closed)
CLKL2 (L2 closed) (L2 open) (L2 closed) (L2 open)

D
Q1
Q

Lecture 6: 20
 Register
• Collection of FFs operating off common clock
• A single D flip-flop is a 1-bit register
D1 D Q Q1

CLK

D2 D Q Q2

CLK

D3 D Q Q3

CLK

D4 D Q Q4

CLK CLK
Lecture 6: 21
 Before Next Class
• H&H 4.1-4.5 (skip VHDL parts), 5.4

Next Time

Counters
Shift Registers
Verilog

Lecture 6: 22