TOPIC:

LATCHES and FLIP-FLOPS

CS118 1
 S-R Latch

▪ Latches are digital circuits that store a single bit of information and
hold its value until it is updated by new input signals. They are used in
digitalS systems
R Q Q' as temporary storage elements to store binary
No change. Latch
information.
0 0 NC Latches
NC
remainedbe
can implemented
in present state. using various digital logic
gates,1 such
0 1as AND,
0 OR, NOT, NAND, and NOR gates.
Latch SET.

▪ There1 are
0 1 0 1 Latch RESET.
1
two
0
types
0
ofInvalid
latches:
condition.
1. S-R (Set-Reset) Latches: S-R latches are the simplest form of
latches and are implemented using two inputs: S (Set) and R (Reset).
The S input sets the output to 1, while the R input resets the output to
0. When both S and R are at 1, the latch is said to be in an
“undefined” state.

2. D (Data) Latches: D latches are also known as transparent latches

and are implemented using two inputs: D (Data) and a clock signal.
The output of the latch follows the input at the D terminal as long as
the clock signal is high. When the clock signal goes low, the output of
the latch is stored and held until the next rising edge of the clock.
 S-R Latch

SR (Set-Reset)
S R Q
Latch
Q'
– They are also known as preset and clear
states. The SR latch formsNothe basic
change. building blocks of all other types of
Latch
0 0 NC NC
flip-flops. remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
SR Latch
1
is1 a circuit
0
with:
0 Invalid condition.
(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
(ii) 2 inputs, S for SET and R for RESET.
(iii) 2 output Q, Q’.

S Q

R Q'
 S-R Latch

S R Q Q'
Under normal conditions, both the input
No change. Latch remains 0. The following is the
0 0 NC NC
RS Latch with NAND gates:
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R Latch

Case-1: S’=R’=1 (S=R=0) –

If Q = 1,SQ RandQR’ inputs
Q'
for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for
No 2nd NAND
change. Latchgate are 0 and 1 respectively.
0 0 NC NC
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R Latch

Case-2: S’=0, R’=1 (S=1, R=0) –

As S’=0,S the
R
output
Q Q'
of 1st NAND gate, Q = 1(SET state). In 2nd NAND
gate, as Q and R’ inputs are 1, Q’=0.
No change. Latch
0 0 NC NC
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R Latch

Case-3: S’= 1, R’= 0 (S=0, R=1) –

As R’=0,S the
R
output
Q Q'
of 2nd NAND gate, Q’ = 1. In 1st NAND gate, as Q
and S’ inputs are 1, Q=0(RESET state).
No change. Latch
0 0 NC NC
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R Latch

Case-4: S’= R’= 0 (S=R=1) –

When S=R=1,
S R bothQ'Q and Q’ becomes 1 which is not allowed. So, the
Q
input condition
0 0 NC is prohibited.
NC No change. Latch
remained in present state.
The SR 1Latch
0 using
1 0 NOR gate is SET.
Latch shown below:
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R Latch

Gated SR Latch –
A GatedSSRR latchQ isQ'a SR latch with enable input which works when
enable is0 1 0and
NCretain
NC the No
previous
change. state
Latch when enable is 0.
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R Latch

Gated D Latch –
D latch is similar to SR latch with some modifications made. Here, the
inputs are
S complements
R Q Q' of each other. The letter in the D latch stands
for “data”
0 as
0 this
NC latch
NC stores single Latch
No change. bit temporarily.
remained in present state.
The design
1 0
of D1
latch
0
with Enable signal is given below:
Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

Enable D Q(n) Q(n+1) STATE

1 0 x 0 RESET

1 1 x 1 SET

0 x x Q(n) No Chang

As the output is same as the input D, D latch is also called as Transparent

Latch.
 S-R Latch

Advantages of Latches:
S R Q Q'
1. Easy to Implement: Latches are simple digital circuits that can be
No change. Latch
easily
0 implemented
0 NC NC
remained basic
using digital
in present state.logic gates.
1 0 1 0 Latch SET.
2. Low0 Power
1 0 1 LatchLatches
Consumption: RESET. consume less power compared
1 1 0 0 Invalid condition.
to other sequential circuits such as flip-flops.

3. High Speed: Latches can operate at high speeds, making them

suitable for use in high-speed digital systems.

4. Low Cost: Latches are inexpensive to manufacture and can be used

in low-cost digital systems.

5. Versatility: Latches can be used for various applications, such as

data storage, control circuits, and flip-flop circuits.
 S-R Latch

Disadvantages of Latches:
S R Q Q'
1. No Clock:
0 0 NC Latches
NC doNonot have
change. a clock signal to synchronize their
Latch
remained in present state.
operations,
1 0 1
making
0
their Latch
behavior
SET.
unpredictable.
0 1 0 1 Latch RESET.
2. Unstable
1 1 State:
0 0 Latches cancondition.
Invalid sometimes
enter into an unstable state
when both inputs are at 1. This can result in unexpected behavior in
the digital system.

3. Complex Timing: The timing of latches can be complex and difficult

to specify, making them less suitable for real-time control
applications.
 FLIP-FLOP

▪ A flip flop in digital electronics is a circuit with two stable states that
can be used to store binary data. The stored data can be changed by
S R varying
applying Q Q' inputs. Flip-flops and latches are fundamental
No change. Latch
building
0 0blocks
NC NC of remained
digital electronics
in present state. systems used in computers,
communications,
1 0 1 0 and many Latchother
SET. types of systems. Both are used
as data
0 storage
1 0 elements.
1 Latch RESET.
1 1 0 0 Invalid condition.
A flip flop has two outputs as shown-

A flip flop can maintain a binary state for an unlimited period of time as
long as-Power is supplied to the circuit.
Or until it is directed by an input signal to switch states.
 S-R FLIP-FLOP

Flip Flops Types-

Flip flops SareR of Q Q'

different types depending on how their inputs and clock
No change. Latch
pulses cause
0 0 transition
NC NC between
remained intwo states.
present state.
There are1 4 basic
0 1 types
0 of flip Latch
flops-SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R FLIP-FLOP

There are following two methods for constructing a SR flip flop-

S RNOR
1. By using Q latch
Q'
No change. Latch
2. By using
0 0 NAND
NC NClatchremained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R FLIP-FLOP

1. Construction of SR Flip Flop By Using NOR Latch-

S Rof constructing
This method Q Q' SR Flip Flop uses-1. NOR latch 2. Two AND
No change. Latch
gates 0 0 NC NC
remained in present state.
1 0 1 0 Latch SET.
Logic Circuit-The
0 1 0 logic
1 circuit forRESET.
Latch SR Flip Flop constructed using NOR
1 1 0 0 Invalid condition.
latch is as shown below-
 S-R FLIP-FLOP

2. Construction of SR Flip Flop By Using NAND Latch-

S Rof constructing
This method Q Q' SR Flip Flop uses- 1. NAND latch 2. Two
No change. Latch
NAND gates
0 0 NC NC
remained in present state.
1 0 1 0 Latch SET.
Logic Circuit-
0 1 The
0 logic
1 circuit forRESET.
Latch SR Flip Flop constructed using NAND
1 1 0 0 Invalid condition.
latch is as shown below-
 S-R FLIP-FLOP

Logic Symbol-

The logicSsymbol
R Q forQ'SR Flip Flop is as shown below-
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R FLIP-FLOP

Truth Table- The truth table for SR Flip Flop is as shown below-

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R FLIP-FLOP

The above truth table may be reduced as-

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 S-R FLIP-FLOP

Characteristic Equation-

Draw a k Smap
R using
Q Q'
the above truth table-
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

From here-
Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )

Qn+1 = S + QnR’
 D FLIP-FLOP

D Flip Flop

D flip flopSis Ran electronic

Q Q' devices that is known as “delay flip flop” or “data
No change. Latch
flip flop” which
0 0 is NCused
NC to store
remainedsingle bitstate.
in present of data.
1 0 1 0 Latch SET.
• D flip 0flops
1 are
0 synchronous
1 Latchor asynchronous.
RESET. The clock signal
1 1 0 0 Invalid condition.
required for the synchronous version of D flip flops but not for the
asynchronous one.
• The D flip flop has two inputs, data and clock input which controls the
flip flop. when clock input is high, the data is transferred to the output of
the flip flop and when the clock input is low, the output of the flip flop is
held in its previous state.
 D FLIP-FLOP

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

Basically, such type of flip flop is a modification of clocked RS flip flop

gates from a basic Latch flip flop, and NOR gates modify it into a clock RS
flip flop. The D input goes directly to the S input and its complement
through the NOT gate, is applied to the R input.
 D FLIP-FLOP

Working of D Flip Flop: D flip flop consist of a single input D and two
outputs (Q and Q’).
The basicS working
R Q ofQ'D Flip Flop is as follows:
No change. Latch
• When the0 clock
0 NC signal
NC
remained the
is low, flip flop
in present holds its current state and
state.
ignores1the0 D input.
1 0 Latch SET.
• When the0 clock
1 0 signal
1 is high,
Latchthe flip flop samples and stores D input.
RESET.
1 1
• The value that0was0 previously
Invalid condition.
fed into the D input is reflected at the flip
flop’s Q output.
• If D = 0 then Q will be 0.
• If D = 1 then Q will be 1.
The Q’ output of the flip flop is
complemented by the Q output.
• If Q = 0 then Q’ will be 1.
• If Q = 1 then Q’ will be 0.
 D FLIP-FLOP

Characteristic Table of D Flip Flop

The characteristic table of the D flip flop displays the behavior of the flip
flop for each
S Rcombination
Q Q' of input and current state. The characteristic
table for a0 D 0flipNC
flopNC
is as follows.
No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

• D is the input, and Q is current state, Qn + 1 is the next state outputs.

• Qn+1 will always be zero when D is 0, irrespective of current state of flip
flop.
• When the input of the flip flop is 1, next state of flip flop will always be
1, regardless of the current state of flip flop.
 D FLIP-FLOP

D Flip Flop Excitation Table

Here, S R Q Q'
Qn represents
0 0 the
NC current
NC state of theLatch
No change. flip flop, and Dn represents the
remained in present state.
current input
1 0
of the
1
flip
0
flop. Where as Qn+1 represents the next state of
Latch SET.
the flipflop.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
• When the Qn is 0 and the Dn is also 0, then the Qn+1 becomes
0. This situation explains the condition of “hold” state.
• When the Qn is 0 but Dn is 1, then the Qn+1 becomes 1. This
situation explains the condition of “reset” state.
• When the Qn is 1 but Dn is 0, then the Qn+1 becomes 0. This
situation explains the condition of “hold” state.
• When the Qn is 1 and the Dn is also 1, then the Qn+1 becomes
1. This situation explains the condition of “reset” state.
 D FLIP-FLOP

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 D FLIP-FLOP

Advantages of D Flip Flop

• D flip flop
S is
R very
Q simple
Q' to design.
• The computation
0 0 NC speed
NC ofNoDchange.
flip flop is very fast compared to other flip
Latch
flops. 1 0 1 0 remained in present state.
Latch SET.
• D flip flop
0 requires
1 0 1very fewLatch
components
RESET. to design which makes it
simple to1 understand.
1 0 0 Invalid condition.

Disadvantages of D Flip Flop

• D flip flops are glitch prone. When input varies fast, flip flop output may
glitch. Digital circuit glitches are hard to identify and fix.
 J-K FLIP-FLOP

JK FLIP FLOP
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has
the following
S Rswitching
Q Q' problems:
1. When0 Set 0 'S'
NCandNCResetNo'R'
change.
inputsLatch
are set to 0, this condition is always
remained in present state.
avoided.
1 0 1 0 Latch SET.
2. When0 the 1 Set
0 or1Reset input
Latch changes
RESET. their state while the enable
input 1is 1,
1 the
0 incorrect
0 latching action occurs.
Invalid condition.

The JK Flip Flop removes these two drawbacks of SR Flip Flop.

• The JK Flip Flop is a gated SR flip-flop having the addition of a clock

input circuitry. The invalid or illegal output condition occurs when both
of the inputs are set to 1 and are prevented by the addition of a clock
input circuit. So, the JK flip-flop has four possible input combinations,
i.e., 1, 0, "no change" and "toggle". The symbol of JK flip flop is the
same as SR Bistable Latch except for the addition of a clock input.
 J-K FLIP-FLOP

Block Diagram:

• The JK SFlipR Flop

Q isQ'a gated SR flip-flop having the addition of a clock
input circuitry.
0 0 NC TheNCinvalid No
orchange.
illegal Latch
output condition occurs when both of
remained in present state.
the inputs
1 are
0 set to
1 0 1 and are prevented
Latch SET. by the addition of a clock input
circuit. So,
0 1the0JK flip-flop
1 has
Latchfour possible input combinations, i.e., 1,
RESET.
0, "no change"
1 1 0 and0 "toggle". The
Invalid symbol of JK flip flop is the same
condition.

as SR Bistable Latch except for the addition of a clock input.

 J-K FLIP-FLOP

Circuit Diagram:

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 J-K FLIP-FLOP

Circuit Diagram:

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 J-K FLIP-FLOP

Circuit Diagram:

In SR flipSflop,
R both
Q the
Q' inputs 'S' and 'R' are replaced by two inputs J and
K. It means
0 the J and
0 NC No equates
NCK input change. Latch
to S and R, respectively.
remained in present state.
1 0 1 0 Latch SET.
The two 2-input
0 1 AND
0 1 gates are replaced
Latch RESET. by two 3-input NAND gates. The
third input1 of1each
0 gate
0 is connected to the outputs at Q and Q'.
Invalid condition.

The cross-coupling of the SR flip-flop permits the previous invalid

condition of (S = "1", R = "1") to be used to produce the "toggle action" as
the two inputs are now interlocked.

• If the circuit is "set", the J input is interrupted from the "0" position of Q'
through the lower NAND gate. If the circuit is "RESET", K input is
interrupted from 0 positions of Q through the upper NAND gate. Since Q
and Q' are always different, we can use them to control the input. When
both inputs 'J' and 'K' are set to 1, the JK toggles the flip flop as per the
given truth table.
 J-K FLIP-FLOP

Truth Table:

JK flip flop
S Rcomprises
Q Q' four possible combinations of inputs: J=0, K=0;
J=0, K=1;0 J=1,
0 K=0;
NC NC No change.
andremained
J=1, K=1. Latch input combinations determine
These
in present state.
the behavior
1 0 of flip
1 flop
0 and its output.
Latch SET.
0 1 0 1 Latch RESET.
1. J=0, K=0:
1 1 In0this0state, flip flop
Invalid retains
its preceding state. It neither
condition.

sets nor resets itself, making it stable.

2. J=0, K=1: This input combination forces flip flop to reset, resulting in
Q=0 and Q̅ =1. It is often referred to as the “reset” state.
3. J=1, K=0: Here, flip flop resides in the set mode, causing Q=1 and
Q̅ =0. It is known as the “set” state.
4. J=1, K=1: This combination toggles flip flop. If the previous state is
Q=0, it switches to Q=1 and vice versa. This makes it valuable for
frequency division and data storage applications.
 J-K FLIP-FLOP

JK Flip Flop Truth Table

JK flip flop truth table illustrates the relationship between the inputs (J
and K) andS the
R outputs
Q Q' (Q and Q̅ ) of flip flop. Here is JK flip flop truth
table: 0 0 NC NC remained No change. Latch
in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 J-K FLIP-FLOP

JK Flip-Flop reduced Table

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 J-K FLIP-FLOP

Characteristic Equation-

Draw a k Smap
R using
Q the above truth table-
Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

From here-
Qn+1 = Q’n (JK + JK’) + Qn (J’K’ + JK’)
Qn+1 = Q’nJ + QnK’
 T FLIP-FLOP

T flip flop is similar to JK flip flop. Just tie both J and K inputs together to
get a T Flip flop. Just like the D flip flop, it has only one external input
along withS a Rclock.
Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
 T FLIP-FLOP
T Flip-Flop Working
Let us take a look at the possible cases and write it down in our truth table.
The clock isS always
R Q 1, Q'
so only two cases are possible where T can be high or
low. 0 0 NC NC No change. Latch
Case 1: T=0 remained in present state.
1 0 1 0 Latch SET.
Gate1 = 0, Gate2
0 1
=
0
0, Gate3/Q(n+1)
1
= Q, Gate4/Q(n+1)’ = Q’
Latch RESET.
Note: 1 1 0 0 Invalid condition.
Since one of the inputs to Gate1 and gate2 is 0 and both are AND gates; the
output of gate1 and gate2 will be equal to 0 irrespective of other inputs as per
the property of AND gates
Gate3 = (0+Q’)’ = (Q’)’ = Q
Gate4 = (0+Q)’ = (Q)’ = Q’
Case 2: T=1
Gate1 = Q, Gate2 = Q’, Gate4/Q(n+1)’ = 0, Gate3/Q(n+1) = Q’
Note:
Since one input of both gate1 and gate2 is 0 and both gates are AND gates,
the output of both gates will be equal to the third input.
Gate4 = (Q’+Q)’ = 1’ = 0
Gate3 = (Q+0)’ = Q’
 T FLIP-FLOP

T Flip-Flop Truth Table

S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.
We will use this truth table to write the characteristics table for the T flip flop.
In the truth table, you can see there is only one input T and one output
Q(n+1). But in the characteristics table, you will see there are two inputs T
and Qn, and one output Q(n+1).

From the logic diagram above it is clear that Qn and Qn’ are two
complementary outputs that also act as inputs for Gate3 and Gate4 hence
we will consider Qn i.e the present state of Flip flop as input and Q(n+1) i.e.
the next state as output.
 T FLIP-FLOP

After writing the characteristic table, we will draw a 2-variable K-map to

derive the characteristic equation.
S R Q Q'
0 0 NC NC No change. Latch
remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

From the K-map you get 2 pairs. On solving both we get the following
characteristic equation:
Q(n+1) = TQn’ + T’Qn = T XOR Qn
 T FLIP-FLOP

Advantages
There are several advantages to using a T flip flop. Some of them are listed
below: S R Q Q'
0 input:
0 NC The No change. Latch
NC T flip-flop
1. Single has astate.
remained in present single input that can be used to
toggle1 between
0 1 two
0 states,Latch
which
SET. makes it simpler to use and easier to
0 1with
interface 0 other
1 digitalLatch RESET.
circuits.
1 1 0 0
2. No invalid states: TheInvalid condition.
T flip-flop does not have any invalid states,
which helps to avoid unpredictable behavior in digital systems.
3. Reduced power consumption: The T flip-flop consumes less power
than other types of flip-flops, making it more energy-efficient.
4. Bi-stable operation: Like other flip-flops, the T flip-flop has a bi-stable
operation, which means that it can hold a state indefinitely until it is
changed by an input signal.
5. Easy to implement: The T flip-flop can be easily implemented using
simple logic gates, which makes it a cost-effective option for digital
systems.
 T FLIP-FLOP

Limitations
S R Q Q'
Apart from several advantages, there are some limitations associated with
0 Some
0 NC ofNC No change. Latch
T flip-flops. them are listed below:
remained in present state.
1. Inverted1 0 output:
1 0 The output
Latchof a T flip-flop is inverted from the input,
SET.
which0 can1 be0 confusing
1 Latch
and RESET.
make it difficult to design sequential logic
1 1 0 0 Invalid condition.
circuits.
2. Limited functionality: The T flip-flop can only store a single bit of
information and cannot perform more complex operations like addition
or multiplication.
3. Glitches: The T flip-flop is vulnerable to glitches and noise on the input
signal, which can cause it to toggle unexpectedly and lead to
unpredictable behavior in digital systems.
4. Propagation delay: Like other flip-flops, the T flip-flop has a
propagation delay, which can lead to timing issues in digital systems
with tight timing constraints.
 T FLIP-FLOP

Applications
Some of the applications of T flip flop in real-world includes:
S R Q Q'
1. Frequency division: The T flip-flop can be used to divide the
0 0 ofNCa clock
NC No change. Latch
frequency remained by
signal two, making
in present state. it useful in applications such
as digital
1 0 clocks
1 and frequency
0 synthesizers.
Latch SET.
0 1
2. Frequency 0 1
multiplication:Latch RESET.
The T flip-flop can also be used to multiply
1 1 0 0 Invalid condition.
the frequency of a clock signal by two, making it useful in applications
such as frequency synthesizers and digital signal processing.
3. Data storage: The T flip-flop can be used to store a single bit of data,
making it useful in applications such as shift registers and memory
devices.
4. Counters: The T flip-flop can be used in conjunction with other digital
logic gates to create binary counters that can count up or down
depending on the design. This makes them useful in real-time
applications such as timers and clocks.